diff options
Diffstat (limited to 'arch/arm/mm/cache-l2x0.c')
-rw-r--r-- | arch/arm/mm/cache-l2x0.c | 36 |
1 files changed, 26 insertions, 10 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index cb8fc6573b1..1a14d18e571 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c | |||
@@ -42,6 +42,27 @@ static inline void cache_sync(void) | |||
42 | cache_wait(base + L2X0_CACHE_SYNC, 1); | 42 | cache_wait(base + L2X0_CACHE_SYNC, 1); |
43 | } | 43 | } |
44 | 44 | ||
45 | static inline void l2x0_clean_line(unsigned long addr) | ||
46 | { | ||
47 | void __iomem *base = l2x0_base; | ||
48 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); | ||
49 | writel(addr, base + L2X0_CLEAN_LINE_PA); | ||
50 | } | ||
51 | |||
52 | static inline void l2x0_inv_line(unsigned long addr) | ||
53 | { | ||
54 | void __iomem *base = l2x0_base; | ||
55 | cache_wait(base + L2X0_INV_LINE_PA, 1); | ||
56 | writel(addr, base + L2X0_INV_LINE_PA); | ||
57 | } | ||
58 | |||
59 | static inline void l2x0_flush_line(unsigned long addr) | ||
60 | { | ||
61 | void __iomem *base = l2x0_base; | ||
62 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); | ||
63 | writel(addr, base + L2X0_CLEAN_INV_LINE_PA); | ||
64 | } | ||
65 | |||
45 | static inline void l2x0_inv_all(void) | 66 | static inline void l2x0_inv_all(void) |
46 | { | 67 | { |
47 | unsigned long flags; | 68 | unsigned long flags; |
@@ -62,23 +83,20 @@ static void l2x0_inv_range(unsigned long start, unsigned long end) | |||
62 | spin_lock_irqsave(&l2x0_lock, flags); | 83 | spin_lock_irqsave(&l2x0_lock, flags); |
63 | if (start & (CACHE_LINE_SIZE - 1)) { | 84 | if (start & (CACHE_LINE_SIZE - 1)) { |
64 | start &= ~(CACHE_LINE_SIZE - 1); | 85 | start &= ~(CACHE_LINE_SIZE - 1); |
65 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); | 86 | l2x0_flush_line(start); |
66 | writel(start, base + L2X0_CLEAN_INV_LINE_PA); | ||
67 | start += CACHE_LINE_SIZE; | 87 | start += CACHE_LINE_SIZE; |
68 | } | 88 | } |
69 | 89 | ||
70 | if (end & (CACHE_LINE_SIZE - 1)) { | 90 | if (end & (CACHE_LINE_SIZE - 1)) { |
71 | end &= ~(CACHE_LINE_SIZE - 1); | 91 | end &= ~(CACHE_LINE_SIZE - 1); |
72 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); | 92 | l2x0_flush_line(end); |
73 | writel(end, base + L2X0_CLEAN_INV_LINE_PA); | ||
74 | } | 93 | } |
75 | 94 | ||
76 | while (start < end) { | 95 | while (start < end) { |
77 | unsigned long blk_end = start + min(end - start, 4096UL); | 96 | unsigned long blk_end = start + min(end - start, 4096UL); |
78 | 97 | ||
79 | while (start < blk_end) { | 98 | while (start < blk_end) { |
80 | cache_wait(base + L2X0_INV_LINE_PA, 1); | 99 | l2x0_inv_line(start); |
81 | writel(start, base + L2X0_INV_LINE_PA); | ||
82 | start += CACHE_LINE_SIZE; | 100 | start += CACHE_LINE_SIZE; |
83 | } | 101 | } |
84 | 102 | ||
@@ -103,8 +121,7 @@ static void l2x0_clean_range(unsigned long start, unsigned long end) | |||
103 | unsigned long blk_end = start + min(end - start, 4096UL); | 121 | unsigned long blk_end = start + min(end - start, 4096UL); |
104 | 122 | ||
105 | while (start < blk_end) { | 123 | while (start < blk_end) { |
106 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); | 124 | l2x0_clean_line(start); |
107 | writel(start, base + L2X0_CLEAN_LINE_PA); | ||
108 | start += CACHE_LINE_SIZE; | 125 | start += CACHE_LINE_SIZE; |
109 | } | 126 | } |
110 | 127 | ||
@@ -129,8 +146,7 @@ static void l2x0_flush_range(unsigned long start, unsigned long end) | |||
129 | unsigned long blk_end = start + min(end - start, 4096UL); | 146 | unsigned long blk_end = start + min(end - start, 4096UL); |
130 | 147 | ||
131 | while (start < blk_end) { | 148 | while (start < blk_end) { |
132 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); | 149 | l2x0_flush_line(start); |
133 | writel(start, base + L2X0_CLEAN_INV_LINE_PA); | ||
134 | start += CACHE_LINE_SIZE; | 150 | start += CACHE_LINE_SIZE; |
135 | } | 151 | } |
136 | 152 | ||