1 files changed, 21 insertions, 1 deletions

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c4ed9f93f64..33027301639 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -754,7 +754,8 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 config CACHE_L2X0
         bool "Enable the L2x0 outer cache controller"
         depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4
+                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
+                   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
         default y
         select OUTER_CACHE
         help
@@ -781,3 +782,22 @@ config ARM_L1_CACHE_SHIFT
         int
         default 6 if ARM_L1_CACHE_SHIFT_6
         default 5
+
+config ARM_DMA_MEM_BUFFERABLE
+        bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7
+        default y if CPU_V6 || CPU_V7
+        help
+          Historically, the kernel has used strongly ordered mappings to
+          provide DMA coherent memory.  With the advent of ARMv7, mapping
+          memory with differing types results in unpredictable behaviour,
+          so on these CPUs, this option is forced on.
+
+          Multiple mappings with differing attributes is also unpredictable
+          on ARMv6 CPUs, but since they do not have aggressive speculative
+          prefetch, no harm appears to occur.
+
+          However, drivers may be missing the necessary barriers for ARMv6,
+          and therefore turning this on may result in unpredictable driver
+          behaviour.  Therefore, we offer this as an option.
+
+          You are recommended say 'Y' here and debug any affected drivers.