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-rw-r--r--arch/arm/mach-s3c6410/Kconfig109
-rw-r--r--arch/arm/mach-s3c6410/Makefile26
-rw-r--r--arch/arm/mach-s3c6410/cpu.c105
-rw-r--r--arch/arm/mach-s3c6410/mach-anw6410.c245
-rw-r--r--arch/arm/mach-s3c6410/mach-hmt.c276
-rw-r--r--arch/arm/mach-s3c6410/mach-ncp.c107
-rw-r--r--arch/arm/mach-s3c6410/mach-smdk6410.c457
-rw-r--r--arch/arm/mach-s3c6410/setup-sdhci.c68
8 files changed, 0 insertions, 1393 deletions
diff --git a/arch/arm/mach-s3c6410/Kconfig b/arch/arm/mach-s3c6410/Kconfig
deleted file mode 100644
index 162f4561f80..00000000000
--- a/arch/arm/mach-s3c6410/Kconfig
+++ /dev/null
@@ -1,109 +0,0 @@
1# Copyright 2008 Openmoko, Inc.
2# Copyright 2008 Simtec Electronics
3#
4# Licensed under GPLv2
5
6# Configuration options for the S3C6410 CPU
7
8config CPU_S3C6410
9 bool
10 select CPU_S3C6400_INIT
11 select CPU_S3C6400_CLOCK
12 help
13 Enable S3C6410 CPU support
14
15config S3C6410_SETUP_SDHCI
16 bool
17 select S3C64XX_SETUP_SDHCI_GPIO
18 help
19 Internal helper functions for S3C6410 based SDHCI systems
20
21config MACH_ANW6410
22 bool "A&W6410"
23 select CPU_S3C6410
24 select S3C_DEV_FB
25 select S3C64XX_SETUP_FB_24BPP
26 help
27 Machine support for the A&W6410
28
29config MACH_SMDK6410
30 bool "SMDK6410"
31 select CPU_S3C6410
32 select S3C_DEV_HSMMC
33 select S3C_DEV_HSMMC1
34 select S3C_DEV_I2C1
35 select S3C_DEV_FB
36 select S3C_DEV_USB_HOST
37 select S3C_DEV_USB_HSOTG
38 select S3C6410_SETUP_SDHCI
39 select S3C64XX_SETUP_I2C1
40 select S3C64XX_SETUP_FB_24BPP
41 help
42 Machine support for the Samsung SMDK6410
43
44# At least some of the SMDK6410s were shipped with the card detect
45# for the MMC/SD slots connected to the same input. This means that
46# either the boards need to be altered to have channel0 to an alternate
47# configuration or that only one slot can be used.
48
49choice
50 prompt "SMDK6410 MMC/SD slot setup"
51 depends on MACH_SMDK6410
52
53config SMDK6410_SD_CH0
54 bool "Use channel 0 only"
55 depends on MACH_SMDK6410
56 help
57 Select CON7 (channel 0) as the MMC/SD slot, as
58 at least some SMDK6410 boards come with the
59 resistors fitted so that the card detects for
60 channels 0 and 1 are the same.
61
62config SMDK6410_SD_CH1
63 bool "Use channel 1 only"
64 depends on MACH_SMDK6410
65 help
66 Select CON6 (channel 1) as the MMC/SD slot, as
67 at least some SMDK6410 boards come with the
68 resistors fitted so that the card detects for
69 channels 0 and 1 are the same.
70
71endchoice
72
73config SMDK6410_WM1190_EV1
74 bool "Support Wolfson Microelectronics 1190-EV1 PMIC card"
75 depends on MACH_SMDK6410
76 select REGULATOR
77 select REGULATOR_WM8350
78 select S3C24XX_GPIO_EXTRA64
79 select MFD_WM8350_I2C
80 select MFD_WM8350_CONFIG_MODE_0
81 select MFD_WM8350_CONFIG_MODE_3
82 select MFD_WM8352_CONFIG_MODE_0
83 help
84 The Wolfson Microelectronics 1190-EV1 is a WM835x based PMIC
85 and audio daughtercard for the Samsung SMDK6410 reference
86 platform. Enabling this option will build support for this
87 module into the kernel. The presence of the module will be
88 detected at runtime so the the resulting kernel can be used
89 with or without the 1190-EV1 fitted.
90
91config MACH_NCP
92 bool "NCP"
93 select CPU_S3C6410
94 select S3C_DEV_I2C1
95 select S3C_DEV_HSMMC1
96 select S3C64XX_SETUP_I2C1
97 help
98 Machine support for the Samsung NCP
99
100config MACH_HMT
101 bool "Airgoo HMT"
102 select CPU_S3C6410
103 select S3C_DEV_FB
104 select S3C_DEV_NAND
105 select S3C_DEV_USB_HOST
106 select S3C64XX_SETUP_FB_24BPP
107 select HAVE_PWM
108 help
109 Machine support for the Airgoo HMT
diff --git a/arch/arm/mach-s3c6410/Makefile b/arch/arm/mach-s3c6410/Makefile
deleted file mode 100644
index 3e48c3dbf97..00000000000
--- a/arch/arm/mach-s3c6410/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
1# arch/arm/plat-s3c6410/Makefile
2#
3# Copyright 2008 Openmoko, Inc.
4# Copyright 2008 Simtec Electronics
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n :=
11obj- :=
12
13# Core support for S3C6410 system
14
15obj-$(CONFIG_CPU_S3C6410) += cpu.o
16
17# Helper and device support
18
19obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o
20
21# machine support
22
23obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o
24obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
25obj-$(CONFIG_MACH_NCP) += mach-ncp.o
26obj-$(CONFIG_MACH_HMT) += mach-hmt.o
diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c6410/cpu.c
deleted file mode 100644
index 522c0869195..00000000000
--- a/arch/arm/mach-s3c6410/cpu.c
+++ /dev/null
@@ -1,105 +0,0 @@
1/* linux/arch/arm/mach-s3c6410/cpu.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/io.h>
21#include <linux/sysdev.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31
32#include <plat/cpu-freq.h>
33#include <plat/regs-serial.h>
34#include <plat/regs-clock.h>
35
36#include <plat/cpu.h>
37#include <plat/devs.h>
38#include <plat/clock.h>
39#include <plat/sdhci.h>
40#include <plat/iic-core.h>
41#include <plat/s3c6400.h>
42#include <plat/s3c6410.h>
43
44/* Initial IO mappings */
45
46static struct map_desc s3c6410_iodesc[] __initdata = {
47};
48
49/* s3c6410_map_io
50 *
51 * register the standard cpu IO areas
52*/
53
54void __init s3c6410_map_io(void)
55{
56 iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc));
57
58 /* initialise device information early */
59 s3c6410_default_sdhci0();
60 s3c6410_default_sdhci1();
61 s3c6410_default_sdhci2();
62
63 /* the i2c devices are directly compatible with s3c2440 */
64 s3c_i2c0_setname("s3c2440-i2c");
65 s3c_i2c1_setname("s3c2440-i2c");
66
67 s3c_device_nand.name = "s3c6400-nand";
68}
69
70void __init s3c6410_init_clocks(int xtal)
71{
72 printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
73 s3c24xx_register_baseclocks(xtal);
74 s3c64xx_register_clocks();
75 s3c6400_register_clocks(S3C6410_CLKDIV0_ARM_MASK);
76 s3c6400_setup_clocks();
77}
78
79void __init s3c6410_init_irq(void)
80{
81 /* VIC0 is missing IRQ7, VIC1 is fully populated. */
82 s3c64xx_init_irq(~0 & ~(1 << 7), ~0);
83}
84
85struct sysdev_class s3c6410_sysclass = {
86 .name = "s3c6410-core",
87};
88
89static struct sys_device s3c6410_sysdev = {
90 .cls = &s3c6410_sysclass,
91};
92
93static int __init s3c6410_core_init(void)
94{
95 return sysdev_class_register(&s3c6410_sysclass);
96}
97
98core_initcall(s3c6410_core_init);
99
100int __init s3c6410_init(void)
101{
102 printk("S3C6410: Initialising architecture\n");
103
104 return sysdev_register(&s3c6410_sysdev);
105}
diff --git a/arch/arm/mach-s3c6410/mach-anw6410.c b/arch/arm/mach-s3c6410/mach-anw6410.c
deleted file mode 100644
index 661cca63de2..00000000000
--- a/arch/arm/mach-s3c6410/mach-anw6410.c
+++ /dev/null
@@ -1,245 +0,0 @@
1/* linux/arch/arm/mach-s3c6410/mach-anw6410.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 * Copyright 2009 Kwangwoo Lee
8 * Kwangwoo Lee <kwangwoo.lee@gmail.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14*/
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/interrupt.h>
19#include <linux/list.h>
20#include <linux/timer.h>
21#include <linux/init.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24#include <linux/io.h>
25#include <linux/i2c.h>
26#include <linux/fb.h>
27#include <linux/gpio.h>
28#include <linux/delay.h>
29#include <linux/dm9000.h>
30
31#include <video/platform_lcd.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/irq.h>
36
37#include <mach/hardware.h>
38#include <mach/regs-fb.h>
39#include <mach/map.h>
40
41#include <asm/irq.h>
42#include <asm/mach-types.h>
43
44#include <plat/regs-serial.h>
45#include <plat/iic.h>
46#include <plat/fb.h>
47
48#include <plat/s3c6410.h>
49#include <plat/clock.h>
50#include <plat/devs.h>
51#include <plat/cpu.h>
52#include <plat/regs-gpio.h>
53#include <plat/regs-modem.h>
54
55/* DM9000 */
56#define ANW6410_PA_DM9000 (0x18000000)
57
58/* A hardware buffer to control external devices is mapped at 0x30000000.
59 * It can not be read. So current status must be kept in anw6410_extdev_status.
60 */
61#define ANW6410_VA_EXTDEV S3C_ADDR(0x02000000)
62#define ANW6410_PA_EXTDEV (0x30000000)
63
64#define ANW6410_EN_DM9000 (1<<11)
65#define ANW6410_EN_LCD (1<<14)
66
67static __u32 anw6410_extdev_status;
68
69static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
70 [0] = {
71 .hwport = 0,
72 .flags = 0,
73 .ucon = 0x3c5,
74 .ulcon = 0x03,
75 .ufcon = 0x51,
76 },
77 [1] = {
78 .hwport = 1,
79 .flags = 0,
80 .ucon = 0x3c5,
81 .ulcon = 0x03,
82 .ufcon = 0x51,
83 },
84};
85
86/* framebuffer and LCD setup. */
87static void __init anw6410_lcd_mode_set(void)
88{
89 u32 tmp;
90
91 /* set the LCD type */
92 tmp = __raw_readl(S3C64XX_SPCON);
93 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
94 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
95 __raw_writel(tmp, S3C64XX_SPCON);
96
97 /* remove the LCD bypass */
98 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
99 tmp &= ~MIFPCON_LCD_BYPASS;
100 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
101}
102
103/* GPF1 = LCD panel power
104 * GPF4 = LCD backlight control
105 */
106static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
107 unsigned int power)
108{
109 if (power) {
110 anw6410_extdev_status |= (ANW6410_EN_LCD << 16);
111 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
112
113 gpio_direction_output(S3C64XX_GPF(1), 1);
114 gpio_direction_output(S3C64XX_GPF(4), 1);
115 } else {
116 anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
117 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
118
119 gpio_direction_output(S3C64XX_GPF(1), 0);
120 gpio_direction_output(S3C64XX_GPF(4), 0);
121 }
122}
123
124static struct plat_lcd_data anw6410_lcd_power_data = {
125 .set_power = anw6410_lcd_power_set,
126};
127
128static struct platform_device anw6410_lcd_powerdev = {
129 .name = "platform-lcd",
130 .dev.parent = &s3c_device_fb.dev,
131 .dev.platform_data = &anw6410_lcd_power_data,
132};
133
134static struct s3c_fb_pd_win anw6410_fb_win0 = {
135 /* this is to ensure we use win0 */
136 .win_mode = {
137 .pixclock = 41094,
138 .left_margin = 8,
139 .right_margin = 13,
140 .upper_margin = 7,
141 .lower_margin = 5,
142 .hsync_len = 3,
143 .vsync_len = 1,
144 .xres = 800,
145 .yres = 480,
146 },
147 .max_bpp = 32,
148 .default_bpp = 16,
149};
150
151/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
152static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
153 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
154 .win[0] = &anw6410_fb_win0,
155 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
156 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
157};
158
159/* DM9000AEP 10/100 ethernet controller */
160static void __init anw6410_dm9000_enable(void)
161{
162 anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16);
163 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
164}
165
166static struct resource anw6410_dm9000_resource[] = {
167 [0] = {
168 .start = ANW6410_PA_DM9000,
169 .end = ANW6410_PA_DM9000 + 3,
170 .flags = IORESOURCE_MEM,
171 },
172 [1] = {
173 .start = ANW6410_PA_DM9000 + 4,
174 .end = ANW6410_PA_DM9000 + 4 + 500,
175 .flags = IORESOURCE_MEM,
176 },
177 [2] = {
178 .start = IRQ_EINT(15),
179 .end = IRQ_EINT(15),
180 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
181 },
182};
183
184static struct dm9000_plat_data anw6410_dm9000_pdata = {
185 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
186 /* dev_addr can be set to provide hwaddr. */
187};
188
189static struct platform_device anw6410_device_eth = {
190 .name = "dm9000",
191 .id = -1,
192 .num_resources = ARRAY_SIZE(anw6410_dm9000_resource),
193 .resource = anw6410_dm9000_resource,
194 .dev = {
195 .platform_data = &anw6410_dm9000_pdata,
196 },
197};
198
199static struct map_desc anw6410_iodesc[] __initdata = {
200 {
201 .virtual = (unsigned long)ANW6410_VA_EXTDEV,
202 .pfn = __phys_to_pfn(ANW6410_PA_EXTDEV),
203 .length = SZ_64K,
204 .type = MT_DEVICE,
205 },
206};
207
208static struct platform_device *anw6410_devices[] __initdata = {
209 &s3c_device_fb,
210 &anw6410_lcd_powerdev,
211 &anw6410_device_eth,
212};
213
214static void __init anw6410_map_io(void)
215{
216 s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
217 s3c24xx_init_clocks(12000000);
218 s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
219
220 anw6410_lcd_mode_set();
221}
222
223static void __init anw6410_machine_init(void)
224{
225 s3c_fb_set_platdata(&anw6410_lcd_pdata);
226
227 gpio_request(S3C64XX_GPF(1), "panel power");
228 gpio_request(S3C64XX_GPF(4), "LCD backlight");
229
230 anw6410_dm9000_enable();
231
232 platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
233}
234
235MACHINE_START(ANW6410, "A&W6410")
236 /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
237 .phys_io = S3C_PA_UART & 0xfff00000,
238 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
239 .boot_params = S3C64XX_PA_SDRAM + 0x100,
240
241 .init_irq = s3c6410_init_irq,
242 .map_io = anw6410_map_io,
243 .init_machine = anw6410_machine_init,
244 .timer = &s3c24xx_timer,
245MACHINE_END
diff --git a/arch/arm/mach-s3c6410/mach-hmt.c b/arch/arm/mach-s3c6410/mach-hmt.c
deleted file mode 100644
index 7619456f2ae..00000000000
--- a/arch/arm/mach-s3c6410/mach-hmt.c
+++ /dev/null
@@ -1,276 +0,0 @@
1/* mach-hmt.c - Platform code for Airgoo HMT
2 *
3 * Copyright 2009 Peter Korsgaard <jacmet@sunsite.dk>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9*/
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/serial_core.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/i2c.h>
17#include <linux/fb.h>
18#include <linux/gpio.h>
19#include <linux/delay.h>
20#include <linux/leds.h>
21#include <linux/pwm_backlight.h>
22#include <linux/mtd/mtd.h>
23#include <linux/mtd/partitions.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28
29#include <mach/hardware.h>
30#include <mach/regs-fb.h>
31#include <mach/map.h>
32
33#include <asm/irq.h>
34#include <asm/mach-types.h>
35
36#include <plat/regs-serial.h>
37#include <plat/iic.h>
38#include <plat/fb.h>
39#include <plat/nand.h>
40
41#include <plat/s3c6410.h>
42#include <plat/clock.h>
43#include <plat/devs.h>
44#include <plat/cpu.h>
45
46#define UCON S3C2410_UCON_DEFAULT
47#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
48#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
49
50static struct s3c2410_uartcfg hmt_uartcfgs[] __initdata = {
51 [0] = {
52 .hwport = 0,
53 .flags = 0,
54 .ucon = UCON,
55 .ulcon = ULCON,
56 .ufcon = UFCON,
57 },
58 [1] = {
59 .hwport = 1,
60 .flags = 0,
61 .ucon = UCON,
62 .ulcon = ULCON,
63 .ufcon = UFCON,
64 },
65 [2] = {
66 .hwport = 2,
67 .flags = 0,
68 .ucon = UCON,
69 .ulcon = ULCON,
70 .ufcon = UFCON,
71 },
72};
73
74static int hmt_bl_init(struct device *dev)
75{
76 int ret;
77
78 ret = gpio_request(S3C64XX_GPB(4), "lcd backlight enable");
79 if (!ret)
80 ret = gpio_direction_output(S3C64XX_GPB(4), 0);
81
82 return ret;
83}
84
85static int hmt_bl_notify(struct device *dev, int brightness)
86{
87 /*
88 * translate from CIELUV/CIELAB L*->brightness, E.G. from
89 * perceived luminance to light output. Assumes range 0..25600
90 */
91 if (brightness < 0x800) {
92 /* Y = Yn * L / 903.3 */
93 brightness = (100*256 * brightness + 231245/2) / 231245;
94 } else {
95 /* Y = Yn * ((L + 16) / 116 )^3 */
96 int t = (brightness*4 + 16*1024 + 58)/116;
97 brightness = 25 * ((t * t * t + 0x100000/2) / 0x100000);
98 }
99
100 gpio_set_value(S3C64XX_GPB(4), brightness);
101
102 return brightness;
103}
104
105static void hmt_bl_exit(struct device *dev)
106{
107 gpio_free(S3C64XX_GPB(4));
108}
109
110static struct platform_pwm_backlight_data hmt_backlight_data = {
111 .pwm_id = 1,
112 .max_brightness = 100 * 256,
113 .dft_brightness = 40 * 256,
114 .pwm_period_ns = 1000000000 / (100 * 256 * 20),
115 .init = hmt_bl_init,
116 .notify = hmt_bl_notify,
117 .exit = hmt_bl_exit,
118
119};
120
121static struct platform_device hmt_backlight_device = {
122 .name = "pwm-backlight",
123 .dev = {
124 .parent = &s3c_device_timer[1].dev,
125 .platform_data = &hmt_backlight_data,
126 },
127};
128
129static struct s3c_fb_pd_win hmt_fb_win0 = {
130 .win_mode = {
131 .pixclock = 41094,
132 .left_margin = 8,
133 .right_margin = 13,
134 .upper_margin = 7,
135 .lower_margin = 5,
136 .hsync_len = 3,
137 .vsync_len = 1,
138 .xres = 800,
139 .yres = 480,
140 },
141 .max_bpp = 32,
142 .default_bpp = 16,
143};
144
145/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
146static struct s3c_fb_platdata hmt_lcd_pdata __initdata = {
147 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
148 .win[0] = &hmt_fb_win0,
149 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
150 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
151};
152
153static struct mtd_partition hmt_nand_part[] = {
154 [0] = {
155 .name = "uboot",
156 .size = SZ_512K,
157 .offset = 0,
158 },
159 [1] = {
160 .name = "uboot-env1",
161 .size = SZ_256K,
162 .offset = SZ_512K,
163 },
164 [2] = {
165 .name = "uboot-env2",
166 .size = SZ_256K,
167 .offset = SZ_512K + SZ_256K,
168 },
169 [3] = {
170 .name = "kernel",
171 .size = SZ_2M,
172 .offset = SZ_1M,
173 },
174 [4] = {
175 .name = "rootfs",
176 .size = MTDPART_SIZ_FULL,
177 .offset = SZ_1M + SZ_2M,
178 },
179};
180
181static struct s3c2410_nand_set hmt_nand_sets[] = {
182 [0] = {
183 .name = "nand",
184 .nr_chips = 1,
185 .nr_partitions = ARRAY_SIZE(hmt_nand_part),
186 .partitions = hmt_nand_part,
187 },
188};
189
190static struct s3c2410_platform_nand hmt_nand_info = {
191 .tacls = 25,
192 .twrph0 = 55,
193 .twrph1 = 40,
194 .nr_sets = ARRAY_SIZE(hmt_nand_sets),
195 .sets = hmt_nand_sets,
196};
197
198static struct gpio_led hmt_leds[] = {
199 { /* left function keys */
200 .name = "left:blue",
201 .gpio = S3C64XX_GPO(12),
202 .default_trigger = "default-on",
203 },
204 { /* right function keys - red */
205 .name = "right:red",
206 .gpio = S3C64XX_GPO(13),
207 },
208 { /* right function keys - green */
209 .name = "right:green",
210 .gpio = S3C64XX_GPO(14),
211 },
212 { /* right function keys - blue */
213 .name = "right:blue",
214 .gpio = S3C64XX_GPO(15),
215 .default_trigger = "default-on",
216 },
217};
218
219static struct gpio_led_platform_data hmt_led_data = {
220 .num_leds = ARRAY_SIZE(hmt_leds),
221 .leds = hmt_leds,
222};
223
224static struct platform_device hmt_leds_device = {
225 .name = "leds-gpio",
226 .id = -1,
227 .dev.platform_data = &hmt_led_data,
228};
229
230static struct map_desc hmt_iodesc[] = {};
231
232static struct platform_device *hmt_devices[] __initdata = {
233 &s3c_device_i2c0,
234 &s3c_device_nand,
235 &s3c_device_fb,
236 &s3c_device_usb,
237 &s3c_device_timer[1],
238 &hmt_backlight_device,
239 &hmt_leds_device,
240};
241
242static void __init hmt_map_io(void)
243{
244 s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
245 s3c24xx_init_clocks(12000000);
246 s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
247}
248
249static void __init hmt_machine_init(void)
250{
251 s3c_i2c0_set_platdata(NULL);
252 s3c_fb_set_platdata(&hmt_lcd_pdata);
253 s3c_nand_set_platdata(&hmt_nand_info);
254
255 gpio_request(S3C64XX_GPC(7), "usb power");
256 gpio_direction_output(S3C64XX_GPC(7), 0);
257 gpio_request(S3C64XX_GPM(0), "usb power");
258 gpio_direction_output(S3C64XX_GPM(0), 1);
259 gpio_request(S3C64XX_GPK(7), "usb power");
260 gpio_direction_output(S3C64XX_GPK(7), 1);
261 gpio_request(S3C64XX_GPF(13), "usb power");
262 gpio_direction_output(S3C64XX_GPF(13), 1);
263
264 platform_add_devices(hmt_devices, ARRAY_SIZE(hmt_devices));
265}
266
267MACHINE_START(HMT, "Airgoo-HMT")
268 /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */
269 .phys_io = S3C_PA_UART & 0xfff00000,
270 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
271 .boot_params = S3C64XX_PA_SDRAM + 0x100,
272 .init_irq = s3c6410_init_irq,
273 .map_io = hmt_map_io,
274 .init_machine = hmt_machine_init,
275 .timer = &s3c24xx_timer,
276MACHINE_END
diff --git a/arch/arm/mach-s3c6410/mach-ncp.c b/arch/arm/mach-s3c6410/mach-ncp.c
deleted file mode 100644
index 55e9bbfaf68..00000000000
--- a/arch/arm/mach-s3c6410/mach-ncp.c
+++ /dev/null
@@ -1,107 +0,0 @@
1/*
2 * linux/arch/arm/mach-s3c6410/mach-ncp.c
3 *
4 * Copyright (C) 2008-2009 Samsung Electronics
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/platform_device.h>
20#include <linux/io.h>
21#include <linux/i2c.h>
22#include <linux/fb.h>
23#include <linux/gpio.h>
24#include <linux/delay.h>
25
26#include <video/platform_lcd.h>
27
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/irq.h>
31
32#include <mach/hardware.h>
33#include <mach/regs-fb.h>
34#include <mach/map.h>
35
36#include <asm/irq.h>
37#include <asm/mach-types.h>
38
39#include <plat/regs-serial.h>
40#include <plat/iic.h>
41#include <plat/fb.h>
42
43#include <plat/s3c6410.h>
44#include <plat/clock.h>
45#include <plat/devs.h>
46#include <plat/cpu.h>
47
48#define UCON S3C2410_UCON_DEFAULT
49#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
50#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
51
52static struct s3c2410_uartcfg ncp_uartcfgs[] __initdata = {
53 /* REVISIT: NCP uses only serial 1, 2 */
54 [0] = {
55 .hwport = 0,
56 .flags = 0,
57 .ucon = UCON,
58 .ulcon = ULCON,
59 .ufcon = UFCON,
60 },
61 [1] = {
62 .hwport = 1,
63 .flags = 0,
64 .ucon = UCON,
65 .ulcon = ULCON,
66 .ufcon = UFCON,
67 },
68 [2] = {
69 .hwport = 2,
70 .flags = 0,
71 .ucon = UCON,
72 .ulcon = ULCON,
73 .ufcon = UFCON,
74 },
75};
76
77static struct platform_device *ncp_devices[] __initdata = {
78 &s3c_device_hsmmc1,
79 &s3c_device_i2c0,
80};
81
82static struct map_desc ncp_iodesc[] __initdata = {};
83
84static void __init ncp_map_io(void)
85{
86 s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
87 s3c24xx_init_clocks(12000000);
88 s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
89}
90
91static void __init ncp_machine_init(void)
92{
93 s3c_i2c0_set_platdata(NULL);
94
95 platform_add_devices(ncp_devices, ARRAY_SIZE(ncp_devices));
96}
97
98MACHINE_START(NCP, "NCP")
99 /* Maintainer: Samsung Electronics */
100 .phys_io = S3C_PA_UART & 0xfff00000,
101 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
102 .boot_params = S3C64XX_PA_SDRAM + 0x100,
103 .init_irq = s3c6410_init_irq,
104 .map_io = ncp_map_io,
105 .init_machine = ncp_machine_init,
106 .timer = &s3c24xx_timer,
107MACHINE_END
diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
deleted file mode 100644
index 8969fe73b83..00000000000
--- a/arch/arm/mach-s3c6410/mach-smdk6410.c
+++ /dev/null
@@ -1,457 +0,0 @@
1/* linux/arch/arm/mach-s3c6410/mach-smdk6410.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23#include <linux/i2c.h>
24#include <linux/fb.h>
25#include <linux/gpio.h>
26#include <linux/delay.h>
27#include <linux/smsc911x.h>
28#include <linux/regulator/fixed.h>
29
30#ifdef CONFIG_SMDK6410_WM1190_EV1
31#include <linux/mfd/wm8350/core.h>
32#include <linux/mfd/wm8350/pmic.h>
33#endif
34
35#include <video/platform_lcd.h>
36
37#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39#include <asm/mach/irq.h>
40
41#include <mach/hardware.h>
42#include <mach/regs-fb.h>
43#include <mach/map.h>
44
45#include <asm/irq.h>
46#include <asm/mach-types.h>
47
48#include <plat/regs-serial.h>
49#include <plat/regs-modem.h>
50#include <plat/regs-gpio.h>
51#include <plat/regs-sys.h>
52#include <plat/iic.h>
53#include <plat/fb.h>
54#include <plat/gpio-cfg.h>
55
56#include <plat/s3c6410.h>
57#include <plat/clock.h>
58#include <plat/devs.h>
59#include <plat/cpu.h>
60
61#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
62#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
63#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
64
65static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
66 [0] = {
67 .hwport = 0,
68 .flags = 0,
69 .ucon = UCON,
70 .ulcon = ULCON,
71 .ufcon = UFCON,
72 },
73 [1] = {
74 .hwport = 1,
75 .flags = 0,
76 .ucon = UCON,
77 .ulcon = ULCON,
78 .ufcon = UFCON,
79 },
80 [2] = {
81 .hwport = 2,
82 .flags = 0,
83 .ucon = UCON,
84 .ulcon = ULCON,
85 .ufcon = UFCON,
86 },
87 [3] = {
88 .hwport = 3,
89 .flags = 0,
90 .ucon = UCON,
91 .ulcon = ULCON,
92 .ufcon = UFCON,
93 },
94};
95
96/* framebuffer and LCD setup. */
97
98/* GPF15 = LCD backlight control
99 * GPF13 => Panel power
100 * GPN5 = LCD nRESET signal
101 * PWM_TOUT1 => backlight brightness
102 */
103
104static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
105 unsigned int power)
106{
107 if (power) {
108 gpio_direction_output(S3C64XX_GPF(13), 1);
109 gpio_direction_output(S3C64XX_GPF(15), 1);
110
111 /* fire nRESET on power up */
112 gpio_direction_output(S3C64XX_GPN(5), 0);
113 msleep(10);
114 gpio_direction_output(S3C64XX_GPN(5), 1);
115 msleep(1);
116 } else {
117 gpio_direction_output(S3C64XX_GPF(15), 0);
118 gpio_direction_output(S3C64XX_GPF(13), 0);
119 }
120}
121
122static struct plat_lcd_data smdk6410_lcd_power_data = {
123 .set_power = smdk6410_lcd_power_set,
124};
125
126static struct platform_device smdk6410_lcd_powerdev = {
127 .name = "platform-lcd",
128 .dev.parent = &s3c_device_fb.dev,
129 .dev.platform_data = &smdk6410_lcd_power_data,
130};
131
132static struct s3c_fb_pd_win smdk6410_fb_win0 = {
133 /* this is to ensure we use win0 */
134 .win_mode = {
135 .pixclock = 41094,
136 .left_margin = 8,
137 .right_margin = 13,
138 .upper_margin = 7,
139 .lower_margin = 5,
140 .hsync_len = 3,
141 .vsync_len = 1,
142 .xres = 800,
143 .yres = 480,
144 },
145 .max_bpp = 32,
146 .default_bpp = 16,
147};
148
149/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
150static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
151 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
152 .win[0] = &smdk6410_fb_win0,
153 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
154 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
155};
156
157static struct resource smdk6410_smsc911x_resources[] = {
158 [0] = {
159 .start = 0x18000000,
160 .end = 0x18000000 + SZ_64K - 1,
161 .flags = IORESOURCE_MEM,
162 },
163 [1] = {
164 .start = S3C_EINT(10),
165 .end = S3C_EINT(10),
166 .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
167 },
168};
169
170static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
171 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
172 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
173 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
174 .phy_interface = PHY_INTERFACE_MODE_MII,
175};
176
177
178static struct platform_device smdk6410_smsc911x = {
179 .name = "smsc911x",
180 .id = -1,
181 .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
182 .resource = &smdk6410_smsc911x_resources[0],
183 .dev = {
184 .platform_data = &smdk6410_smsc911x_pdata,
185 },
186};
187
188#ifdef CONFIG_REGULATOR
189static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
190 {
191 /* WM8580 */
192 .supply = "PVDD",
193 .dev_name = "0-001b",
194 },
195 {
196 /* WM8580 */
197 .supply = "AVDD",
198 .dev_name = "0-001b",
199 },
200};
201
202static struct regulator_init_data smdk6410_b_pwr_5v_data = {
203 .constraints = {
204 .always_on = 1,
205 },
206 .num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
207 .consumer_supplies = smdk6410_b_pwr_5v_consumers,
208};
209
210static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
211 .supply_name = "B_PWR_5V",
212 .microvolts = 5000000,
213 .init_data = &smdk6410_b_pwr_5v_data,
214 .gpio = -EINVAL,
215};
216
217static struct platform_device smdk6410_b_pwr_5v = {
218 .name = "reg-fixed-voltage",
219 .id = -1,
220 .dev = {
221 .platform_data = &smdk6410_b_pwr_5v_pdata,
222 },
223};
224#endif
225
226static struct map_desc smdk6410_iodesc[] = {};
227
228static struct platform_device *smdk6410_devices[] __initdata = {
229#ifdef CONFIG_SMDK6410_SD_CH0
230 &s3c_device_hsmmc0,
231#endif
232#ifdef CONFIG_SMDK6410_SD_CH1
233 &s3c_device_hsmmc1,
234#endif
235 &s3c_device_i2c0,
236 &s3c_device_i2c1,
237 &s3c_device_fb,
238 &s3c_device_usb,
239 &s3c_device_usb_hsotg,
240
241#ifdef CONFIG_REGULATOR
242 &smdk6410_b_pwr_5v,
243#endif
244 &smdk6410_lcd_powerdev,
245
246 &smdk6410_smsc911x,
247};
248
249#ifdef CONFIG_SMDK6410_WM1190_EV1
250/* S3C64xx internal logic & PLL */
251static struct regulator_init_data wm8350_dcdc1_data = {
252 .constraints = {
253 .name = "PVDD_INT/PVDD_PLL",
254 .min_uV = 1200000,
255 .max_uV = 1200000,
256 .always_on = 1,
257 .apply_uV = 1,
258 },
259};
260
261/* Memory */
262static struct regulator_init_data wm8350_dcdc3_data = {
263 .constraints = {
264 .name = "PVDD_MEM",
265 .min_uV = 1800000,
266 .max_uV = 1800000,
267 .always_on = 1,
268 .state_mem = {
269 .uV = 1800000,
270 .mode = REGULATOR_MODE_NORMAL,
271 .enabled = 1,
272 },
273 .initial_state = PM_SUSPEND_MEM,
274 },
275};
276
277/* USB, EXT, PCM, ADC/DAC, USB, MMC */
278static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
279 {
280 /* WM8580 */
281 .supply = "DVDD",
282 .dev_name = "0-001b",
283 },
284};
285
286static struct regulator_init_data wm8350_dcdc4_data = {
287 .constraints = {
288 .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
289 .min_uV = 3000000,
290 .max_uV = 3000000,
291 .always_on = 1,
292 },
293 .num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
294 .consumer_supplies = wm8350_dcdc4_consumers,
295};
296
297/* ARM core */
298static struct regulator_consumer_supply dcdc6_consumers[] = {
299 {
300 .supply = "vddarm",
301 }
302};
303
304static struct regulator_init_data wm8350_dcdc6_data = {
305 .constraints = {
306 .name = "PVDD_ARM",
307 .min_uV = 1000000,
308 .max_uV = 1300000,
309 .always_on = 1,
310 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
311 },
312 .num_consumer_supplies = ARRAY_SIZE(dcdc6_consumers),
313 .consumer_supplies = dcdc6_consumers,
314};
315
316/* Alive */
317static struct regulator_init_data wm8350_ldo1_data = {
318 .constraints = {
319 .name = "PVDD_ALIVE",
320 .min_uV = 1200000,
321 .max_uV = 1200000,
322 .always_on = 1,
323 .apply_uV = 1,
324 },
325};
326
327/* OTG */
328static struct regulator_init_data wm8350_ldo2_data = {
329 .constraints = {
330 .name = "PVDD_OTG",
331 .min_uV = 3300000,
332 .max_uV = 3300000,
333 .always_on = 1,
334 },
335};
336
337/* LCD */
338static struct regulator_init_data wm8350_ldo3_data = {
339 .constraints = {
340 .name = "PVDD_LCD",
341 .min_uV = 3000000,
342 .max_uV = 3000000,
343 .always_on = 1,
344 },
345};
346
347/* OTGi/1190-EV1 HPVDD & AVDD */
348static struct regulator_init_data wm8350_ldo4_data = {
349 .constraints = {
350 .name = "PVDD_OTGI/HPVDD/AVDD",
351 .min_uV = 1200000,
352 .max_uV = 1200000,
353 .apply_uV = 1,
354 .always_on = 1,
355 },
356};
357
358static struct {
359 int regulator;
360 struct regulator_init_data *initdata;
361} wm1190_regulators[] = {
362 { WM8350_DCDC_1, &wm8350_dcdc1_data },
363 { WM8350_DCDC_3, &wm8350_dcdc3_data },
364 { WM8350_DCDC_4, &wm8350_dcdc4_data },
365 { WM8350_DCDC_6, &wm8350_dcdc6_data },
366 { WM8350_LDO_1, &wm8350_ldo1_data },
367 { WM8350_LDO_2, &wm8350_ldo2_data },
368 { WM8350_LDO_3, &wm8350_ldo3_data },
369 { WM8350_LDO_4, &wm8350_ldo4_data },
370};
371
372static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
373{
374 int i;
375
376 /* Configure the IRQ line */
377 s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
378
379 /* Instantiate the regulators */
380 for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
381 wm8350_register_regulator(wm8350,
382 wm1190_regulators[i].regulator,
383 wm1190_regulators[i].initdata);
384
385 return 0;
386}
387
388static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
389 .init = smdk6410_wm8350_init,
390 .irq_high = 1,
391};
392#endif
393
394static struct i2c_board_info i2c_devs0[] __initdata = {
395 { I2C_BOARD_INFO("24c08", 0x50), },
396 { I2C_BOARD_INFO("wm8580", 0x1b), },
397
398#ifdef CONFIG_SMDK6410_WM1190_EV1
399 { I2C_BOARD_INFO("wm8350", 0x1a),
400 .platform_data = &smdk6410_wm8350_pdata,
401 .irq = S3C_EINT(12),
402 },
403#endif
404};
405
406static struct i2c_board_info i2c_devs1[] __initdata = {
407 { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
408};
409
410static void __init smdk6410_map_io(void)
411{
412 u32 tmp;
413
414 s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
415 s3c24xx_init_clocks(12000000);
416 s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
417
418 /* set the LCD type */
419
420 tmp = __raw_readl(S3C64XX_SPCON);
421 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
422 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
423 __raw_writel(tmp, S3C64XX_SPCON);
424
425 /* remove the lcd bypass */
426 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
427 tmp &= ~MIFPCON_LCD_BYPASS;
428 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
429}
430
431static void __init smdk6410_machine_init(void)
432{
433 s3c_i2c0_set_platdata(NULL);
434 s3c_i2c1_set_platdata(NULL);
435 s3c_fb_set_platdata(&smdk6410_lcd_pdata);
436
437 gpio_request(S3C64XX_GPN(5), "LCD power");
438 gpio_request(S3C64XX_GPF(13), "LCD power");
439 gpio_request(S3C64XX_GPF(15), "LCD power");
440
441 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
442 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
443
444 platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
445}
446
447MACHINE_START(SMDK6410, "SMDK6410")
448 /* Maintainer: Ben Dooks <ben@fluff.org> */
449 .phys_io = S3C_PA_UART & 0xfff00000,
450 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
451 .boot_params = S3C64XX_PA_SDRAM + 0x100,
452
453 .init_irq = s3c6410_init_irq,
454 .map_io = smdk6410_map_io,
455 .init_machine = smdk6410_machine_init,
456 .timer = &s3c24xx_timer,
457MACHINE_END
diff --git a/arch/arm/mach-s3c6410/setup-sdhci.c b/arch/arm/mach-s3c6410/setup-sdhci.c
deleted file mode 100644
index 816d2d9f9ef..00000000000
--- a/arch/arm/mach-s3c6410/setup-sdhci.c
+++ /dev/null
@@ -1,68 +0,0 @@
1/* linux/arch/arm/mach-s3c6410/setup-sdhci.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20
21#include <linux/mmc/card.h>
22#include <linux/mmc/host.h>
23
24#include <plat/regs-sdhci.h>
25#include <plat/sdhci.h>
26
27/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
28
29char *s3c6410_hsmmc_clksrcs[4] = {
30 [0] = "hsmmc",
31 [1] = "hsmmc",
32 [2] = "mmc_bus",
33 /* [3] = "48m", - note not successfully used yet */
34};
35
36
37void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
38 void __iomem *r,
39 struct mmc_ios *ios,
40 struct mmc_card *card)
41{
42 u32 ctrl2, ctrl3;
43
44 /* don't need to alter anything acording to card-type */
45
46 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
47
48 ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
49 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
50 ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
51 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
52 S3C_SDHCI_CTRL2_ENFBCLKRX |
53 S3C_SDHCI_CTRL2_DFCNT_NONE |
54 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
55
56 if (ios->clock < 25 * 1000000)
57 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
58 S3C_SDHCI_CTRL3_FCSEL2 |
59 S3C_SDHCI_CTRL3_FCSEL1 |
60 S3C_SDHCI_CTRL3_FCSEL0);
61 else
62 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
63
64 printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
65 writel(ctrl2, r + S3C_SDHCI_CONTROL2);
66 writel(ctrl3, r + S3C_SDHCI_CONTROL3);
67}
68
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-20 22:34:03 -0500