diff options
Diffstat (limited to 'arch/arm/mach-s3c2410/include/mach/regs-gpio.h')
| -rw-r--r-- | arch/arm/mach-s3c2410/include/mach/regs-gpio.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index ebc85c6dadb..fd672f330bf 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h | |||
| @@ -406,31 +406,31 @@ | |||
| 406 | #define S3C2443_GPE5_SD1_CLK (0x02 << 10) | 406 | #define S3C2443_GPE5_SD1_CLK (0x02 << 10) |
| 407 | #define S3C2400_GPE5_EINT5 (0x02 << 10) | 407 | #define S3C2400_GPE5_EINT5 (0x02 << 10) |
| 408 | #define S3C2400_GPE5_TCLK1 (0x03 << 10) | 408 | #define S3C2400_GPE5_TCLK1 (0x03 << 10) |
| 409 | #define S3C2443_GPE5_AC_BITCLK (0x03 << 10) | ||
| 409 | 410 | ||
| 410 | #define S3C2410_GPE6_SDCMD (0x02 << 12) | 411 | #define S3C2410_GPE6_SDCMD (0x02 << 12) |
| 411 | #define S3C2443_GPE6_SD1_CMD (0x02 << 12) | 412 | #define S3C2443_GPE6_SD1_CMD (0x02 << 12) |
| 412 | #define S3C2443_GPE6_AC_BITCLK (0x03 << 12) | 413 | #define S3C2443_GPE6_AC_SDI (0x03 << 12) |
| 413 | #define S3C2400_GPE6_EINT6 (0x02 << 12) | 414 | #define S3C2400_GPE6_EINT6 (0x02 << 12) |
| 414 | 415 | ||
| 415 | #define S3C2410_GPE7_SDDAT0 (0x02 << 14) | 416 | #define S3C2410_GPE7_SDDAT0 (0x02 << 14) |
| 416 | #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) | 417 | #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) |
| 417 | #define S3C2443_GPE7_AC_SDI (0x03 << 14) | 418 | #define S3C2443_GPE7_AC_SDO (0x03 << 14) |
| 418 | #define S3C2400_GPE7_EINT7 (0x02 << 14) | 419 | #define S3C2400_GPE7_EINT7 (0x02 << 14) |
| 419 | 420 | ||
| 420 | #define S3C2410_GPE8_SDDAT1 (0x02 << 16) | 421 | #define S3C2410_GPE8_SDDAT1 (0x02 << 16) |
| 421 | #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) | 422 | #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) |
| 422 | #define S3C2443_GPE8_AC_SDO (0x03 << 16) | 423 | #define S3C2443_GPE8_AC_SYNC (0x03 << 16) |
| 423 | #define S3C2400_GPE8_nXDACK0 (0x02 << 16) | 424 | #define S3C2400_GPE8_nXDACK0 (0x02 << 16) |
| 424 | 425 | ||
| 425 | #define S3C2410_GPE9_SDDAT2 (0x02 << 18) | 426 | #define S3C2410_GPE9_SDDAT2 (0x02 << 18) |
| 426 | #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) | 427 | #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) |
| 427 | #define S3C2443_GPE9_AC_SYNC (0x03 << 18) | 428 | #define S3C2443_GPE9_AC_nRESET (0x03 << 18) |
| 428 | #define S3C2400_GPE9_nXDACK1 (0x02 << 18) | 429 | #define S3C2400_GPE9_nXDACK1 (0x02 << 18) |
| 429 | #define S3C2400_GPE9_nXBACK (0x03 << 18) | 430 | #define S3C2400_GPE9_nXBACK (0x03 << 18) |
| 430 | 431 | ||
| 431 | #define S3C2410_GPE10_SDDAT3 (0x02 << 20) | 432 | #define S3C2410_GPE10_SDDAT3 (0x02 << 20) |
| 432 | #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) | 433 | #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) |
| 433 | #define S3C2443_GPE10_AC_nRESET (0x03 << 20) | ||
| 434 | #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) | 434 | #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) |
| 435 | 435 | ||
| 436 | #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) | 436 | #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) |