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@@ -41,27 +41,12 @@ Table of Contents
41 VI - System-on-a-chip devices and nodes 41 VI - System-on-a-chip devices and nodes
42 1) Defining child nodes of an SOC 42 1) Defining child nodes of an SOC
43 2) Representing devices without a current OF specification 43 2) Representing devices without a current OF specification
44 a) MDIO IO device 44 a) PHY nodes
45 b) Gianfar-compatible ethernet nodes 45 b) Interrupt controllers
46 c) PHY nodes 46 c) CFI or JEDEC memory-mapped NOR flash
47 d) Interrupt controllers 47 d) 4xx/Axon EMAC ethernet nodes
48 e) I2C 48 e) Xilinx IP cores
49 f) Freescale SOC USB controllers 49 f) USB EHCI controllers
50 g) Freescale SOC SEC Security Engines
51 h) Board Control and Status (BCSR)
52 i) Freescale QUICC Engine module (QE)
53 j) CFI or JEDEC memory-mapped NOR flash
54 k) Global Utilities Block
55 l) Freescale Communications Processor Module
56 m) Chipselect/Local Bus
57 n) 4xx/Axon EMAC ethernet nodes
58 o) Xilinx IP cores
59 p) Freescale Synchronous Serial Interface
60 q) USB EHCI controllers
61 r) Freescale Display Interface Unit
62 s) Freescale on board FPGA
63 t) Freescael MSI interrupt controller
64 u) Freescale General-purpose Timers Module
65 50
66 VII - Marvell Discovery mv64[345]6x System Controller chips 51 VII - Marvell Discovery mv64[345]6x System Controller chips
67 1) The /system-controller node 52 1) The /system-controller node
@@ -1250,80 +1235,7 @@ descriptions for the SOC devices for which new nodes have been
1250defined; this list will expand as more and more SOC-containing 1235defined; this list will expand as more and more SOC-containing
1251platforms are moved over to use the flattened-device-tree model. 1236platforms are moved over to use the flattened-device-tree model.
1252 1237
1253 a) MDIO IO device 1238 a) PHY nodes
1254
1255 The MDIO is a bus to which the PHY devices are connected. For each
1256 device that exists on this bus, a child node should be created. See
1257 the definition of the PHY node below for an example of how to define
1258 a PHY.
1259
1260 Required properties:
1261 - reg : Offset and length of the register set for the device
1262 - compatible : Should define the compatible device type for the
1263 mdio. Currently, this is most likely to be "fsl,gianfar-mdio"
1264
1265 Example:
1266
1267 mdio@24520 {
1268 reg = <24520 20>;
1269 compatible = "fsl,gianfar-mdio";
1270
1271 ethernet-phy@0 {
1272 ......
1273 };
1274 };
1275
1276
1277 b) Gianfar-compatible ethernet nodes
1278
1279 Required properties:
1280
1281 - device_type : Should be "network"
1282 - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
1283 - compatible : Should be "gianfar"
1284 - reg : Offset and length of the register set for the device
1285 - mac-address : List of bytes representing the ethernet address of
1286 this controller
1287 - interrupts : <a b> where a is the interrupt number and b is a
1288 field that represents an encoding of the sense and level
1289 information for the interrupt. This should be encoded based on
1290 the information in section 2) depending on the type of interrupt
1291 controller you have.
1292 - interrupt-parent : the phandle for the interrupt controller that
1293 services interrupts for this device.
1294 - phy-handle : The phandle for the PHY connected to this ethernet
1295 controller.
1296 - fixed-link : <a b c d e> where a is emulated phy id - choose any,
1297 but unique to the all specified fixed-links, b is duplex - 0 half,
1298 1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
1299 pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
1300
1301 Recommended properties:
1302
1303 - phy-connection-type : a string naming the controller/PHY interface type,
1304 i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
1305 "tbi", or "rtbi". This property is only really needed if the connection
1306 is of type "rgmii-id", as all other connection types are detected by
1307 hardware.
1308
1309
1310 Example:
1311
1312 ethernet@24000 {
1313 #size-cells = <0>;
1314 device_type = "network";
1315 model = "TSEC";
1316 compatible = "gianfar";
1317 reg = <24000 1000>;
1318 mac-address = [ 00 E0 0C 00 73 00 ];
1319 interrupts = <d 3 e 3 12 3>;
1320 interrupt-parent = <40000>;
1321 phy-handle = <2452000>
1322 };
1323
1324
1325
1326 c) PHY nodes
1327 1239
1328 Required properties: 1240 Required properties:
1329 1241
@@ -1351,7 +1263,7 @@ platforms are moved over to use the flattened-device-tree model.
1351 }; 1263 };
1352 1264
1353 1265
1354 d) Interrupt controllers 1266 b) Interrupt controllers
1355 1267
1356 Some SOC devices contain interrupt controllers that are different 1268 Some SOC devices contain interrupt controllers that are different
1357 from the standard Open PIC specification. The SOC device nodes for 1269 from the standard Open PIC specification. The SOC device nodes for
@@ -1371,508 +1283,7 @@ platforms are moved over to use the flattened-device-tree model.
1371 device_type = "open-pic"; 1283 device_type = "open-pic";
1372 }; 1284 };
1373 1285
1374 1286 c) CFI or JEDEC memory-mapped NOR flash
1375 e) I2C
1376
1377 Required properties :
1378
1379 - device_type : Should be "i2c"
1380 - reg : Offset and length of the register set for the device
1381
1382 Recommended properties :
1383
1384 - compatible : Should be "fsl-i2c" for parts compatible with
1385 Freescale I2C specifications.
1386 - interrupts : <a b> where a is the interrupt number and b is a
1387 field that represents an encoding of the sense and level
1388 information for the interrupt. This should be encoded based on
1389 the information in section 2) depending on the type of interrupt
1390 controller you have.
1391 - interrupt-parent : the phandle for the interrupt controller that
1392 services interrupts for this device.
1393 - dfsrr : boolean; if defined, indicates that this I2C device has
1394 a digital filter sampling rate register
1395 - fsl5200-clocking : boolean; if defined, indicated that this device
1396 uses the FSL 5200 clocking mechanism.
1397
1398 Example :
1399
1400 i2c@3000 {
1401 interrupt-parent = <40000>;
1402 interrupts = <1b 3>;
1403 reg = <3000 18>;
1404 device_type = "i2c";
1405 compatible = "fsl-i2c";
1406 dfsrr;
1407 };
1408
1409
1410 f) Freescale SOC USB controllers
1411
1412 The device node for a USB controller that is part of a Freescale
1413 SOC is as described in the document "Open Firmware Recommended
1414 Practice : Universal Serial Bus" with the following modifications
1415 and additions :
1416
1417 Required properties :
1418 - compatible : Should be "fsl-usb2-mph" for multi port host USB
1419 controllers, or "fsl-usb2-dr" for dual role USB controllers
1420 - phy_type : For multi port host USB controllers, should be one of
1421 "ulpi", or "serial". For dual role USB controllers, should be
1422 one of "ulpi", "utmi", "utmi_wide", or "serial".
1423 - reg : Offset and length of the register set for the device
1424 - port0 : boolean; if defined, indicates port0 is connected for
1425 fsl-usb2-mph compatible controllers. Either this property or
1426 "port1" (or both) must be defined for "fsl-usb2-mph" compatible
1427 controllers.
1428 - port1 : boolean; if defined, indicates port1 is connected for
1429 fsl-usb2-mph compatible controllers. Either this property or
1430 "port0" (or both) must be defined for "fsl-usb2-mph" compatible
1431 controllers.
1432 - dr_mode : indicates the working mode for "fsl-usb2-dr" compatible
1433 controllers. Can be "host", "peripheral", or "otg". Default to
1434 "host" if not defined for backward compatibility.
1435
1436 Recommended properties :
1437 - interrupts : <a b> where a is the interrupt number and b is a
1438 field that represents an encoding of the sense and level
1439 information for the interrupt. This should be encoded based on
1440 the information in section 2) depending on the type of interrupt
1441 controller you have.
1442 - interrupt-parent : the phandle for the interrupt controller that
1443 services interrupts for this device.
1444
1445 Example multi port host USB controller device node :
1446 usb@22000 {
1447 compatible = "fsl-usb2-mph";
1448 reg = <22000 1000>;
1449 #address-cells = <1>;
1450 #size-cells = <0>;
1451 interrupt-parent = <700>;
1452 interrupts = <27 1>;
1453 phy_type = "ulpi";
1454 port0;
1455 port1;
1456 };
1457
1458 Example dual role USB controller device node :
1459 usb@23000 {
1460 compatible = "fsl-usb2-dr";
1461 reg = <23000 1000>;
1462 #address-cells = <1>;
1463 #size-cells = <0>;
1464 interrupt-parent = <700>;
1465 interrupts = <26 1>;
1466 dr_mode = "otg";
1467 phy = "ulpi";
1468 };
1469
1470
1471 g) Freescale SOC SEC Security Engines
1472
1473 Required properties:
1474
1475 - device_type : Should be "crypto"
1476 - model : Model of the device. Should be "SEC1" or "SEC2"
1477 - compatible : Should be "talitos"
1478 - reg : Offset and length of the register set for the device
1479 - interrupts : <a b> where a is the interrupt number and b is a
1480 field that represents an encoding of the sense and level
1481 information for the interrupt. This should be encoded based on
1482 the information in section 2) depending on the type of interrupt
1483 controller you have.
1484 - interrupt-parent : the phandle for the interrupt controller that
1485 services interrupts for this device.
1486 - num-channels : An integer representing the number of channels
1487 available.
1488 - channel-fifo-len : An integer representing the number of
1489 descriptor pointers each channel fetch fifo can hold.
1490 - exec-units-mask : The bitmask representing what execution units
1491 (EUs) are available. It's a single 32-bit cell. EU information
1492 should be encoded following the SEC's Descriptor Header Dword
1493 EU_SEL0 field documentation, i.e. as follows:
1494
1495 bit 0 = reserved - should be 0
1496 bit 1 = set if SEC has the ARC4 EU (AFEU)
1497 bit 2 = set if SEC has the DES/3DES EU (DEU)
1498 bit 3 = set if SEC has the message digest EU (MDEU)
1499 bit 4 = set if SEC has the random number generator EU (RNG)
1500 bit 5 = set if SEC has the public key EU (PKEU)
1501 bit 6 = set if SEC has the AES EU (AESU)
1502 bit 7 = set if SEC has the Kasumi EU (KEU)
1503
1504 bits 8 through 31 are reserved for future SEC EUs.
1505
1506 - descriptor-types-mask : The bitmask representing what descriptors
1507 are available. It's a single 32-bit cell. Descriptor type
1508 information should be encoded following the SEC's Descriptor
1509 Header Dword DESC_TYPE field documentation, i.e. as follows:
1510
1511 bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
1512 bit 1 = set if SEC supports the ipsec_esp descriptor type
1513 bit 2 = set if SEC supports the common_nonsnoop desc. type
1514 bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
1515 bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
1516 bit 5 = set if SEC supports the srtp descriptor type
1517 bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
1518 bit 7 = set if SEC supports the pkeu_assemble descriptor type
1519 bit 8 = set if SEC supports the aesu_key_expand_output desc.type
1520 bit 9 = set if SEC supports the pkeu_ptmul descriptor type
1521 bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
1522 bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
1523
1524 ..and so on and so forth.
1525
1526 Example:
1527
1528 /* MPC8548E */
1529 crypto@30000 {
1530 device_type = "crypto";
1531 model = "SEC2";
1532 compatible = "talitos";
1533 reg = <30000 10000>;
1534 interrupts = <1d 3>;
1535 interrupt-parent = <40000>;
1536 num-channels = <4>;
1537 channel-fifo-len = <18>;
1538 exec-units-mask = <000000fe>;
1539 descriptor-types-mask = <012b0ebf>;
1540 };
1541
1542 h) Board Control and Status (BCSR)
1543
1544 Required properties:
1545
1546 - device_type : Should be "board-control"
1547 - reg : Offset and length of the register set for the device
1548
1549 Example:
1550
1551 bcsr@f8000000 {
1552 device_type = "board-control";
1553 reg = <f8000000 8000>;
1554 };
1555
1556 i) Freescale QUICC Engine module (QE)
1557 This represents qe module that is installed on PowerQUICC II Pro.
1558
1559 NOTE: This is an interim binding; it should be updated to fit
1560 in with the CPM binding later in this document.
1561
1562 Basically, it is a bus of devices, that could act more or less
1563 as a complete entity (UCC, USB etc ). All of them should be siblings on
1564 the "root" qe node, using the common properties from there.
1565 The description below applies to the qe of MPC8360 and
1566 more nodes and properties would be extended in the future.
1567
1568 i) Root QE device
1569
1570 Required properties:
1571 - compatible : should be "fsl,qe";
1572 - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
1573 - reg : offset and length of the device registers.
1574 - bus-frequency : the clock frequency for QUICC Engine.
1575
1576 Recommended properties
1577 - brg-frequency : the internal clock source frequency for baud-rate
1578 generators in Hz.
1579
1580 Example:
1581 qe@e0100000 {
1582 #address-cells = <1>;
1583 #size-cells = <1>;
1584 #interrupt-cells = <2>;
1585 compatible = "fsl,qe";
1586 ranges = <0 e0100000 00100000>;
1587 reg = <e0100000 480>;
1588 brg-frequency = <0>;
1589 bus-frequency = <179A7B00>;
1590 }
1591
1592
1593 ii) SPI (Serial Peripheral Interface)
1594
1595 Required properties:
1596 - cell-index : SPI controller index.
1597 - compatible : should be "fsl,spi".
1598 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
1599 - reg : Offset and length of the register set for the device
1600 - interrupts : <a b> where a is the interrupt number and b is a
1601 field that represents an encoding of the sense and level
1602 information for the interrupt. This should be encoded based on
1603 the information in section 2) depending on the type of interrupt
1604 controller you have.
1605 - interrupt-parent : the phandle for the interrupt controller that
1606 services interrupts for this device.
1607
1608 Example:
1609 spi@4c0 {
1610 cell-index = <0>;
1611 compatible = "fsl,spi";
1612 reg = <4c0 40>;
1613 interrupts = <82 0>;
1614 interrupt-parent = <700>;
1615 mode = "cpu";
1616 };
1617
1618
1619 iii) USB (Universal Serial Bus Controller)
1620
1621 Required properties:
1622 - compatible : could be "qe_udc" or "fhci-hcd".
1623 - mode : the could be "host" or "slave".
1624 - reg : Offset and length of the register set for the device
1625 - interrupts : <a b> where a is the interrupt number and b is a
1626 field that represents an encoding of the sense and level
1627 information for the interrupt. This should be encoded based on
1628 the information in section 2) depending on the type of interrupt
1629 controller you have.
1630 - interrupt-parent : the phandle for the interrupt controller that
1631 services interrupts for this device.
1632
1633 Example(slave):
1634 usb@6c0 {
1635 compatible = "qe_udc";
1636 reg = <6c0 40>;
1637 interrupts = <8b 0>;
1638 interrupt-parent = <700>;
1639 mode = "slave";
1640 };
1641
1642
1643 iv) UCC (Unified Communications Controllers)
1644
1645 Required properties:
1646 - device_type : should be "network", "hldc", "uart", "transparent"
1647 "bisync", "atm", or "serial".
1648 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
1649 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
1650 - reg : Offset and length of the register set for the device
1651 - interrupts : <a b> where a is the interrupt number and b is a
1652 field that represents an encoding of the sense and level
1653 information for the interrupt. This should be encoded based on
1654 the information in section 2) depending on the type of interrupt
1655 controller you have.
1656 - interrupt-parent : the phandle for the interrupt controller that
1657 services interrupts for this device.
1658 - pio-handle : The phandle for the Parallel I/O port configuration.
1659 - port-number : for UART drivers, the port number to use, between 0 and 3.
1660 This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
1661 The port number is added to the minor number of the device. Unlike the
1662 CPM UART driver, the port-number is required for the QE UART driver.
1663 - soft-uart : for UART drivers, if specified this means the QE UART device
1664 driver should use "Soft-UART" mode, which is needed on some SOCs that have
1665 broken UART hardware. Soft-UART is provided via a microcode upload.
1666 - rx-clock-name: the UCC receive clock source
1667 "none": clock source is disabled
1668 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
1669 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
1670 - tx-clock-name: the UCC transmit clock source
1671 "none": clock source is disabled
1672 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
1673 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
1674 The following two properties are deprecated. rx-clock has been replaced
1675 with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
1676 Drivers that currently use the deprecated properties should continue to
1677 do so, in order to support older device trees, but they should be updated
1678 to check for the new properties first.
1679 - rx-clock : represents the UCC receive clock source.
1680 0x00 : clock source is disabled;
1681 0x1~0x10 : clock source is BRG1~BRG16 respectively;
1682 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
1683 - tx-clock: represents the UCC transmit clock source;
1684 0x00 : clock source is disabled;
1685 0x1~0x10 : clock source is BRG1~BRG16 respectively;
1686 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
1687
1688 Required properties for network device_type:
1689 - mac-address : list of bytes representing the ethernet address.
1690 - phy-handle : The phandle for the PHY connected to this controller.
1691
1692 Recommended properties:
1693 - phy-connection-type : a string naming the controller/PHY interface type,
1694 i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
1695 Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
1696 "tbi", or "rtbi".
1697
1698 Example:
1699 ucc@2000 {
1700 device_type = "network";
1701 compatible = "ucc_geth";
1702 cell-index = <1>;
1703 reg = <2000 200>;
1704 interrupts = <a0 0>;
1705 interrupt-parent = <700>;
1706 mac-address = [ 00 04 9f 00 23 23 ];
1707 rx-clock = "none";
1708 tx-clock = "clk9";
1709 phy-handle = <212000>;
1710 phy-connection-type = "gmii";
1711 pio-handle = <140001>;
1712 };
1713
1714
1715 v) Parallel I/O Ports
1716
1717 This node configures Parallel I/O ports for CPUs with QE support.
1718 The node should reside in the "soc" node of the tree. For each
1719 device that using parallel I/O ports, a child node should be created.
1720 See the definition of the Pin configuration nodes below for more
1721 information.
1722
1723 Required properties:
1724 - device_type : should be "par_io".
1725 - reg : offset to the register set and its length.
1726 - num-ports : number of Parallel I/O ports
1727
1728 Example:
1729 par_io@1400 {
1730 reg = <1400 100>;
1731 #address-cells = <1>;
1732 #size-cells = <0>;
1733 device_type = "par_io";
1734 num-ports = <7>;
1735 ucc_pin@01 {
1736 ......
1737 };
1738
1739 Note that "par_io" nodes are obsolete, and should not be used for
1740 the new device trees. Instead, each Par I/O bank should be represented
1741 via its own gpio-controller node:
1742
1743 Required properties:
1744 - #gpio-cells : should be "2".
1745 - compatible : should be "fsl,<chip>-qe-pario-bank",
1746 "fsl,mpc8323-qe-pario-bank".
1747 - reg : offset to the register set and its length.
1748 - gpio-controller : node to identify gpio controllers.
1749
1750 Example:
1751 qe_pio_a: gpio-controller@1400 {
1752 #gpio-cells = <2>;
1753 compatible = "fsl,mpc8360-qe-pario-bank",
1754 "fsl,mpc8323-qe-pario-bank";
1755 reg = <0x1400 0x18>;
1756 gpio-controller;
1757 };
1758
1759 qe_pio_e: gpio-controller@1460 {
1760 #gpio-cells = <2>;
1761 compatible = "fsl,mpc8360-qe-pario-bank",
1762 "fsl,mpc8323-qe-pario-bank";
1763 reg = <0x1460 0x18>;
1764 gpio-controller;
1765 };
1766
1767 vi) Pin configuration nodes
1768
1769 Required properties:
1770 - linux,phandle : phandle of this node; likely referenced by a QE
1771 device.
1772 - pio-map : array of pin configurations. Each pin is defined by 6
1773 integers. The six numbers are respectively: port, pin, dir,
1774 open_drain, assignment, has_irq.
1775 - port : port number of the pin; 0-6 represent port A-G in UM.
1776 - pin : pin number in the port.
1777 - dir : direction of the pin, should encode as follows:
1778
1779 0 = The pin is disabled
1780 1 = The pin is an output
1781 2 = The pin is an input
1782 3 = The pin is I/O
1783
1784 - open_drain : indicates the pin is normal or wired-OR:
1785
1786 0 = The pin is actively driven as an output
1787 1 = The pin is an open-drain driver. As an output, the pin is
1788 driven active-low, otherwise it is three-stated.
1789
1790 - assignment : function number of the pin according to the Pin Assignment
1791 tables in User Manual. Each pin can have up to 4 possible functions in
1792 QE and two options for CPM.
1793 - has_irq : indicates if the pin is used as source of external
1794 interrupts.
1795
1796 Example:
1797 ucc_pin@01 {
1798 linux,phandle = <140001>;
1799 pio-map = <
1800 /* port pin dir open_drain assignment has_irq */
1801 0 3 1 0 1 0 /* TxD0 */
1802 0 4 1 0 1 0 /* TxD1 */
1803 0 5 1 0 1 0 /* TxD2 */
1804 0 6 1 0 1 0 /* TxD3 */
1805 1 6 1 0 3 0 /* TxD4 */
1806 1 7 1 0 1 0 /* TxD5 */
1807 1 9 1 0 2 0 /* TxD6 */
1808 1 a 1 0 2 0 /* TxD7 */
1809 0 9 2 0 1 0 /* RxD0 */
1810 0 a 2 0 1 0 /* RxD1 */
1811 0 b 2 0 1 0 /* RxD2 */
1812 0 c 2 0 1 0 /* RxD3 */
1813 0 d 2 0 1 0 /* RxD4 */
1814 1 1 2 0 2 0 /* RxD5 */
1815 1 0 2 0 2 0 /* RxD6 */
1816 1 4 2 0 2 0 /* RxD7 */
1817 0 7 1 0 1 0 /* TX_EN */
1818 0 8 1 0 1 0 /* TX_ER */
1819 0 f 2 0 1 0 /* RX_DV */
1820 0 10 2 0 1 0 /* RX_ER */
1821 0 0 2 0 1 0 /* RX_CLK */
1822 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
1823 2 8 2 0 1 0>; /* GTX125 - CLK9 */
1824 };
1825
1826 vii) Multi-User RAM (MURAM)
1827
1828 Required properties:
1829 - compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
1830 - mode : the could be "host" or "slave".
1831 - ranges : Should be defined as specified in 1) to describe the
1832 translation of MURAM addresses.
1833 - data-only : sub-node which defines the address area under MURAM
1834 bus that can be allocated as data/parameter
1835
1836 Example:
1837
1838 muram@10000 {
1839 compatible = "fsl,qe-muram", "fsl,cpm-muram";
1840 ranges = <0 00010000 0000c000>;
1841
1842 data-only@0{
1843 compatible = "fsl,qe-muram-data",
1844 "fsl,cpm-muram-data";
1845 reg = <0 c000>;
1846 };
1847 };
1848
1849 viii) Uploaded QE firmware
1850
1851 If a new firwmare has been uploaded to the QE (usually by the
1852 boot loader), then a 'firmware' child node should be added to the QE
1853 node. This node provides information on the uploaded firmware that
1854 device drivers may need.
1855
1856 Required properties:
1857 - id: The string name of the firmware. This is taken from the 'id'
1858 member of the qe_firmware structure of the uploaded firmware.
1859 Device drivers can search this string to determine if the
1860 firmware they want is already present.
1861 - extended-modes: The Extended Modes bitfield, taken from the
1862 firmware binary. It is a 64-bit number represented
1863 as an array of two 32-bit numbers.
1864 - virtual-traps: The virtual traps, taken from the firmware binary.
1865 It is an array of 8 32-bit numbers.
1866
1867 Example:
1868
1869 firmware {
1870 id = "Soft-UART";
1871 extended-modes = <0 0>;
1872 virtual-traps = <0 0 0 0 0 0 0 0>;
1873 }
1874
1875 j) CFI or JEDEC memory-mapped NOR flash
1876 1287
1877 Flash chips (Memory Technology Devices) are often used for solid state 1288 Flash chips (Memory Technology Devices) are often used for solid state
1878 file systems on embedded devices. 1289 file systems on embedded devices.
@@ -1936,268 +1347,7 @@ platforms are moved over to use the flattened-device-tree model.
1936 }; 1347 };
1937 }; 1348 };
1938 1349
1939 k) Global Utilities Block 1350 d) 4xx/Axon EMAC ethernet nodes
1940
1941 The global utilities block controls power management, I/O device
1942 enabling, power-on-reset configuration monitoring, general-purpose
1943 I/O signal configuration, alternate function selection for multiplexed
1944 signals, and clock control.
1945
1946 Required properties:
1947
1948 - compatible : Should define the compatible device type for
1949 global-utilities.
1950 - reg : Offset and length of the register set for the device.
1951
1952 Recommended properties:
1953
1954 - fsl,has-rstcr : Indicates that the global utilities register set
1955 contains a functioning "reset control register" (i.e. the board
1956 is wired to reset upon setting the HRESET_REQ bit in this register).
1957
1958 Example:
1959
1960 global-utilities@e0000 { /* global utilities block */
1961 compatible = "fsl,mpc8548-guts";
1962 reg = <e0000 1000>;
1963 fsl,has-rstcr;
1964 };
1965
1966 l) Freescale Communications Processor Module
1967
1968 NOTE: This is an interim binding, and will likely change slightly,
1969 as more devices are supported. The QE bindings especially are
1970 incomplete.
1971
1972 i) Root CPM node
1973
1974 Properties:
1975 - compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
1976 - reg : A 48-byte region beginning with CPCR.
1977
1978 Example:
1979 cpm@119c0 {
1980 #address-cells = <1>;
1981 #size-cells = <1>;
1982 #interrupt-cells = <2>;
1983 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
1984 reg = <119c0 30>;
1985 }
1986
1987 ii) Properties common to mulitple CPM/QE devices
1988
1989 - fsl,cpm-command : This value is ORed with the opcode and command flag
1990 to specify the device on which a CPM command operates.
1991
1992 - fsl,cpm-brg : Indicates which baud rate generator the device
1993 is associated with. If absent, an unused BRG
1994 should be dynamically allocated. If zero, the
1995 device uses an external clock rather than a BRG.
1996
1997 - reg : Unless otherwise specified, the first resource represents the
1998 scc/fcc/ucc registers, and the second represents the device's
1999 parameter RAM region (if it has one).
2000
2001 iii) Serial
2002
2003 Currently defined compatibles:
2004 - fsl,cpm1-smc-uart
2005 - fsl,cpm2-smc-uart
2006 - fsl,cpm1-scc-uart
2007 - fsl,cpm2-scc-uart
2008 - fsl,qe-uart
2009
2010 Example:
2011
2012 serial@11a00 {
2013 device_type = "serial";
2014 compatible = "fsl,mpc8272-scc-uart",
2015 "fsl,cpm2-scc-uart";
2016 reg = <11a00 20 8000 100>;
2017 interrupts = <28 8>;
2018 interrupt-parent = <&PIC>;
2019 fsl,cpm-brg = <1>;
2020 fsl,cpm-command = <00800000>;
2021 };
2022
2023 iii) Network
2024
2025 Currently defined compatibles:
2026 - fsl,cpm1-scc-enet
2027 - fsl,cpm2-scc-enet
2028 - fsl,cpm1-fec-enet
2029 - fsl,cpm2-fcc-enet (third resource is GFEMR)
2030 - fsl,qe-enet
2031
2032 Example:
2033
2034 ethernet@11300 {
2035 device_type = "network";
2036 compatible = "fsl,mpc8272-fcc-enet",
2037 "fsl,cpm2-fcc-enet";
2038 reg = <11300 20 8400 100 11390 1>;
2039 local-mac-address = [ 00 00 00 00 00 00 ];
2040 interrupts = <20 8>;
2041 interrupt-parent = <&PIC>;
2042 phy-handle = <&PHY0>;
2043 fsl,cpm-command = <12000300>;
2044 };
2045
2046 iv) MDIO
2047
2048 Currently defined compatibles:
2049 fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
2050 fsl,cpm2-mdio-bitbang (reg is port C registers)
2051
2052 Properties for fsl,cpm2-mdio-bitbang:
2053 fsl,mdio-pin : pin of port C controlling mdio data
2054 fsl,mdc-pin : pin of port C controlling mdio clock
2055
2056 Example:
2057
2058 mdio@10d40 {
2059 device_type = "mdio";
2060 compatible = "fsl,mpc8272ads-mdio-bitbang",
2061 "fsl,mpc8272-mdio-bitbang",
2062 "fsl,cpm2-mdio-bitbang";
2063 reg = <10d40 14>;
2064 #address-cells = <1>;
2065 #size-cells = <0>;
2066 fsl,mdio-pin = <12>;
2067 fsl,mdc-pin = <13>;
2068 };
2069
2070 v) Baud Rate Generators
2071
2072 Currently defined compatibles:
2073 fsl,cpm-brg
2074 fsl,cpm1-brg
2075 fsl,cpm2-brg
2076
2077 Properties:
2078 - reg : There may be an arbitrary number of reg resources; BRG
2079 numbers are assigned to these in order.
2080 - clock-frequency : Specifies the base frequency driving
2081 the BRG.
2082
2083 Example:
2084
2085 brg@119f0 {
2086 compatible = "fsl,mpc8272-brg",
2087 "fsl,cpm2-brg",
2088 "fsl,cpm-brg";
2089 reg = <119f0 10 115f0 10>;
2090 clock-frequency = <d#25000000>;
2091 };
2092
2093 vi) Interrupt Controllers
2094
2095 Currently defined compatibles:
2096 - fsl,cpm1-pic
2097 - only one interrupt cell
2098 - fsl,pq1-pic
2099 - fsl,cpm2-pic
2100 - second interrupt cell is level/sense:
2101 - 2 is falling edge
2102 - 8 is active low
2103
2104 Example:
2105
2106 interrupt-controller@10c00 {
2107 #interrupt-cells = <2>;
2108 interrupt-controller;
2109 reg = <10c00 80>;
2110 compatible = "mpc8272-pic", "fsl,cpm2-pic";
2111 };
2112
2113 vii) USB (Universal Serial Bus Controller)
2114
2115 Properties:
2116 - compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"
2117
2118 Example:
2119 usb@11bc0 {
2120 #address-cells = <1>;
2121 #size-cells = <0>;
2122 compatible = "fsl,cpm2-usb";
2123 reg = <11b60 18 8b00 100>;
2124 interrupts = <b 8>;
2125 interrupt-parent = <&PIC>;
2126 fsl,cpm-command = <2e600000>;
2127 };
2128
2129 viii) Multi-User RAM (MURAM)
2130
2131 The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
2132
2133 Ranges must be set up subject to the following restrictions:
2134
2135 - Children's reg nodes must be offsets from the start of all muram, even
2136 if the user-data area does not begin at zero.
2137 - If multiple range entries are used, the difference between the parent
2138 address and the child address must be the same in all, so that a single
2139 mapping can cover them all while maintaining the ability to determine
2140 CPM-side offsets with pointer subtraction. It is recommended that
2141 multiple range entries not be used.
2142 - A child address of zero must be translatable, even if no reg resources
2143 contain it.
2144
2145 A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
2146 indicate the portion of muram that is usable by the OS for arbitrary
2147 purposes. The data node may have an arbitrary number of reg resources,
2148 all of which contribute to the allocatable muram pool.
2149
2150 Example, based on mpc8272:
2151
2152 muram@0 {
2153 #address-cells = <1>;
2154 #size-cells = <1>;
2155 ranges = <0 0 10000>;
2156
2157 data@0 {
2158 compatible = "fsl,cpm-muram-data";
2159 reg = <0 2000 9800 800>;
2160 };
2161 };
2162
2163 m) Chipselect/Local Bus
2164
2165 Properties:
2166 - name : Should be localbus
2167 - #address-cells : Should be either two or three. The first cell is the
2168 chipselect number, and the remaining cells are the
2169 offset into the chipselect.
2170 - #size-cells : Either one or two, depending on how large each chipselect
2171 can be.
2172 - ranges : Each range corresponds to a single chipselect, and cover
2173 the entire access window as configured.
2174
2175 Example:
2176 localbus@f0010100 {
2177 compatible = "fsl,mpc8272-localbus",
2178 "fsl,pq2-localbus";
2179 #address-cells = <2>;
2180 #size-cells = <1>;
2181 reg = <f0010100 40>;
2182
2183 ranges = <0 0 fe000000 02000000
2184 1 0 f4500000 00008000>;
2185
2186 flash@0,0 {
2187 compatible = "jedec-flash";
2188 reg = <0 0 2000000>;
2189 bank-width = <4>;
2190 device-width = <1>;
2191 };
2192
2193 board-control@1,0 {
2194 reg = <1 0 20>;
2195 compatible = "fsl,mpc8272ads-bcsr";
2196 };
2197 };
2198
2199
2200 n) 4xx/Axon EMAC ethernet nodes
2201 1351
2202 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also 1352 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
2203 the Axon bridge. To operate this needs to interact with a ths 1353 the Axon bridge. To operate this needs to interact with a ths
@@ -2345,7 +1495,7 @@ platforms are moved over to use the flattened-device-tree model.
2345 available. 1495 available.
2346 For Axon: 0x0000012a 1496 For Axon: 0x0000012a
2347 1497
2348 o) Xilinx IP cores 1498 e) Xilinx IP cores
2349 1499
2350 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use 1500 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
2351 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range 1501 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
@@ -2639,206 +1789,7 @@ platforms are moved over to use the flattened-device-tree model.
2639 - reg-offset : A value of 3 is required 1789 - reg-offset : A value of 3 is required
2640 - reg-shift : A value of 2 is required 1790 - reg-shift : A value of 2 is required
2641 1791
2642 1792 f) USB EHCI controllers
2643 p) Freescale Synchronous Serial Interface
2644
2645 The SSI is a serial device that communicates with audio codecs. It can
2646 be programmed in AC97, I2S, left-justified, or right-justified modes.
2647
2648 Required properties:
2649 - compatible : compatible list, containing "fsl,ssi"
2650 - cell-index : the SSI, <0> = SSI1, <1> = SSI2, and so on
2651 - reg : offset and length of the register set for the device
2652 - interrupts : <a b> where a is the interrupt number and b is a
2653 field that represents an encoding of the sense and
2654 level information for the interrupt. This should be
2655 encoded based on the information in section 2)
2656 depending on the type of interrupt controller you
2657 have.
2658 - interrupt-parent : the phandle for the interrupt controller that
2659 services interrupts for this device.
2660 - fsl,mode : the operating mode for the SSI interface
2661 "i2s-slave" - I2S mode, SSI is clock slave
2662 "i2s-master" - I2S mode, SSI is clock master
2663 "lj-slave" - left-justified mode, SSI is clock slave
2664 "lj-master" - l.j. mode, SSI is clock master
2665 "rj-slave" - right-justified mode, SSI is clock slave
2666 "rj-master" - r.j., SSI is clock master
2667 "ac97-slave" - AC97 mode, SSI is clock slave
2668 "ac97-master" - AC97 mode, SSI is clock master
2669
2670 Optional properties:
2671 - codec-handle : phandle to a 'codec' node that defines an audio
2672 codec connected to this SSI. This node is typically
2673 a child of an I2C or other control node.
2674
2675 Child 'codec' node required properties:
2676 - compatible : compatible list, contains the name of the codec
2677
2678 Child 'codec' node optional properties:
2679 - clock-frequency : The frequency of the input clock, which typically
2680 comes from an on-board dedicated oscillator.
2681
2682 * Freescale 83xx DMA Controller
2683
2684 Freescale PowerPC 83xx have on chip general purpose DMA controllers.
2685
2686 Required properties:
2687
2688 - compatible : compatible list, contains 2 entries, first is
2689 "fsl,CHIP-dma", where CHIP is the processor
2690 (mpc8349, mpc8360, etc.) and the second is
2691 "fsl,elo-dma"
2692 - reg : <registers mapping for DMA general status reg>
2693 - ranges : Should be defined as specified in 1) to describe the
2694 DMA controller channels.
2695 - cell-index : controller index. 0 for controller @ 0x8100
2696 - interrupts : <interrupt mapping for DMA IRQ>
2697 - interrupt-parent : optional, if needed for interrupt mapping
2698
2699
2700 - DMA channel nodes:
2701 - compatible : compatible list, contains 2 entries, first is
2702 "fsl,CHIP-dma-channel", where CHIP is the processor
2703 (mpc8349, mpc8350, etc.) and the second is
2704 "fsl,elo-dma-channel"
2705 - reg : <registers mapping for channel>
2706 - cell-index : dma channel index starts at 0.
2707
2708 Optional properties:
2709 - interrupts : <interrupt mapping for DMA channel IRQ>
2710 (on 83xx this is expected to be identical to
2711 the interrupts property of the parent node)
2712 - interrupt-parent : optional, if needed for interrupt mapping
2713
2714 Example:
2715 dma@82a8 {
2716 #address-cells = <1>;
2717 #size-cells = <1>;
2718 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
2719 reg = <82a8 4>;
2720 ranges = <0 8100 1a4>;
2721 interrupt-parent = <&ipic>;
2722 interrupts = <47 8>;
2723 cell-index = <0>;
2724 dma-channel@0 {
2725 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
2726 cell-index = <0>;
2727 reg = <0 80>;
2728 };
2729 dma-channel@80 {
2730 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
2731 cell-index = <1>;
2732 reg = <80 80>;
2733 };
2734 dma-channel@100 {
2735 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
2736 cell-index = <2>;
2737 reg = <100 80>;
2738 };
2739 dma-channel@180 {
2740 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
2741 cell-index = <3>;
2742 reg = <180 80>;
2743 };
2744 };
2745
2746 * Freescale 85xx/86xx DMA Controller
2747
2748 Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.
2749
2750 Required properties:
2751
2752 - compatible : compatible list, contains 2 entries, first is
2753 "fsl,CHIP-dma", where CHIP is the processor
2754 (mpc8540, mpc8540, etc.) and the second is
2755 "fsl,eloplus-dma"
2756 - reg : <registers mapping for DMA general status reg>
2757 - cell-index : controller index. 0 for controller @ 0x21000,
2758 1 for controller @ 0xc000
2759 - ranges : Should be defined as specified in 1) to describe the
2760 DMA controller channels.
2761
2762 - DMA channel nodes:
2763 - compatible : compatible list, contains 2 entries, first is
2764 "fsl,CHIP-dma-channel", where CHIP is the processor
2765 (mpc8540, mpc8560, etc.) and the second is
2766 "fsl,eloplus-dma-channel"
2767 - cell-index : dma channel index starts at 0.
2768 - reg : <registers mapping for channel>
2769 - interrupts : <interrupt mapping for DMA channel IRQ>
2770 - interrupt-parent : optional, if needed for interrupt mapping
2771
2772 Example:
2773 dma@21300 {
2774 #address-cells = <1>;
2775 #size-cells = <1>;
2776 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
2777 reg = <21300 4>;
2778 ranges = <0 21100 200>;
2779 cell-index = <0>;
2780 dma-channel@0 {
2781 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
2782 reg = <0 80>;
2783 cell-index = <0>;
2784 interrupt-parent = <&mpic>;
2785 interrupts = <14 2>;
2786 };
2787 dma-channel@80 {
2788 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
2789 reg = <80 80>;
2790 cell-index = <1>;
2791 interrupt-parent = <&mpic>;
2792 interrupts = <15 2>;
2793 };
2794 dma-channel@100 {
2795 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
2796 reg = <100 80>;
2797 cell-index = <2>;
2798 interrupt-parent = <&mpic>;
2799 interrupts = <16 2>;
2800 };
2801 dma-channel@180 {
2802 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
2803 reg = <180 80>;
2804 cell-index = <3>;
2805 interrupt-parent = <&mpic>;
2806 interrupts = <17 2>;
2807 };
2808 };
2809
2810 * Freescale 8xxx/3.0 Gb/s SATA nodes
2811
2812 SATA nodes are defined to describe on-chip Serial ATA controllers.
2813 Each SATA port should have its own node.
2814
2815 Required properties:
2816 - compatible : compatible list, contains 2 entries, first is
2817 "fsl,CHIP-sata", where CHIP is the processor
2818 (mpc8315, mpc8379, etc.) and the second is
2819 "fsl,pq-sata"
2820 - interrupts : <interrupt mapping for SATA IRQ>
2821 - cell-index : controller index.
2822 1 for controller @ 0x18000
2823 2 for controller @ 0x19000
2824 3 for controller @ 0x1a000
2825 4 for controller @ 0x1b000
2826
2827 Optional properties:
2828 - interrupt-parent : optional, if needed for interrupt mapping
2829 - reg : <registers mapping>
2830
2831 Example:
2832
2833 sata@18000 {
2834 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
2835 reg = <0x18000 0x1000>;
2836 cell-index = <1>;
2837 interrupts = <2c 8>;
2838 interrupt-parent = < &ipic >;
2839 };
2840
2841 q) USB EHCI controllers
2842 1793
2843 Required properties: 1794 Required properties:
2844 - compatible : should be "usb-ehci". 1795 - compatible : should be "usb-ehci".
@@ -2864,109 +1815,6 @@ platforms are moved over to use the flattened-device-tree model.
2864 big-endian; 1815 big-endian;
2865 }; 1816 };
2866 1817
2867 r) Freescale Display Interface Unit
2868
2869 The Freescale DIU is a LCD controller, with proper hardware, it can also
2870 drive DVI monitors.
2871
2872 Required properties:
2873 - compatible : should be "fsl-diu".
2874 - reg : should contain at least address and length of the DIU register
2875 set.
2876 - Interrupts : one DIU interrupt should be describe here.
2877
2878 Example (MPC8610HPCD)
2879 display@2c000 {
2880 compatible = "fsl,diu";
2881 reg = <0x2c000 100>;
2882 interrupts = <72 2>;
2883 interrupt-parent = <&mpic>;
2884 };
2885
2886 s) Freescale on board FPGA
2887
2888 This is the memory-mapped registers for on board FPGA.
2889
2890 Required properities:
2891 - compatible : should be "fsl,fpga-pixis".
2892 - reg : should contain the address and the lenght of the FPPGA register
2893 set.
2894
2895 Example (MPC8610HPCD)
2896 board-control@e8000000 {
2897 compatible = "fsl,fpga-pixis";
2898 reg = <0xe8000000 32>;
2899 };
2900
2901 t) Freescale MSI interrupt controller
2902
2903 Reguired properities:
2904 - compatible : compatible list, contains 2 entries,
2905 first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
2906 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
2907 the parent type.
2908 - reg : should contain the address and the length of the shared message
2909 interrupt register set.
2910 - msi-available-ranges: use <start count> style section to define which
2911 msi interrupt can be used in the 256 msi interrupts. This property is
2912 optional, without this, all the 256 MSI interrupts can be used.
2913 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
2914 and routed to the host interrupt controller. the interrupts should
2915 be set as edge sensitive.
2916 - interrupt-parent: the phandle for the interrupt controller
2917 that services interrupts for this device. for 83xx cpu, the interrupts
2918 are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
2919 to MPIC.
2920
2921 Example
2922 msi@41600 {
2923 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
2924 reg = <0x41600 0x80>;
2925 msi-available-ranges = <0 0x100>;
2926 interrupts = <
2927 0xe0 0
2928 0xe1 0
2929 0xe2 0
2930 0xe3 0
2931 0xe4 0
2932 0xe5 0
2933 0xe6 0
2934 0xe7 0>;
2935 interrupt-parent = <&mpic>;
2936 };
2937
2938 u) Freescale General-purpose Timers Module
2939
2940 Required properties:
2941 - compatible : should be
2942 "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs
2943 "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
2944 "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
2945 - reg : should contain gtm registers location and length (0x40).
2946 - interrupts : should contain four interrupts.
2947 - interrupt-parent : interrupt source phandle.
2948 - clock-frequency : specifies the frequency driving the timer.
2949
2950 Example:
2951
2952 timer@500 {
2953 compatible = "fsl,mpc8360-gtm", "fsl,gtm";
2954 reg = <0x500 0x40>;
2955 interrupts = <90 8 78 8 84 8 72 8>;
2956 interrupt-parent = <&ipic>;
2957 /* filled by u-boot */
2958 clock-frequency = <0>;
2959 };
2960
2961 timer@440 {
2962 compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm";
2963 reg = <0x440 0x40>;
2964 interrupts = <12 13 14 15>;
2965 interrupt-parent = <&qeic>;
2966 /* filled by u-boot */
2967 clock-frequency = <0>;
2968 };
2969
2970VII - Marvell Discovery mv64[345]6x System Controller chips 1818VII - Marvell Discovery mv64[345]6x System Controller chips
2971=========================================================== 1819===========================================================
2972 1820
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 09:21:48 -0500