diff options
-rw-r--r-- | include/asm-x86_64/tlbflush.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/include/asm-x86_64/tlbflush.h b/include/asm-x86_64/tlbflush.h index 06174238252..505b0cf906d 100644 --- a/include/asm-x86_64/tlbflush.h +++ b/include/asm-x86_64/tlbflush.h | |||
@@ -56,8 +56,9 @@ extern unsigned long pgkern_mask; | |||
56 | * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages | 56 | * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages |
57 | * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables | 57 | * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables |
58 | * | 58 | * |
59 | * ..but the x86_64 has somewhat limited tlb flushing capabilities, | 59 | * x86-64 can only flush individual pages or full VMs. For a range flush |
60 | * and page-granular flushes are available only on i486 and up. | 60 | * we always do the full VM. Might be worth trying if for a small |
61 | * range a few INVLPGs in a row are a win. | ||
61 | */ | 62 | */ |
62 | 63 | ||
63 | #ifndef CONFIG_SMP | 64 | #ifndef CONFIG_SMP |
@@ -115,7 +116,9 @@ static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long st | |||
115 | static inline void flush_tlb_pgtables(struct mm_struct *mm, | 116 | static inline void flush_tlb_pgtables(struct mm_struct *mm, |
116 | unsigned long start, unsigned long end) | 117 | unsigned long start, unsigned long end) |
117 | { | 118 | { |
118 | /* x86_64 does not keep any page table caches in TLB */ | 119 | /* x86_64 does not keep any page table caches in a software TLB. |
120 | The CPUs do in their hardware TLBs, but they are handled | ||
121 | by the normal TLB flushing algorithms. */ | ||
119 | } | 122 | } |
120 | 123 | ||
121 | #endif /* _X8664_TLBFLUSH_H */ | 124 | #endif /* _X8664_TLBFLUSH_H */ |