diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/linux/i2o.h |
Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'include/linux/i2o.h')
-rw-r--r-- | include/linux/i2o.h | 1003 |
1 files changed, 1003 insertions, 0 deletions
diff --git a/include/linux/i2o.h b/include/linux/i2o.h new file mode 100644 index 00000000000..ea9a3ad4b67 --- /dev/null +++ b/include/linux/i2o.h | |||
@@ -0,0 +1,1003 @@ | |||
1 | /* | ||
2 | * I2O kernel space accessible structures/APIs | ||
3 | * | ||
4 | * (c) Copyright 1999, 2000 Red Hat Software | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * as published by the Free Software Foundation; either version | ||
9 | * 2 of the License, or (at your option) any later version. | ||
10 | * | ||
11 | ************************************************************************* | ||
12 | * | ||
13 | * This header file defined the I2O APIs/structures for use by | ||
14 | * the I2O kernel modules. | ||
15 | * | ||
16 | */ | ||
17 | |||
18 | #ifndef _I2O_H | ||
19 | #define _I2O_H | ||
20 | |||
21 | #ifdef __KERNEL__ /* This file to be included by kernel only */ | ||
22 | |||
23 | #include <linux/i2o-dev.h> | ||
24 | |||
25 | /* How many different OSM's are we allowing */ | ||
26 | #define I2O_MAX_DRIVERS 8 | ||
27 | |||
28 | #include <asm/io.h> | ||
29 | #include <asm/semaphore.h> /* Needed for MUTEX init macros */ | ||
30 | #include <linux/pci.h> | ||
31 | #include <linux/dma-mapping.h> | ||
32 | |||
33 | /* message queue empty */ | ||
34 | #define I2O_QUEUE_EMPTY 0xffffffff | ||
35 | |||
36 | /* | ||
37 | * Message structures | ||
38 | */ | ||
39 | struct i2o_message { | ||
40 | union { | ||
41 | struct { | ||
42 | u8 version_offset; | ||
43 | u8 flags; | ||
44 | u16 size; | ||
45 | u32 target_tid:12; | ||
46 | u32 init_tid:12; | ||
47 | u32 function:8; | ||
48 | u32 icntxt; /* initiator context */ | ||
49 | u32 tcntxt; /* transaction context */ | ||
50 | } s; | ||
51 | u32 head[4]; | ||
52 | } u; | ||
53 | /* List follows */ | ||
54 | u32 body[0]; | ||
55 | }; | ||
56 | |||
57 | /* | ||
58 | * Each I2O device entity has one of these. There is one per device. | ||
59 | */ | ||
60 | struct i2o_device { | ||
61 | i2o_lct_entry lct_data; /* Device LCT information */ | ||
62 | |||
63 | struct i2o_controller *iop; /* Controlling IOP */ | ||
64 | struct list_head list; /* node in IOP devices list */ | ||
65 | |||
66 | struct device device; | ||
67 | |||
68 | struct semaphore lock; /* device lock */ | ||
69 | |||
70 | struct class_device classdev; /* i2o device class */ | ||
71 | }; | ||
72 | |||
73 | /* | ||
74 | * Event structure provided to the event handling function | ||
75 | */ | ||
76 | struct i2o_event { | ||
77 | struct work_struct work; | ||
78 | struct i2o_device *i2o_dev; /* I2O device pointer from which the | ||
79 | event reply was initiated */ | ||
80 | u16 size; /* Size of data in 32-bit words */ | ||
81 | u32 tcntxt; /* Transaction context used at | ||
82 | registration */ | ||
83 | u32 event_indicator; /* Event indicator from reply */ | ||
84 | u32 data[0]; /* Event data from reply */ | ||
85 | }; | ||
86 | |||
87 | /* | ||
88 | * I2O classes which could be handled by the OSM | ||
89 | */ | ||
90 | struct i2o_class_id { | ||
91 | u16 class_id:12; | ||
92 | }; | ||
93 | |||
94 | /* | ||
95 | * I2O driver structure for OSMs | ||
96 | */ | ||
97 | struct i2o_driver { | ||
98 | char *name; /* OSM name */ | ||
99 | int context; /* Low 8 bits of the transaction info */ | ||
100 | struct i2o_class_id *classes; /* I2O classes that this OSM handles */ | ||
101 | |||
102 | /* Message reply handler */ | ||
103 | int (*reply) (struct i2o_controller *, u32, struct i2o_message *); | ||
104 | |||
105 | /* Event handler */ | ||
106 | void (*event) (struct i2o_event *); | ||
107 | |||
108 | struct workqueue_struct *event_queue; /* Event queue */ | ||
109 | |||
110 | struct device_driver driver; | ||
111 | |||
112 | /* notification of changes */ | ||
113 | void (*notify_controller_add) (struct i2o_controller *); | ||
114 | void (*notify_controller_remove) (struct i2o_controller *); | ||
115 | void (*notify_device_add) (struct i2o_device *); | ||
116 | void (*notify_device_remove) (struct i2o_device *); | ||
117 | |||
118 | struct semaphore lock; | ||
119 | }; | ||
120 | |||
121 | /* | ||
122 | * Contains all information which are necessary for DMA operations | ||
123 | */ | ||
124 | struct i2o_dma { | ||
125 | void *virt; | ||
126 | dma_addr_t phys; | ||
127 | u32 len; | ||
128 | }; | ||
129 | |||
130 | /* | ||
131 | * Context queue entry, used for 32-bit context on 64-bit systems | ||
132 | */ | ||
133 | struct i2o_context_list_element { | ||
134 | struct list_head list; | ||
135 | u32 context; | ||
136 | void *ptr; | ||
137 | unsigned long timestamp; | ||
138 | }; | ||
139 | |||
140 | /* | ||
141 | * Each I2O controller has one of these objects | ||
142 | */ | ||
143 | struct i2o_controller { | ||
144 | char name[16]; | ||
145 | int unit; | ||
146 | int type; | ||
147 | |||
148 | struct pci_dev *pdev; /* PCI device */ | ||
149 | |||
150 | unsigned int short_req:1; /* use small block sizes */ | ||
151 | unsigned int no_quiesce:1; /* dont quiesce before reset */ | ||
152 | unsigned int raptor:1; /* split bar */ | ||
153 | unsigned int promise:1; /* Promise controller */ | ||
154 | |||
155 | #ifdef CONFIG_MTRR | ||
156 | int mtrr_reg0; | ||
157 | int mtrr_reg1; | ||
158 | #endif | ||
159 | |||
160 | struct list_head devices; /* list of I2O devices */ | ||
161 | |||
162 | struct notifier_block *event_notifer; /* Events */ | ||
163 | atomic_t users; | ||
164 | struct list_head list; /* Controller list */ | ||
165 | void __iomem *post_port; /* Inbout port address */ | ||
166 | void __iomem *reply_port; /* Outbound port address */ | ||
167 | void __iomem *irq_mask; /* Interrupt register address */ | ||
168 | |||
169 | /* Dynamic LCT related data */ | ||
170 | |||
171 | struct i2o_dma status; /* status of IOP */ | ||
172 | |||
173 | struct i2o_dma hrt; /* HW Resource Table */ | ||
174 | i2o_lct *lct; /* Logical Config Table */ | ||
175 | struct i2o_dma dlct; /* Temp LCT */ | ||
176 | struct semaphore lct_lock; /* Lock for LCT updates */ | ||
177 | struct i2o_dma status_block; /* IOP status block */ | ||
178 | |||
179 | struct i2o_dma base; /* controller messaging unit */ | ||
180 | struct i2o_dma in_queue; /* inbound message queue Host->IOP */ | ||
181 | struct i2o_dma out_queue; /* outbound message queue IOP->Host */ | ||
182 | |||
183 | unsigned int battery:1; /* Has a battery backup */ | ||
184 | unsigned int io_alloc:1; /* An I/O resource was allocated */ | ||
185 | unsigned int mem_alloc:1; /* A memory resource was allocated */ | ||
186 | |||
187 | struct resource io_resource; /* I/O resource allocated to the IOP */ | ||
188 | struct resource mem_resource; /* Mem resource allocated to the IOP */ | ||
189 | |||
190 | struct proc_dir_entry *proc_entry; /* /proc dir */ | ||
191 | |||
192 | struct list_head bus_list; /* list of busses on IOP */ | ||
193 | struct device device; | ||
194 | struct i2o_device *exec; /* Executive */ | ||
195 | #if BITS_PER_LONG == 64 | ||
196 | spinlock_t context_list_lock; /* lock for context_list */ | ||
197 | atomic_t context_list_counter; /* needed for unique contexts */ | ||
198 | struct list_head context_list; /* list of context id's | ||
199 | and pointers */ | ||
200 | #endif | ||
201 | spinlock_t lock; /* lock for controller | ||
202 | configuration */ | ||
203 | |||
204 | void *driver_data[I2O_MAX_DRIVERS]; /* storage for drivers */ | ||
205 | }; | ||
206 | |||
207 | /* | ||
208 | * I2O System table entry | ||
209 | * | ||
210 | * The system table contains information about all the IOPs in the | ||
211 | * system. It is sent to all IOPs so that they can create peer2peer | ||
212 | * connections between them. | ||
213 | */ | ||
214 | struct i2o_sys_tbl_entry { | ||
215 | u16 org_id; | ||
216 | u16 reserved1; | ||
217 | u32 iop_id:12; | ||
218 | u32 reserved2:20; | ||
219 | u16 seg_num:12; | ||
220 | u16 i2o_version:4; | ||
221 | u8 iop_state; | ||
222 | u8 msg_type; | ||
223 | u16 frame_size; | ||
224 | u16 reserved3; | ||
225 | u32 last_changed; | ||
226 | u32 iop_capabilities; | ||
227 | u32 inbound_low; | ||
228 | u32 inbound_high; | ||
229 | }; | ||
230 | |||
231 | struct i2o_sys_tbl { | ||
232 | u8 num_entries; | ||
233 | u8 version; | ||
234 | u16 reserved1; | ||
235 | u32 change_ind; | ||
236 | u32 reserved2; | ||
237 | u32 reserved3; | ||
238 | struct i2o_sys_tbl_entry iops[0]; | ||
239 | }; | ||
240 | |||
241 | extern struct list_head i2o_controllers; | ||
242 | |||
243 | /* Message functions */ | ||
244 | static inline u32 i2o_msg_get(struct i2o_controller *, struct i2o_message __iomem **); | ||
245 | extern u32 i2o_msg_get_wait(struct i2o_controller *, struct i2o_message __iomem **, | ||
246 | int); | ||
247 | static inline void i2o_msg_post(struct i2o_controller *, u32); | ||
248 | static inline int i2o_msg_post_wait(struct i2o_controller *, u32, | ||
249 | unsigned long); | ||
250 | extern int i2o_msg_post_wait_mem(struct i2o_controller *, u32, unsigned long, | ||
251 | struct i2o_dma *); | ||
252 | extern void i2o_msg_nop(struct i2o_controller *, u32); | ||
253 | static inline void i2o_flush_reply(struct i2o_controller *, u32); | ||
254 | |||
255 | /* DMA handling functions */ | ||
256 | static inline int i2o_dma_alloc(struct device *, struct i2o_dma *, size_t, | ||
257 | unsigned int); | ||
258 | static inline void i2o_dma_free(struct device *, struct i2o_dma *); | ||
259 | int i2o_dma_realloc(struct device *, struct i2o_dma *, size_t, unsigned int); | ||
260 | |||
261 | static inline int i2o_dma_map(struct device *, struct i2o_dma *); | ||
262 | static inline void i2o_dma_unmap(struct device *, struct i2o_dma *); | ||
263 | |||
264 | /* IOP functions */ | ||
265 | extern int i2o_status_get(struct i2o_controller *); | ||
266 | |||
267 | extern int i2o_event_register(struct i2o_device *, struct i2o_driver *, int, | ||
268 | u32); | ||
269 | extern struct i2o_device *i2o_iop_find_device(struct i2o_controller *, u16); | ||
270 | extern struct i2o_controller *i2o_find_iop(int); | ||
271 | |||
272 | /* Functions needed for handling 64-bit pointers in 32-bit context */ | ||
273 | #if BITS_PER_LONG == 64 | ||
274 | extern u32 i2o_cntxt_list_add(struct i2o_controller *, void *); | ||
275 | extern void *i2o_cntxt_list_get(struct i2o_controller *, u32); | ||
276 | extern u32 i2o_cntxt_list_remove(struct i2o_controller *, void *); | ||
277 | extern u32 i2o_cntxt_list_get_ptr(struct i2o_controller *, void *); | ||
278 | |||
279 | static inline u32 i2o_ptr_low(void *ptr) | ||
280 | { | ||
281 | return (u32) (u64) ptr; | ||
282 | }; | ||
283 | |||
284 | static inline u32 i2o_ptr_high(void *ptr) | ||
285 | { | ||
286 | return (u32) ((u64) ptr >> 32); | ||
287 | }; | ||
288 | #else | ||
289 | static inline u32 i2o_cntxt_list_add(struct i2o_controller *c, void *ptr) | ||
290 | { | ||
291 | return (u32) ptr; | ||
292 | }; | ||
293 | |||
294 | static inline void *i2o_cntxt_list_get(struct i2o_controller *c, u32 context) | ||
295 | { | ||
296 | return (void *)context; | ||
297 | }; | ||
298 | |||
299 | static inline u32 i2o_cntxt_list_remove(struct i2o_controller *c, void *ptr) | ||
300 | { | ||
301 | return (u32) ptr; | ||
302 | }; | ||
303 | |||
304 | static inline u32 i2o_cntxt_list_get_ptr(struct i2o_controller *c, void *ptr) | ||
305 | { | ||
306 | return (u32) ptr; | ||
307 | }; | ||
308 | |||
309 | static inline u32 i2o_ptr_low(void *ptr) | ||
310 | { | ||
311 | return (u32) ptr; | ||
312 | }; | ||
313 | |||
314 | static inline u32 i2o_ptr_high(void *ptr) | ||
315 | { | ||
316 | return 0; | ||
317 | }; | ||
318 | #endif | ||
319 | |||
320 | /* I2O driver (OSM) functions */ | ||
321 | extern int i2o_driver_register(struct i2o_driver *); | ||
322 | extern void i2o_driver_unregister(struct i2o_driver *); | ||
323 | |||
324 | /** | ||
325 | * i2o_driver_notify_controller_add - Send notification of added controller | ||
326 | * to a single I2O driver | ||
327 | * | ||
328 | * Send notification of added controller to a single registered driver. | ||
329 | */ | ||
330 | static inline void i2o_driver_notify_controller_add(struct i2o_driver *drv, | ||
331 | struct i2o_controller *c) | ||
332 | { | ||
333 | if (drv->notify_controller_add) | ||
334 | drv->notify_controller_add(c); | ||
335 | }; | ||
336 | |||
337 | /** | ||
338 | * i2o_driver_notify_controller_remove - Send notification of removed | ||
339 | * controller to a single I2O driver | ||
340 | * | ||
341 | * Send notification of removed controller to a single registered driver. | ||
342 | */ | ||
343 | static inline void i2o_driver_notify_controller_remove(struct i2o_driver *drv, | ||
344 | struct i2o_controller *c) | ||
345 | { | ||
346 | if (drv->notify_controller_remove) | ||
347 | drv->notify_controller_remove(c); | ||
348 | }; | ||
349 | |||
350 | /** | ||
351 | * i2o_driver_notify_device_add - Send notification of added device to a | ||
352 | * single I2O driver | ||
353 | * | ||
354 | * Send notification of added device to a single registered driver. | ||
355 | */ | ||
356 | static inline void i2o_driver_notify_device_add(struct i2o_driver *drv, | ||
357 | struct i2o_device *i2o_dev) | ||
358 | { | ||
359 | if (drv->notify_device_add) | ||
360 | drv->notify_device_add(i2o_dev); | ||
361 | }; | ||
362 | |||
363 | /** | ||
364 | * i2o_driver_notify_device_remove - Send notification of removed device | ||
365 | * to a single I2O driver | ||
366 | * | ||
367 | * Send notification of removed device to a single registered driver. | ||
368 | */ | ||
369 | static inline void i2o_driver_notify_device_remove(struct i2o_driver *drv, | ||
370 | struct i2o_device *i2o_dev) | ||
371 | { | ||
372 | if (drv->notify_device_remove) | ||
373 | drv->notify_device_remove(i2o_dev); | ||
374 | }; | ||
375 | |||
376 | extern void i2o_driver_notify_controller_add_all(struct i2o_controller *); | ||
377 | extern void i2o_driver_notify_controller_remove_all(struct i2o_controller *); | ||
378 | extern void i2o_driver_notify_device_add_all(struct i2o_device *); | ||
379 | extern void i2o_driver_notify_device_remove_all(struct i2o_device *); | ||
380 | |||
381 | /* I2O device functions */ | ||
382 | extern int i2o_device_claim(struct i2o_device *); | ||
383 | extern int i2o_device_claim_release(struct i2o_device *); | ||
384 | |||
385 | /* Exec OSM functions */ | ||
386 | extern int i2o_exec_lct_get(struct i2o_controller *); | ||
387 | |||
388 | /* device to i2o_device and driver to i2o_driver convertion functions */ | ||
389 | #define to_i2o_driver(drv) container_of(drv,struct i2o_driver, driver) | ||
390 | #define to_i2o_device(dev) container_of(dev, struct i2o_device, device) | ||
391 | |||
392 | /* | ||
393 | * Messenger inlines | ||
394 | */ | ||
395 | static inline u32 I2O_POST_READ32(struct i2o_controller *c) | ||
396 | { | ||
397 | rmb(); | ||
398 | return readl(c->post_port); | ||
399 | }; | ||
400 | |||
401 | static inline void I2O_POST_WRITE32(struct i2o_controller *c, u32 val) | ||
402 | { | ||
403 | wmb(); | ||
404 | writel(val, c->post_port); | ||
405 | }; | ||
406 | |||
407 | static inline u32 I2O_REPLY_READ32(struct i2o_controller *c) | ||
408 | { | ||
409 | rmb(); | ||
410 | return readl(c->reply_port); | ||
411 | }; | ||
412 | |||
413 | static inline void I2O_REPLY_WRITE32(struct i2o_controller *c, u32 val) | ||
414 | { | ||
415 | wmb(); | ||
416 | writel(val, c->reply_port); | ||
417 | }; | ||
418 | |||
419 | static inline u32 I2O_IRQ_READ32(struct i2o_controller *c) | ||
420 | { | ||
421 | rmb(); | ||
422 | return readl(c->irq_mask); | ||
423 | }; | ||
424 | |||
425 | static inline void I2O_IRQ_WRITE32(struct i2o_controller *c, u32 val) | ||
426 | { | ||
427 | wmb(); | ||
428 | writel(val, c->irq_mask); | ||
429 | wmb(); | ||
430 | }; | ||
431 | |||
432 | /** | ||
433 | * i2o_msg_get - obtain an I2O message from the IOP | ||
434 | * @c: I2O controller | ||
435 | * @msg: pointer to a I2O message pointer | ||
436 | * | ||
437 | * This function tries to get a message slot. If no message slot is | ||
438 | * available do not wait until one is availabe (see also i2o_msg_get_wait). | ||
439 | * | ||
440 | * On a success the message is returned and the pointer to the message is | ||
441 | * set in msg. The returned message is the physical page frame offset | ||
442 | * address from the read port (see the i2o spec). If no message is | ||
443 | * available returns I2O_QUEUE_EMPTY and msg is leaved untouched. | ||
444 | */ | ||
445 | static inline u32 i2o_msg_get(struct i2o_controller *c, | ||
446 | struct i2o_message __iomem **msg) | ||
447 | { | ||
448 | u32 m; | ||
449 | |||
450 | if ((m = I2O_POST_READ32(c)) != I2O_QUEUE_EMPTY) | ||
451 | *msg = c->in_queue.virt + m; | ||
452 | |||
453 | return m; | ||
454 | }; | ||
455 | |||
456 | /** | ||
457 | * i2o_msg_post - Post I2O message to I2O controller | ||
458 | * @c: I2O controller to which the message should be send | ||
459 | * @m: the message identifier | ||
460 | * | ||
461 | * Post the message to the I2O controller. | ||
462 | */ | ||
463 | static inline void i2o_msg_post(struct i2o_controller *c, u32 m) | ||
464 | { | ||
465 | I2O_POST_WRITE32(c, m); | ||
466 | }; | ||
467 | |||
468 | /** | ||
469 | * i2o_msg_post_wait - Post and wait a message and wait until return | ||
470 | * @c: controller | ||
471 | * @m: message to post | ||
472 | * @timeout: time in seconds to wait | ||
473 | * | ||
474 | * This API allows an OSM to post a message and then be told whether or | ||
475 | * not the system received a successful reply. If the message times out | ||
476 | * then the value '-ETIMEDOUT' is returned. | ||
477 | * | ||
478 | * Returns 0 on success or negative error code on failure. | ||
479 | */ | ||
480 | static inline int i2o_msg_post_wait(struct i2o_controller *c, u32 m, | ||
481 | unsigned long timeout) | ||
482 | { | ||
483 | return i2o_msg_post_wait_mem(c, m, timeout, NULL); | ||
484 | }; | ||
485 | |||
486 | /** | ||
487 | * i2o_flush_reply - Flush reply from I2O controller | ||
488 | * @c: I2O controller | ||
489 | * @m: the message identifier | ||
490 | * | ||
491 | * The I2O controller must be informed that the reply message is not needed | ||
492 | * anymore. If you forget to flush the reply, the message frame can't be | ||
493 | * used by the controller anymore and is therefore lost. | ||
494 | * | ||
495 | * FIXME: is there a timeout after which the controller reuse the message? | ||
496 | */ | ||
497 | static inline void i2o_flush_reply(struct i2o_controller *c, u32 m) | ||
498 | { | ||
499 | I2O_REPLY_WRITE32(c, m); | ||
500 | }; | ||
501 | |||
502 | /** | ||
503 | * i2o_out_to_virt - Turn an I2O message to a virtual address | ||
504 | * @c: controller | ||
505 | * @m: message engine value | ||
506 | * | ||
507 | * Turn a receive message from an I2O controller bus address into | ||
508 | * a Linux virtual address. The shared page frame is a linear block | ||
509 | * so we simply have to shift the offset. This function does not | ||
510 | * work for sender side messages as they are ioremap objects | ||
511 | * provided by the I2O controller. | ||
512 | */ | ||
513 | static inline struct i2o_message *i2o_msg_out_to_virt(struct i2o_controller *c, | ||
514 | u32 m) | ||
515 | { | ||
516 | BUG_ON(m < c->out_queue.phys | ||
517 | || m >= c->out_queue.phys + c->out_queue.len); | ||
518 | |||
519 | return c->out_queue.virt + (m - c->out_queue.phys); | ||
520 | }; | ||
521 | |||
522 | /** | ||
523 | * i2o_msg_in_to_virt - Turn an I2O message to a virtual address | ||
524 | * @c: controller | ||
525 | * @m: message engine value | ||
526 | * | ||
527 | * Turn a send message from an I2O controller bus address into | ||
528 | * a Linux virtual address. The shared page frame is a linear block | ||
529 | * so we simply have to shift the offset. This function does not | ||
530 | * work for receive side messages as they are kmalloc objects | ||
531 | * in a different pool. | ||
532 | */ | ||
533 | static inline struct i2o_message __iomem *i2o_msg_in_to_virt(struct i2o_controller *c, | ||
534 | u32 m) | ||
535 | { | ||
536 | return c->in_queue.virt + m; | ||
537 | }; | ||
538 | |||
539 | /** | ||
540 | * i2o_dma_alloc - Allocate DMA memory | ||
541 | * @dev: struct device pointer to the PCI device of the I2O controller | ||
542 | * @addr: i2o_dma struct which should get the DMA buffer | ||
543 | * @len: length of the new DMA memory | ||
544 | * @gfp_mask: GFP mask | ||
545 | * | ||
546 | * Allocate a coherent DMA memory and write the pointers into addr. | ||
547 | * | ||
548 | * Returns 0 on success or -ENOMEM on failure. | ||
549 | */ | ||
550 | static inline int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr, | ||
551 | size_t len, unsigned int gfp_mask) | ||
552 | { | ||
553 | addr->virt = dma_alloc_coherent(dev, len, &addr->phys, gfp_mask); | ||
554 | if (!addr->virt) | ||
555 | return -ENOMEM; | ||
556 | |||
557 | memset(addr->virt, 0, len); | ||
558 | addr->len = len; | ||
559 | |||
560 | return 0; | ||
561 | }; | ||
562 | |||
563 | /** | ||
564 | * i2o_dma_free - Free DMA memory | ||
565 | * @dev: struct device pointer to the PCI device of the I2O controller | ||
566 | * @addr: i2o_dma struct which contains the DMA buffer | ||
567 | * | ||
568 | * Free a coherent DMA memory and set virtual address of addr to NULL. | ||
569 | */ | ||
570 | static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr) | ||
571 | { | ||
572 | if (addr->virt) { | ||
573 | if (addr->phys) | ||
574 | dma_free_coherent(dev, addr->len, addr->virt, | ||
575 | addr->phys); | ||
576 | else | ||
577 | kfree(addr->virt); | ||
578 | addr->virt = NULL; | ||
579 | } | ||
580 | }; | ||
581 | |||
582 | /** | ||
583 | * i2o_dma_map - Map the memory to DMA | ||
584 | * @dev: struct device pointer to the PCI device of the I2O controller | ||
585 | * @addr: i2o_dma struct which should be mapped | ||
586 | * | ||
587 | * Map the memory in addr->virt to coherent DMA memory and write the | ||
588 | * physical address into addr->phys. | ||
589 | * | ||
590 | * Returns 0 on success or -ENOMEM on failure. | ||
591 | */ | ||
592 | static inline int i2o_dma_map(struct device *dev, struct i2o_dma *addr) | ||
593 | { | ||
594 | if (!addr->virt) | ||
595 | return -EFAULT; | ||
596 | |||
597 | if (!addr->phys) | ||
598 | addr->phys = dma_map_single(dev, addr->virt, addr->len, | ||
599 | DMA_BIDIRECTIONAL); | ||
600 | if (!addr->phys) | ||
601 | return -ENOMEM; | ||
602 | |||
603 | return 0; | ||
604 | }; | ||
605 | |||
606 | /** | ||
607 | * i2o_dma_unmap - Unmap the DMA memory | ||
608 | * @dev: struct device pointer to the PCI device of the I2O controller | ||
609 | * @addr: i2o_dma struct which should be unmapped | ||
610 | * | ||
611 | * Unmap the memory in addr->virt from DMA memory. | ||
612 | */ | ||
613 | static inline void i2o_dma_unmap(struct device *dev, struct i2o_dma *addr) | ||
614 | { | ||
615 | if (!addr->virt) | ||
616 | return; | ||
617 | |||
618 | if (addr->phys) { | ||
619 | dma_unmap_single(dev, addr->phys, addr->len, DMA_BIDIRECTIONAL); | ||
620 | addr->phys = 0; | ||
621 | } | ||
622 | }; | ||
623 | |||
624 | /* | ||
625 | * Endian handling wrapped into the macro - keeps the core code | ||
626 | * cleaner. | ||
627 | */ | ||
628 | |||
629 | #define i2o_raw_writel(val, mem) __raw_writel(cpu_to_le32(val), mem) | ||
630 | |||
631 | extern int i2o_parm_field_get(struct i2o_device *, int, int, void *, int); | ||
632 | extern int i2o_parm_table_get(struct i2o_device *, int, int, int, void *, int, | ||
633 | void *, int); | ||
634 | |||
635 | /* debugging and troubleshooting/diagnostic helpers. */ | ||
636 | #define osm_printk(level, format, arg...) \ | ||
637 | printk(level "%s: " format, OSM_NAME , ## arg) | ||
638 | |||
639 | #ifdef DEBUG | ||
640 | #define osm_debug(format, arg...) \ | ||
641 | osm_printk(KERN_DEBUG, format , ## arg) | ||
642 | #else | ||
643 | #define osm_debug(format, arg...) \ | ||
644 | do { } while (0) | ||
645 | #endif | ||
646 | |||
647 | #define osm_err(format, arg...) \ | ||
648 | osm_printk(KERN_ERR, format , ## arg) | ||
649 | #define osm_info(format, arg...) \ | ||
650 | osm_printk(KERN_INFO, format , ## arg) | ||
651 | #define osm_warn(format, arg...) \ | ||
652 | osm_printk(KERN_WARNING, format , ## arg) | ||
653 | |||
654 | /* debugging functions */ | ||
655 | extern void i2o_report_status(const char *, const char *, struct i2o_message *); | ||
656 | extern void i2o_dump_message(struct i2o_message *); | ||
657 | extern void i2o_dump_hrt(struct i2o_controller *c); | ||
658 | extern void i2o_debug_state(struct i2o_controller *c); | ||
659 | |||
660 | /* | ||
661 | * Cache strategies | ||
662 | */ | ||
663 | |||
664 | /* The NULL strategy leaves everything up to the controller. This tends to be a | ||
665 | * pessimal but functional choice. | ||
666 | */ | ||
667 | #define CACHE_NULL 0 | ||
668 | /* Prefetch data when reading. We continually attempt to load the next 32 sectors | ||
669 | * into the controller cache. | ||
670 | */ | ||
671 | #define CACHE_PREFETCH 1 | ||
672 | /* Prefetch data when reading. We sometimes attempt to load the next 32 sectors | ||
673 | * into the controller cache. When an I/O is less <= 8K we assume its probably | ||
674 | * not sequential and don't prefetch (default) | ||
675 | */ | ||
676 | #define CACHE_SMARTFETCH 2 | ||
677 | /* Data is written to the cache and then out on to the disk. The I/O must be | ||
678 | * physically on the medium before the write is acknowledged (default without | ||
679 | * NVRAM) | ||
680 | */ | ||
681 | #define CACHE_WRITETHROUGH 17 | ||
682 | /* Data is written to the cache and then out on to the disk. The controller | ||
683 | * is permitted to write back the cache any way it wants. (default if battery | ||
684 | * backed NVRAM is present). It can be useful to set this for swap regardless of | ||
685 | * battery state. | ||
686 | */ | ||
687 | #define CACHE_WRITEBACK 18 | ||
688 | /* Optimise for under powered controllers, especially on RAID1 and RAID0. We | ||
689 | * write large I/O's directly to disk bypassing the cache to avoid the extra | ||
690 | * memory copy hits. Small writes are writeback cached | ||
691 | */ | ||
692 | #define CACHE_SMARTBACK 19 | ||
693 | /* Optimise for under powered controllers, especially on RAID1 and RAID0. We | ||
694 | * write large I/O's directly to disk bypassing the cache to avoid the extra | ||
695 | * memory copy hits. Small writes are writethrough cached. Suitable for devices | ||
696 | * lacking battery backup | ||
697 | */ | ||
698 | #define CACHE_SMARTTHROUGH 20 | ||
699 | |||
700 | /* | ||
701 | * Ioctl structures | ||
702 | */ | ||
703 | |||
704 | #define BLKI2OGRSTRAT _IOR('2', 1, int) | ||
705 | #define BLKI2OGWSTRAT _IOR('2', 2, int) | ||
706 | #define BLKI2OSRSTRAT _IOW('2', 3, int) | ||
707 | #define BLKI2OSWSTRAT _IOW('2', 4, int) | ||
708 | |||
709 | /* | ||
710 | * I2O Function codes | ||
711 | */ | ||
712 | |||
713 | /* | ||
714 | * Executive Class | ||
715 | */ | ||
716 | #define I2O_CMD_ADAPTER_ASSIGN 0xB3 | ||
717 | #define I2O_CMD_ADAPTER_READ 0xB2 | ||
718 | #define I2O_CMD_ADAPTER_RELEASE 0xB5 | ||
719 | #define I2O_CMD_BIOS_INFO_SET 0xA5 | ||
720 | #define I2O_CMD_BOOT_DEVICE_SET 0xA7 | ||
721 | #define I2O_CMD_CONFIG_VALIDATE 0xBB | ||
722 | #define I2O_CMD_CONN_SETUP 0xCA | ||
723 | #define I2O_CMD_DDM_DESTROY 0xB1 | ||
724 | #define I2O_CMD_DDM_ENABLE 0xD5 | ||
725 | #define I2O_CMD_DDM_QUIESCE 0xC7 | ||
726 | #define I2O_CMD_DDM_RESET 0xD9 | ||
727 | #define I2O_CMD_DDM_SUSPEND 0xAF | ||
728 | #define I2O_CMD_DEVICE_ASSIGN 0xB7 | ||
729 | #define I2O_CMD_DEVICE_RELEASE 0xB9 | ||
730 | #define I2O_CMD_HRT_GET 0xA8 | ||
731 | #define I2O_CMD_ADAPTER_CLEAR 0xBE | ||
732 | #define I2O_CMD_ADAPTER_CONNECT 0xC9 | ||
733 | #define I2O_CMD_ADAPTER_RESET 0xBD | ||
734 | #define I2O_CMD_LCT_NOTIFY 0xA2 | ||
735 | #define I2O_CMD_OUTBOUND_INIT 0xA1 | ||
736 | #define I2O_CMD_PATH_ENABLE 0xD3 | ||
737 | #define I2O_CMD_PATH_QUIESCE 0xC5 | ||
738 | #define I2O_CMD_PATH_RESET 0xD7 | ||
739 | #define I2O_CMD_STATIC_MF_CREATE 0xDD | ||
740 | #define I2O_CMD_STATIC_MF_RELEASE 0xDF | ||
741 | #define I2O_CMD_STATUS_GET 0xA0 | ||
742 | #define I2O_CMD_SW_DOWNLOAD 0xA9 | ||
743 | #define I2O_CMD_SW_UPLOAD 0xAB | ||
744 | #define I2O_CMD_SW_REMOVE 0xAD | ||
745 | #define I2O_CMD_SYS_ENABLE 0xD1 | ||
746 | #define I2O_CMD_SYS_MODIFY 0xC1 | ||
747 | #define I2O_CMD_SYS_QUIESCE 0xC3 | ||
748 | #define I2O_CMD_SYS_TAB_SET 0xA3 | ||
749 | |||
750 | /* | ||
751 | * Utility Class | ||
752 | */ | ||
753 | #define I2O_CMD_UTIL_NOP 0x00 | ||
754 | #define I2O_CMD_UTIL_ABORT 0x01 | ||
755 | #define I2O_CMD_UTIL_CLAIM 0x09 | ||
756 | #define I2O_CMD_UTIL_RELEASE 0x0B | ||
757 | #define I2O_CMD_UTIL_PARAMS_GET 0x06 | ||
758 | #define I2O_CMD_UTIL_PARAMS_SET 0x05 | ||
759 | #define I2O_CMD_UTIL_EVT_REGISTER 0x13 | ||
760 | #define I2O_CMD_UTIL_EVT_ACK 0x14 | ||
761 | #define I2O_CMD_UTIL_CONFIG_DIALOG 0x10 | ||
762 | #define I2O_CMD_UTIL_DEVICE_RESERVE 0x0D | ||
763 | #define I2O_CMD_UTIL_DEVICE_RELEASE 0x0F | ||
764 | #define I2O_CMD_UTIL_LOCK 0x17 | ||
765 | #define I2O_CMD_UTIL_LOCK_RELEASE 0x19 | ||
766 | #define I2O_CMD_UTIL_REPLY_FAULT_NOTIFY 0x15 | ||
767 | |||
768 | /* | ||
769 | * SCSI Host Bus Adapter Class | ||
770 | */ | ||
771 | #define I2O_CMD_SCSI_EXEC 0x81 | ||
772 | #define I2O_CMD_SCSI_ABORT 0x83 | ||
773 | #define I2O_CMD_SCSI_BUSRESET 0x27 | ||
774 | |||
775 | /* | ||
776 | * Random Block Storage Class | ||
777 | */ | ||
778 | #define I2O_CMD_BLOCK_READ 0x30 | ||
779 | #define I2O_CMD_BLOCK_WRITE 0x31 | ||
780 | #define I2O_CMD_BLOCK_CFLUSH 0x37 | ||
781 | #define I2O_CMD_BLOCK_MLOCK 0x49 | ||
782 | #define I2O_CMD_BLOCK_MUNLOCK 0x4B | ||
783 | #define I2O_CMD_BLOCK_MMOUNT 0x41 | ||
784 | #define I2O_CMD_BLOCK_MEJECT 0x43 | ||
785 | #define I2O_CMD_BLOCK_POWER 0x70 | ||
786 | |||
787 | #define I2O_PRIVATE_MSG 0xFF | ||
788 | |||
789 | /* Command status values */ | ||
790 | |||
791 | #define I2O_CMD_IN_PROGRESS 0x01 | ||
792 | #define I2O_CMD_REJECTED 0x02 | ||
793 | #define I2O_CMD_FAILED 0x03 | ||
794 | #define I2O_CMD_COMPLETED 0x04 | ||
795 | |||
796 | /* I2O API function return values */ | ||
797 | |||
798 | #define I2O_RTN_NO_ERROR 0 | ||
799 | #define I2O_RTN_NOT_INIT 1 | ||
800 | #define I2O_RTN_FREE_Q_EMPTY 2 | ||
801 | #define I2O_RTN_TCB_ERROR 3 | ||
802 | #define I2O_RTN_TRANSACTION_ERROR 4 | ||
803 | #define I2O_RTN_ADAPTER_ALREADY_INIT 5 | ||
804 | #define I2O_RTN_MALLOC_ERROR 6 | ||
805 | #define I2O_RTN_ADPTR_NOT_REGISTERED 7 | ||
806 | #define I2O_RTN_MSG_REPLY_TIMEOUT 8 | ||
807 | #define I2O_RTN_NO_STATUS 9 | ||
808 | #define I2O_RTN_NO_FIRM_VER 10 | ||
809 | #define I2O_RTN_NO_LINK_SPEED 11 | ||
810 | |||
811 | /* Reply message status defines for all messages */ | ||
812 | |||
813 | #define I2O_REPLY_STATUS_SUCCESS 0x00 | ||
814 | #define I2O_REPLY_STATUS_ABORT_DIRTY 0x01 | ||
815 | #define I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER 0x02 | ||
816 | #define I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER 0x03 | ||
817 | #define I2O_REPLY_STATUS_ERROR_DIRTY 0x04 | ||
818 | #define I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER 0x05 | ||
819 | #define I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER 0x06 | ||
820 | #define I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY 0x08 | ||
821 | #define I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER 0x09 | ||
822 | #define I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER 0x0A | ||
823 | #define I2O_REPLY_STATUS_TRANSACTION_ERROR 0x0B | ||
824 | #define I2O_REPLY_STATUS_PROGRESS_REPORT 0x80 | ||
825 | |||
826 | /* Status codes and Error Information for Parameter functions */ | ||
827 | |||
828 | #define I2O_PARAMS_STATUS_SUCCESS 0x00 | ||
829 | #define I2O_PARAMS_STATUS_BAD_KEY_ABORT 0x01 | ||
830 | #define I2O_PARAMS_STATUS_BAD_KEY_CONTINUE 0x02 | ||
831 | #define I2O_PARAMS_STATUS_BUFFER_FULL 0x03 | ||
832 | #define I2O_PARAMS_STATUS_BUFFER_TOO_SMALL 0x04 | ||
833 | #define I2O_PARAMS_STATUS_FIELD_UNREADABLE 0x05 | ||
834 | #define I2O_PARAMS_STATUS_FIELD_UNWRITEABLE 0x06 | ||
835 | #define I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS 0x07 | ||
836 | #define I2O_PARAMS_STATUS_INVALID_GROUP_ID 0x08 | ||
837 | #define I2O_PARAMS_STATUS_INVALID_OPERATION 0x09 | ||
838 | #define I2O_PARAMS_STATUS_NO_KEY_FIELD 0x0A | ||
839 | #define I2O_PARAMS_STATUS_NO_SUCH_FIELD 0x0B | ||
840 | #define I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP 0x0C | ||
841 | #define I2O_PARAMS_STATUS_OPERATION_ERROR 0x0D | ||
842 | #define I2O_PARAMS_STATUS_SCALAR_ERROR 0x0E | ||
843 | #define I2O_PARAMS_STATUS_TABLE_ERROR 0x0F | ||
844 | #define I2O_PARAMS_STATUS_WRONG_GROUP_TYPE 0x10 | ||
845 | |||
846 | /* DetailedStatusCode defines for Executive, DDM, Util and Transaction error | ||
847 | * messages: Table 3-2 Detailed Status Codes.*/ | ||
848 | |||
849 | #define I2O_DSC_SUCCESS 0x0000 | ||
850 | #define I2O_DSC_BAD_KEY 0x0002 | ||
851 | #define I2O_DSC_TCL_ERROR 0x0003 | ||
852 | #define I2O_DSC_REPLY_BUFFER_FULL 0x0004 | ||
853 | #define I2O_DSC_NO_SUCH_PAGE 0x0005 | ||
854 | #define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT 0x0006 | ||
855 | #define I2O_DSC_INSUFFICIENT_RESOURCE_HARD 0x0007 | ||
856 | #define I2O_DSC_CHAIN_BUFFER_TOO_LARGE 0x0009 | ||
857 | #define I2O_DSC_UNSUPPORTED_FUNCTION 0x000A | ||
858 | #define I2O_DSC_DEVICE_LOCKED 0x000B | ||
859 | #define I2O_DSC_DEVICE_RESET 0x000C | ||
860 | #define I2O_DSC_INAPPROPRIATE_FUNCTION 0x000D | ||
861 | #define I2O_DSC_INVALID_INITIATOR_ADDRESS 0x000E | ||
862 | #define I2O_DSC_INVALID_MESSAGE_FLAGS 0x000F | ||
863 | #define I2O_DSC_INVALID_OFFSET 0x0010 | ||
864 | #define I2O_DSC_INVALID_PARAMETER 0x0011 | ||
865 | #define I2O_DSC_INVALID_REQUEST 0x0012 | ||
866 | #define I2O_DSC_INVALID_TARGET_ADDRESS 0x0013 | ||
867 | #define I2O_DSC_MESSAGE_TOO_LARGE 0x0014 | ||
868 | #define I2O_DSC_MESSAGE_TOO_SMALL 0x0015 | ||
869 | #define I2O_DSC_MISSING_PARAMETER 0x0016 | ||
870 | #define I2O_DSC_TIMEOUT 0x0017 | ||
871 | #define I2O_DSC_UNKNOWN_ERROR 0x0018 | ||
872 | #define I2O_DSC_UNKNOWN_FUNCTION 0x0019 | ||
873 | #define I2O_DSC_UNSUPPORTED_VERSION 0x001A | ||
874 | #define I2O_DSC_DEVICE_BUSY 0x001B | ||
875 | #define I2O_DSC_DEVICE_NOT_AVAILABLE 0x001C | ||
876 | |||
877 | /* DetailedStatusCode defines for Block Storage Operation: Table 6-7 Detailed | ||
878 | Status Codes.*/ | ||
879 | |||
880 | #define I2O_BSA_DSC_SUCCESS 0x0000 | ||
881 | #define I2O_BSA_DSC_MEDIA_ERROR 0x0001 | ||
882 | #define I2O_BSA_DSC_ACCESS_ERROR 0x0002 | ||
883 | #define I2O_BSA_DSC_DEVICE_FAILURE 0x0003 | ||
884 | #define I2O_BSA_DSC_DEVICE_NOT_READY 0x0004 | ||
885 | #define I2O_BSA_DSC_MEDIA_NOT_PRESENT 0x0005 | ||
886 | #define I2O_BSA_DSC_MEDIA_LOCKED 0x0006 | ||
887 | #define I2O_BSA_DSC_MEDIA_FAILURE 0x0007 | ||
888 | #define I2O_BSA_DSC_PROTOCOL_FAILURE 0x0008 | ||
889 | #define I2O_BSA_DSC_BUS_FAILURE 0x0009 | ||
890 | #define I2O_BSA_DSC_ACCESS_VIOLATION 0x000A | ||
891 | #define I2O_BSA_DSC_WRITE_PROTECTED 0x000B | ||
892 | #define I2O_BSA_DSC_DEVICE_RESET 0x000C | ||
893 | #define I2O_BSA_DSC_VOLUME_CHANGED 0x000D | ||
894 | #define I2O_BSA_DSC_TIMEOUT 0x000E | ||
895 | |||
896 | /* FailureStatusCodes, Table 3-3 Message Failure Codes */ | ||
897 | |||
898 | #define I2O_FSC_TRANSPORT_SERVICE_SUSPENDED 0x81 | ||
899 | #define I2O_FSC_TRANSPORT_SERVICE_TERMINATED 0x82 | ||
900 | #define I2O_FSC_TRANSPORT_CONGESTION 0x83 | ||
901 | #define I2O_FSC_TRANSPORT_FAILURE 0x84 | ||
902 | #define I2O_FSC_TRANSPORT_STATE_ERROR 0x85 | ||
903 | #define I2O_FSC_TRANSPORT_TIME_OUT 0x86 | ||
904 | #define I2O_FSC_TRANSPORT_ROUTING_FAILURE 0x87 | ||
905 | #define I2O_FSC_TRANSPORT_INVALID_VERSION 0x88 | ||
906 | #define I2O_FSC_TRANSPORT_INVALID_OFFSET 0x89 | ||
907 | #define I2O_FSC_TRANSPORT_INVALID_MSG_FLAGS 0x8A | ||
908 | #define I2O_FSC_TRANSPORT_FRAME_TOO_SMALL 0x8B | ||
909 | #define I2O_FSC_TRANSPORT_FRAME_TOO_LARGE 0x8C | ||
910 | #define I2O_FSC_TRANSPORT_INVALID_TARGET_ID 0x8D | ||
911 | #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_ID 0x8E | ||
912 | #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_CONTEXT 0x8F | ||
913 | #define I2O_FSC_TRANSPORT_UNKNOWN_FAILURE 0xFF | ||
914 | |||
915 | /* Device Claim Types */ | ||
916 | #define I2O_CLAIM_PRIMARY 0x01000000 | ||
917 | #define I2O_CLAIM_MANAGEMENT 0x02000000 | ||
918 | #define I2O_CLAIM_AUTHORIZED 0x03000000 | ||
919 | #define I2O_CLAIM_SECONDARY 0x04000000 | ||
920 | |||
921 | /* Message header defines for VersionOffset */ | ||
922 | #define I2OVER15 0x0001 | ||
923 | #define I2OVER20 0x0002 | ||
924 | |||
925 | /* Default is 1.5, FIXME: Need support for both 1.5 and 2.0 */ | ||
926 | #define I2OVERSION I2OVER15 | ||
927 | |||
928 | #define SGL_OFFSET_0 I2OVERSION | ||
929 | #define SGL_OFFSET_4 (0x0040 | I2OVERSION) | ||
930 | #define SGL_OFFSET_5 (0x0050 | I2OVERSION) | ||
931 | #define SGL_OFFSET_6 (0x0060 | I2OVERSION) | ||
932 | #define SGL_OFFSET_7 (0x0070 | I2OVERSION) | ||
933 | #define SGL_OFFSET_8 (0x0080 | I2OVERSION) | ||
934 | #define SGL_OFFSET_9 (0x0090 | I2OVERSION) | ||
935 | #define SGL_OFFSET_10 (0x00A0 | I2OVERSION) | ||
936 | |||
937 | #define TRL_OFFSET_5 (0x0050 | I2OVERSION) | ||
938 | #define TRL_OFFSET_6 (0x0060 | I2OVERSION) | ||
939 | |||
940 | /* Transaction Reply Lists (TRL) Control Word structure */ | ||
941 | #define TRL_SINGLE_FIXED_LENGTH 0x00 | ||
942 | #define TRL_SINGLE_VARIABLE_LENGTH 0x40 | ||
943 | #define TRL_MULTIPLE_FIXED_LENGTH 0x80 | ||
944 | |||
945 | /* msg header defines for MsgFlags */ | ||
946 | #define MSG_STATIC 0x0100 | ||
947 | #define MSG_64BIT_CNTXT 0x0200 | ||
948 | #define MSG_MULTI_TRANS 0x1000 | ||
949 | #define MSG_FAIL 0x2000 | ||
950 | #define MSG_FINAL 0x4000 | ||
951 | #define MSG_REPLY 0x8000 | ||
952 | |||
953 | /* minimum size msg */ | ||
954 | #define THREE_WORD_MSG_SIZE 0x00030000 | ||
955 | #define FOUR_WORD_MSG_SIZE 0x00040000 | ||
956 | #define FIVE_WORD_MSG_SIZE 0x00050000 | ||
957 | #define SIX_WORD_MSG_SIZE 0x00060000 | ||
958 | #define SEVEN_WORD_MSG_SIZE 0x00070000 | ||
959 | #define EIGHT_WORD_MSG_SIZE 0x00080000 | ||
960 | #define NINE_WORD_MSG_SIZE 0x00090000 | ||
961 | #define TEN_WORD_MSG_SIZE 0x000A0000 | ||
962 | #define ELEVEN_WORD_MSG_SIZE 0x000B0000 | ||
963 | #define I2O_MESSAGE_SIZE(x) ((x)<<16) | ||
964 | |||
965 | /* Special TID Assignments */ | ||
966 | |||
967 | #define ADAPTER_TID 0 | ||
968 | #define HOST_TID 1 | ||
969 | |||
970 | #define MSG_FRAME_SIZE 128 /* i2o_scsi assumes >= 32 */ | ||
971 | #define REPLY_FRAME_SIZE 17 | ||
972 | #define SG_TABLESIZE 30 | ||
973 | #define NMBR_MSG_FRAMES 128 | ||
974 | |||
975 | #define MSG_POOL_SIZE (MSG_FRAME_SIZE*NMBR_MSG_FRAMES*sizeof(u32)) | ||
976 | |||
977 | #define I2O_POST_WAIT_OK 0 | ||
978 | #define I2O_POST_WAIT_TIMEOUT -ETIMEDOUT | ||
979 | |||
980 | #define I2O_CONTEXT_LIST_MIN_LENGTH 15 | ||
981 | #define I2O_CONTEXT_LIST_USED 0x01 | ||
982 | #define I2O_CONTEXT_LIST_DELETED 0x02 | ||
983 | |||
984 | /* timeouts */ | ||
985 | #define I2O_TIMEOUT_INIT_OUTBOUND_QUEUE 15 | ||
986 | #define I2O_TIMEOUT_MESSAGE_GET 5 | ||
987 | #define I2O_TIMEOUT_RESET 30 | ||
988 | #define I2O_TIMEOUT_STATUS_GET 5 | ||
989 | #define I2O_TIMEOUT_LCT_GET 360 | ||
990 | #define I2O_TIMEOUT_SCSI_SCB_ABORT 240 | ||
991 | |||
992 | /* retries */ | ||
993 | #define I2O_HRT_GET_TRIES 3 | ||
994 | #define I2O_LCT_GET_TRIES 3 | ||
995 | |||
996 | /* request queue sizes */ | ||
997 | #define I2O_MAX_SECTORS 1024 | ||
998 | #define I2O_MAX_SEGMENTS 128 | ||
999 | |||
1000 | #define I2O_REQ_MEMPOOL_SIZE 32 | ||
1001 | |||
1002 | #endif /* __KERNEL__ */ | ||
1003 | #endif /* _I2O_H */ | ||