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authorGreg Kroah-Hartman <gregkh@suse.de>2009-06-03 10:45:49 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2009-06-19 14:00:56 -0400
commit482612afc611a504ef7f0e51022d381876ee3cca (patch)
tree2556b161c753abf3d31d4ee8b2e01d7710672352 /drivers/staging
parentb079fa27d946cf7382ebcd06148782d62103e51a (diff)
Staging: pata_rdc: coding style fixes
This fixes a number of coding style issues in the pata_rdc.h file Cc: Kevin Huang <Kevin.Huang@rdc.com.tw> Cc: Tomy Wang <Tomy.Wang@rdc.com.tw> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging')
-rw-r--r--drivers/staging/pata_rdc/pata_rdc.c2061
-rw-r--r--drivers/staging/pata_rdc/pata_rdc.h363
2 files changed, 1012 insertions, 1412 deletions
diff --git a/drivers/staging/pata_rdc/pata_rdc.c b/drivers/staging/pata_rdc/pata_rdc.c
index 5bc74ed0532..5d52373eeec 100644
--- a/drivers/staging/pata_rdc/pata_rdc.c
+++ b/drivers/staging/pata_rdc/pata_rdc.c
@@ -10,7 +10,7 @@
10 10
11#include "pata_rdc.h" 11#include "pata_rdc.h"
12 12
13//#define DBGPRINTF 13/* #define DBGPRINTF */
14 14
15#ifdef DBGPRINTF 15#ifdef DBGPRINTF
16 16
@@ -22,113 +22,111 @@
22 22
23#endif 23#endif
24 24
25// Driver Info. 25/* Driver Info. */
26 26#define DRIVER_NAME "pata_rdc" /* sata_rdc for SATA */
27#define DRIVER_NAME "pata_rdc" // sata_rdc for SATA 27#define DRIVER_VERSION "2.6.28" /* based on kernel version. */
28#define DRIVER_VERSION "2.6.28" // based on kernel version. 28 /* because each kernel main version has
29 // because each kernel main version has its libata, we follow kernel to determine the last libata version. 29 * its libata, we follow kernel to
30 * determine the last libata version.
31 */
30 32
31 33
32static const struct pci_device_id rdc_pata_id_table[] = { 34static const struct pci_device_id rdc_pata_id_table[] = {
33 { 0x17F3, 0x1011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RDC_17F31011}, 35 { 0x17F3, 0x1011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RDC_17F31011},
34 { 0x17F3, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RDC_17F31012}, 36 { 0x17F3, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RDC_17F31012},
35 { } /* terminate list */ 37 { } /* terminate list */
36}; 38};
37 39
38MODULE_LICENSE("GPL"); 40MODULE_LICENSE("GPL");
39MODULE_AUTHOR("this version author is RDC"); // replace "RDC" with the last maintainer. 41MODULE_AUTHOR("this version author is RDC"); /* replace "RDC" with the last maintainer. */
40MODULE_DESCRIPTION("RDC PCI IDE Driver"); 42MODULE_DESCRIPTION("RDC PCI IDE Driver");
41MODULE_DEVICE_TABLE(pci, rdc_pata_id_table); 43MODULE_DEVICE_TABLE(pci, rdc_pata_id_table);
42MODULE_VERSION(DRIVER_VERSION); 44MODULE_VERSION(DRIVER_VERSION);
43 45
44// a pci driver 46/* a pci driver */
45static struct pci_driver rdc_pata_driver = { 47static struct pci_driver rdc_pata_driver = {
46 .name = DRIVER_NAME, 48 .name = DRIVER_NAME,
47 .id_table = rdc_pata_id_table, 49 .id_table = rdc_pata_id_table,
48 .probe = rdc_init_one, 50 .probe = rdc_init_one,
49 .remove = ata_pci_remove_one, 51 .remove = ata_pci_remove_one,
50#ifdef CONFIG_PM 52#ifdef CONFIG_PM
51 .suspend = ata_pci_device_suspend, 53 .suspend = ata_pci_device_suspend,
52 .resume = ata_pci_device_resume, 54 .resume = ata_pci_device_resume,
53#endif 55#endif
54}; 56};
55 57
56static unsigned int in_module_init = 1; // hotplugging check??? 58static unsigned int in_module_init = 1; /* hotplugging check??? */
57static int __init pata_rdc_init(void) 59static int __init pata_rdc_init(void)
58{ 60{
59 int rc; 61 int rc;
60 62
61 dbgprintf("pata_rdc_init\n"); 63 dbgprintf("pata_rdc_init\n");
62 rc = pci_register_driver(&rdc_pata_driver); 64 rc = pci_register_driver(&rdc_pata_driver);
63 if (rc) 65 if (rc) {
64 { 66 dbgprintf("pata_rdc_init faile\n");
65 dbgprintf("pata_rdc_init faile\n"); 67 return rc;
66 return rc; 68 }
67 }
68 69
69 in_module_init = 0; 70 in_module_init = 0;
70 71
71 return 0; 72 return 0;
72} 73}
73 74
74static void __exit pata_rdc_exit(void) 75static void __exit pata_rdc_exit(void)
75{ 76{
76 dbgprintf("pata_rdc_exit\n"); 77 dbgprintf("pata_rdc_exit\n");
77 pci_unregister_driver(&rdc_pata_driver); 78 pci_unregister_driver(&rdc_pata_driver);
78} 79}
79 80
80module_init(pata_rdc_init); 81module_init(pata_rdc_init);
81module_exit(pata_rdc_exit); 82module_exit(pata_rdc_exit);
82 83
83// ata device data 84/* ata device data */
84 85
85static struct pci_bits ATA_Decode_Enable_Bits[] = { // see ATA Host Adapters Standards. 86/* see ATA Host Adapters Standards. */
86 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port (Channel) 0 */ 87static struct pci_bits ATA_Decode_Enable_Bits[] = {
87 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port (Channel) 1 */ 88 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port (Channel) 0 */
89 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port (Channel) 1 */
88}; 90};
89 91
90static struct scsi_host_template rdc_pata_sht = { // pata host template 92/* pata host template */
91 ATA_BMDMA_SHT(DRIVER_NAME), 93static struct scsi_host_template rdc_pata_sht = {
94 ATA_BMDMA_SHT(DRIVER_NAME),
92}; 95};
93 96
94static const struct ata_port_operations rdc_pata_ops = { 97static const struct ata_port_operations rdc_pata_ops = {
95 .inherits = &ata_bmdma_port_ops, 98 .inherits = &ata_bmdma_port_ops,
96 99
97 .port_start = rdc_pata_port_start, 100 .port_start = rdc_pata_port_start,
98 .port_stop = rdc_pata_port_stop, 101 .port_stop = rdc_pata_port_stop,
99 .prereset = rdc_pata_prereset, 102 .prereset = rdc_pata_prereset,
100 .cable_detect = rdc_pata_cable_detect, 103 .cable_detect = rdc_pata_cable_detect,
101 .set_piomode = rdc_pata_set_piomode, 104 .set_piomode = rdc_pata_set_piomode,
102 .set_dmamode = rdc_pata_set_dmamode, 105 .set_dmamode = rdc_pata_set_dmamode,
103
104}; 106};
105 107
106static struct ata_port_info rdc_pata_port_info[] = { 108static struct ata_port_info rdc_pata_port_info[] = {
107 [RDC_17F31011] = 109 [RDC_17F31011] = {
108 { 110 .flags = ATA_FLAG_SLAVE_POSS,
109 .flags = ATA_FLAG_SLAVE_POSS, 111 .pio_mask = 0x1f, /* pio0-4 */
110 .pio_mask = 0x1f, /* pio0-4 */ 112 .mwdma_mask = 0x07, /* mwdma0-2 */
111 .mwdma_mask = 0x07, /* mwdma0-2 */ 113 .udma_mask = ATA_UDMA5, /* udma0-5 */
112 .udma_mask = ATA_UDMA5, /* udma0-5 */ 114 .port_ops = &rdc_pata_ops,
113 .port_ops = &rdc_pata_ops, 115 },
114 }, 116
115 117 [RDC_17F31012] = {
116 [RDC_17F31012] = 118 .flags = ATA_FLAG_SLAVE_POSS,
117 { 119 .pio_mask = 0x1f, /* pio0-4 */
118 .flags = ATA_FLAG_SLAVE_POSS, 120 .mwdma_mask = 0x07, /* mwdma0-2 */
119 .pio_mask = 0x1f, /* pio0-4 */ 121 .udma_mask = ATA_UDMA5, /* udma0-5 */
120 .mwdma_mask = 0x07, /* mwdma0-2 */ 122 .port_ops = &rdc_pata_ops,
121 .udma_mask = ATA_UDMA5, /* udma0-5 */ 123 },
122 .port_ops = &rdc_pata_ops,
123 },
124
125
126}; 124};
127 125
128 126
129 127
130 128
131// callback function for pci_driver 129/* callback function for pci_driver */
132 130
133/** 131/**
134 * Register ATA PCI device with kernel services 132 * Register ATA PCI device with kernel services
@@ -141,43 +139,39 @@ static struct ata_port_info rdc_pata_port_info[] = {
141 * RETURNS: 139 * RETURNS:
142 * Zero on success, or -ERRNO value. 140 * Zero on success, or -ERRNO value.
143 */ 141 */
144static int __devinit rdc_init_one( 142static int __devinit rdc_init_one(struct pci_dev *pdev,
145 struct pci_dev *pdev, 143 const struct pci_device_id *ent)
146 const struct pci_device_id *ent
147 )
148{ 144{
149 //struct device *dev = &pdev->dev; 145 /*struct device *dev = &pdev->dev; */
150 struct ata_port_info port_info[2]; 146 struct ata_port_info port_info[2];
151 const struct ata_port_info *ppinfo[] = { &port_info[0], &port_info[1] }; 147 const struct ata_port_info *ppinfo[] = { &port_info[0], &port_info[1] };
152 148
153 int rc; 149 int rc;
154 150
155 dbgprintf("rdc_init_one\n"); 151 dbgprintf("rdc_init_one\n");
156 152
157 /* no hotplugging support (FIXME) */ // why??? 153 /* no hotplugging support (FIXME) */ /* why??? */
158 if (!in_module_init) 154 if (!in_module_init) {
159 { 155 dbgprintf("rdc_init_one in_module_init == 0 failed \n");
160 dbgprintf("rdc_init_one in_module_init == 0 failed \n"); 156 return -ENODEV;
161 return -ENODEV; 157 }
162 } 158 port_info[0] = rdc_pata_port_info[ent->driver_data];
163 port_info[0] = rdc_pata_port_info[ent->driver_data]; 159 port_info[1] = rdc_pata_port_info[ent->driver_data];
164 port_info[1] = rdc_pata_port_info[ent->driver_data]; 160
165 161 /* enable device and prepare host */
166 /* enable device and prepare host */ 162 rc = pci_enable_device(pdev);
167 rc = pci_enable_device(pdev); 163 if (rc) {
168 if (rc) 164 dbgprintf("rdc_init_one pci_enable_device failed \n");
169 { 165 return rc;
170 dbgprintf("rdc_init_one pci_enable_device failed \n"); 166 }
171 return rc; 167 /* initialize controller */
172 } 168
173 /* initialize controller */ 169 pci_intx(pdev, 1); /* enable interrupt */
174 170
175 pci_intx(pdev, 1); // enable interrupt 171 return ata_pci_sff_init_one(pdev, ppinfo, &rdc_pata_sht, NULL);
176
177 return ata_pci_sff_init_one(pdev, ppinfo, &rdc_pata_sht, NULL);
178} 172}
179 173
180// callback function for ata_port 174/* callback function for ata_port */
181 175
182/** 176/**
183 * Set port up for dma. 177 * Set port up for dma.
@@ -196,34 +190,27 @@ static int __devinit rdc_init_one(
196 * LOCKING: 190 * LOCKING:
197 * Inherited from caller. 191 * Inherited from caller.
198 */ 192 */
199static int rdc_pata_port_start( 193static int rdc_pata_port_start(struct ata_port *ap)
200 struct ata_port *ap
201 )
202{ 194{
203 uint Channel; 195 uint Channel;
204 196
205 Channel = ap->port_no; 197 Channel = ap->port_no;
206 dbgprintf("rdc_pata_port_start Channel: %u \n", Channel); 198 dbgprintf("rdc_pata_port_start Channel: %u \n", Channel);
207 if (ap->ioaddr.bmdma_addr) 199 if (ap->ioaddr.bmdma_addr) {
208 { 200 return ata_port_start(ap);
209 return ata_port_start(ap); 201 } else {
210 } 202 dbgprintf("rdc_pata_port_start return 0 !!!\n");
211 else 203 return 0;
212 { 204 }
213 dbgprintf("rdc_pata_port_start return 0 !!!\n");
214 return 0;
215 }
216} 205}
217 206
218static void rdc_pata_port_stop( 207static void rdc_pata_port_stop(struct ata_port *ap)
219 struct ata_port *ap
220 )
221{ 208{
222 uint Channel; 209 uint Channel;
223 210
224 Channel = ap->port_no; 211 Channel = ap->port_no;
225 212
226 dbgprintf("rdc_pata_port_stop Channel: %u \n", Channel); 213 dbgprintf("rdc_pata_port_stop Channel: %u \n", Channel);
227} 214}
228 215
229/** 216/**
@@ -234,34 +221,27 @@ static void rdc_pata_port_stop(
234 * LOCKING: 221 * LOCKING:
235 * None (inherited from caller). 222 * None (inherited from caller).
236 */ 223 */
237static int rdc_pata_prereset( 224static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline)
238 struct ata_link *link,
239 unsigned long deadline
240 )
241{ 225{
242 struct pci_dev *pdev; 226 struct pci_dev *pdev;
243 struct ata_port *ap; 227 struct ata_port *ap;
244 228 uint Channel;
245 uint Channel;
246 229
247 dbgprintf("rdc_pata_prereset\n"); 230 dbgprintf("rdc_pata_prereset\n");
248 231
249 ap = link->ap; 232 ap = link->ap;
250 pdev = to_pci_dev(ap->host->dev); 233 pdev = to_pci_dev(ap->host->dev);
251 234
252 Channel = ap->port_no; 235 Channel = ap->port_no;
253 236
254 // test ATA Decode Enable Bits, should be enable. 237 /* test ATA Decode Enable Bits, should be enable. */
255 if (!pci_test_config_bits(pdev, &ATA_Decode_Enable_Bits[Channel])) 238 if (!pci_test_config_bits(pdev, &ATA_Decode_Enable_Bits[Channel])) {
256 { 239 dbgprintf("rdc_pata_prereset Channel: %u, Decode Disable\n", Channel);
257 dbgprintf("rdc_pata_prereset Channel: %u, Decode Disable\n", Channel); 240 return -ENOENT;
258 return -ENOENT; 241 } else {
259 } 242 dbgprintf("rdc_pata_prereset Channel: %u, Decode Enable\n", Channel);
260 else 243 return ata_std_prereset(link, deadline);
261 { 244 }
262 dbgprintf("rdc_pata_prereset Channel: %u, Decode Enable\n", Channel);
263 return ata_std_prereset(link, deadline);
264 }
265} 245}
266 246
267/** 247/**
@@ -274,46 +254,34 @@ static int rdc_pata_prereset(
274 * LOCKING: 254 * LOCKING:
275 * None (inherited from caller). 255 * None (inherited from caller).
276 */ 256 */
277 257static int rdc_pata_cable_detect(struct ata_port *ap)
278static int rdc_pata_cable_detect(
279 struct ata_port *ap
280 )
281{ 258{
282 struct pci_dev *pdev; 259 struct pci_dev *pdev;
260 uint Channel;
261 uint Mask;
262 u32 u32Value;
283 263
284 uint Channel; 264 dbgprintf("rdc_pata_cable_detect\n");
285 265
286 uint Mask; 266 pdev = to_pci_dev(ap->host->dev);
287 u32 u32Value;
288 267
289 dbgprintf("rdc_pata_cable_detect\n"); 268 Channel = ap->port_no;
290 269
291 pdev = to_pci_dev(ap->host->dev); 270 if (Channel == 0)
271 Mask = ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report;
272 else
273 Mask = ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report;
292 274
293 Channel = ap->port_no; 275 /* check BIOS cable detect results */
276 pci_read_config_dword(pdev, ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, &u32Value);
294 277
295 if (Channel == 0) 278 if ((u32Value & Mask) == 0) {
296 { 279 dbgprintf("rdc_pata_cable_detect Channel: %u, PATA40 \n", Channel);
297 Mask = ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report; 280 return ATA_CBL_PATA40;
298 } 281 } else {
299 else 282 dbgprintf("rdc_pata_cable_detect Channel: %u, PATA80 \n", Channel);
300 { 283 return ATA_CBL_PATA80;
301 Mask = ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report; 284 }
302 }
303
304 /* check BIOS cable detect results */
305 pci_read_config_dword(pdev, ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, &u32Value);
306
307 if ((u32Value & Mask) == 0)
308 {
309 dbgprintf("rdc_pata_cable_detect Channel: %u, PATA40 \n", Channel);
310 return ATA_CBL_PATA40;
311 }
312 else
313 {
314 dbgprintf("rdc_pata_cable_detect Channel: %u, PATA80 \n", Channel);
315 return ATA_CBL_PATA80;
316 }
317} 285}
318 286
319/** 287/**
@@ -326,80 +294,73 @@ static int rdc_pata_cable_detect(
326 * LOCKING: 294 * LOCKING:
327 * None (inherited from caller). 295 * None (inherited from caller).
328 */ 296 */
329 297static void rdc_pata_set_piomode(struct ata_port *ap, struct ata_device *adev)
330static void rdc_pata_set_piomode(
331 struct ata_port *ap,
332 struct ata_device *adev
333 )
334{ 298{
335 struct pci_dev *pdev; 299 struct pci_dev *pdev;
336 300 uint Channel;
337 uint Channel; 301 uint DeviceID;
338 uint DeviceID; 302 uint PIOTimingMode;
339 303 uint PrefetchPostingEnable;
340 uint PIOTimingMode; 304
341 uint PrefetchPostingEnable; 305 dbgprintf("rdc_pata_set_piomode\n");
342 306
343 dbgprintf("rdc_pata_set_piomode\n"); 307 pdev = to_pci_dev(ap->host->dev);
344 308
345 pdev = to_pci_dev(ap->host->dev); 309 Channel = ap->port_no;
346 310 DeviceID = adev->devno;
347 Channel = ap->port_no; 311 /*
348 DeviceID = adev->devno; 312 * piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1,
349 PIOTimingMode = adev->pio_mode - XFER_PIO_0; // piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3... 313 * XFER_PIO_2, XFER_PIO_3...
350 314 */
351 if (adev->class == ATA_DEV_ATA) 315 PIOTimingMode = adev->pio_mode - XFER_PIO_0;
352 { 316
353 PrefetchPostingEnable = TRUE; 317 if (adev->class == ATA_DEV_ATA) {
354 } 318 PrefetchPostingEnable = TRUE;
355 else 319 } else {
356 { // ATAPI, CD DVD Rom 320 /* ATAPI, CD DVD Rom */
357 PrefetchPostingEnable = FALSE; 321 PrefetchPostingEnable = FALSE;
358 } 322 }
359 323
360 /* PIO configuration clears DTE unconditionally. It will be 324 /* PIO configuration clears DTE unconditionally. It will be
361 * programmed in set_dmamode which is guaranteed to be called 325 * programmed in set_dmamode which is guaranteed to be called
362 * after set_piomode if any DMA mode is available. 326 * after set_piomode if any DMA mode is available.
363 */ 327 */
364 328
365 /* Ensure the UDMA bit is off - it will be turned back on if 329 /* Ensure the UDMA bit is off - it will be turned back on if UDMA is
366 UDMA is selected */ 330 * selected */
367 331
368 if (Channel == 0) 332 if (Channel == 0) {
369 { 333 ATAHostAdapter_SetPrimaryPIO(
370 ATAHostAdapter_SetPrimaryPIO( 334 pdev,
371 pdev, 335 DeviceID,
372 DeviceID, 336 PIOTimingMode,
373 PIOTimingMode, 337 TRUE,/* DMAEnable, */
374 TRUE,//DMAEnable, 338 PrefetchPostingEnable
375 PrefetchPostingEnable 339 );
376 ); 340
377 341 ATAHostAdapter_SetPrimaryUDMA(
378 ATAHostAdapter_SetPrimaryUDMA( 342 pdev,
379 pdev, 343 DeviceID,
380 DeviceID, 344 FALSE,/* UDMAEnable, */
381 FALSE,//UDMAEnable, 345 UDMA0
382 UDMA0 346 );
383 ); 347 } else {
384 } 348 ATAHostAdapter_SetSecondaryPIO(
385 else 349 pdev,
386 { 350 DeviceID,
387 ATAHostAdapter_SetSecondaryPIO( 351 PIOTimingMode,
388 pdev, 352 TRUE,/* DMAEnable, */
389 DeviceID, 353 PrefetchPostingEnable
390 PIOTimingMode, 354 );
391 TRUE,//DMAEnable, 355
392 PrefetchPostingEnable 356 ATAHostAdapter_SetSecondaryUDMA(
393 ); 357 pdev,
394 358 DeviceID,
395 ATAHostAdapter_SetSecondaryUDMA( 359 FALSE,/* UDMAEnable, */
396 pdev, 360 UDMA0
397 DeviceID, 361 );
398 FALSE,//UDMAEnable, 362 }
399 UDMA0 363 dbgprintf("rdc_pata_set_piomode Channel: %u, DeviceID: %u, PIO: %d \n", Channel, DeviceID, PIOTimingMode);
400 );
401 }
402 dbgprintf("rdc_pata_set_piomode Channel: %u, DeviceID: %u, PIO: %d \n", Channel, DeviceID, PIOTimingMode);
403} 364}
404 365
405/** 366/**
@@ -412,992 +373,694 @@ static void rdc_pata_set_piomode(
412 * LOCKING: 373 * LOCKING:
413 * None (inherited from caller). 374 * None (inherited from caller).
414 */ 375 */
415 376static void rdc_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev)
416static void rdc_pata_set_dmamode(
417 struct ata_port *ap,
418 struct ata_device *adev
419 )
420{ 377{
421 struct pci_dev *pdev; 378 struct pci_dev *pdev;
422 379 uint Channel;
423 uint Channel; 380 uint DeviceID;
424 uint DeviceID; 381 uint PIOTimingMode;
425 382 uint PrefetchPostingEnable;
426 uint PIOTimingMode; 383 uint DMATimingMode;
427 uint PrefetchPostingEnable; 384 uint UDMAEnable;
428 uint DMATimingMode; 385
429 uint UDMAEnable; 386 dbgprintf("rdc_pata_set_dmamode\n");
430 387
431 dbgprintf("rdc_pata_set_dmamode\n"); 388 pdev = to_pci_dev(ap->host->dev);
432 389
433 pdev = to_pci_dev(ap->host->dev); 390 Channel = ap->port_no;
434 391 DeviceID = adev->devno;
435 Channel = ap->port_no; 392 PIOTimingMode = adev->pio_mode - XFER_PIO_0; /* piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3... */
436 DeviceID = adev->devno; 393 DMATimingMode = adev->dma_mode; /* UDMA or MDMA */
437 PIOTimingMode = adev->pio_mode - XFER_PIO_0; // piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3... 394
438 DMATimingMode = adev->dma_mode; // UDMA or MDMA 395 if (adev->class == ATA_DEV_ATA) {
439 396 PrefetchPostingEnable = TRUE;
440 if (adev->class == ATA_DEV_ATA) 397 } else {
441 { 398 /* ATAPI, CD DVD Rom */
442 PrefetchPostingEnable = TRUE; 399 PrefetchPostingEnable = FALSE;
443 } 400 }
444 else 401
445 { // ATAPI, CD DVD Rom 402 if (ap->udma_mask == 0) {
446 PrefetchPostingEnable = FALSE; 403 /* ata_port dont support udma. depend on hardware spec. */
447 } 404 UDMAEnable = FALSE;
448 405 } else {
449 if (ap->udma_mask == 0) 406 UDMAEnable = TRUE;
450 { // ata_port dont support udma. depend on hardware spec. 407 }
451 UDMAEnable = FALSE; 408
452 } 409 /*if (ap->mdma_mask == 0) {
453 else 410 }*/
454 { 411
455 UDMAEnable = TRUE; 412 if (Channel == 0) {
456 } 413 if (DMATimingMode >= XFER_UDMA_0) {
457 414 /* UDMA */
458 /*if (ap->mdma_mask == 0) 415 ATAHostAdapter_SetPrimaryPIO(pdev,
459 { 416 DeviceID,
460 }*/ 417 PIOTimingMode,
461 418 TRUE,/*DMAEnable,*/
462 if (Channel == 0) 419 PrefetchPostingEnable);
463 { 420
464 if (DMATimingMode >= XFER_UDMA_0) 421 ATAHostAdapter_SetPrimaryUDMA(pdev,
465 { // UDMA 422 DeviceID,
466 ATAHostAdapter_SetPrimaryPIO( 423 UDMAEnable,
467 pdev, 424 DMATimingMode - XFER_UDMA_0);
468 DeviceID, 425 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0));
469 PIOTimingMode, 426 } else {
470 TRUE,//DMAEnable, 427 /* MDMA */
471 PrefetchPostingEnable 428 ATAHostAdapter_SetPrimaryPIO(pdev,
472 ); 429 DeviceID,
473 430 (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */
474 ATAHostAdapter_SetPrimaryUDMA( 431 TRUE,/*DMAEnable,*/
475 pdev, 432 PrefetchPostingEnable);
476 DeviceID, 433
477 UDMAEnable, 434 ATAHostAdapter_SetPrimaryUDMA(pdev,
478 DMATimingMode - XFER_UDMA_0 435 DeviceID,
479 ); 436 FALSE,/*UDMAEnable,*/
480 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0)); 437 UDMA0);
481 } 438 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0));
482 else 439 }
483 { // MDMA 440 } else {
484 ATAHostAdapter_SetPrimaryPIO( 441 if (DMATimingMode >= XFER_UDMA_0) {
485 pdev, 442 /* UDMA */
486 DeviceID, 443 ATAHostAdapter_SetSecondaryPIO(pdev,
487 (DMATimingMode - XFER_MW_DMA_0) + PIO2, // MDMA0 = PIO2 444 DeviceID,
488 TRUE,//DMAEnable, 445 PIOTimingMode,
489 PrefetchPostingEnable 446 TRUE,/*DMAEnable,*/
490 ); 447 PrefetchPostingEnable);
491 448
492 ATAHostAdapter_SetPrimaryUDMA( 449 ATAHostAdapter_SetSecondaryUDMA(pdev,
493 pdev, 450 DeviceID,
494 DeviceID, 451 UDMAEnable,
495 FALSE,//UDMAEnable, 452 DMATimingMode - XFER_UDMA_0);
496 UDMA0 453 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0));
497 ); 454 } else {
498 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0)); 455 /* MDMA */
499 } 456 ATAHostAdapter_SetSecondaryPIO(pdev,
500 } 457 DeviceID,
501 else 458 (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */
502 { 459 TRUE,/*DMAEnable,*/
503 if (DMATimingMode >= XFER_UDMA_0) 460 PrefetchPostingEnable);
504 { // UDMA 461
505 ATAHostAdapter_SetSecondaryPIO( 462 ATAHostAdapter_SetSecondaryUDMA(pdev,
506 pdev, 463 DeviceID,
507 DeviceID, 464 FALSE,/*UDMAEnable,*/
508 PIOTimingMode, 465 UDMA0);
509 TRUE,//DMAEnable, 466 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0));
510 PrefetchPostingEnable 467 }
511 ); 468 }
512
513 ATAHostAdapter_SetSecondaryUDMA(
514 pdev,
515 DeviceID,
516 UDMAEnable,
517 DMATimingMode - XFER_UDMA_0
518 );
519 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0));
520 }
521 else
522 { // MDMA
523 ATAHostAdapter_SetSecondaryPIO(
524 pdev,
525 DeviceID,
526 (DMATimingMode - XFER_MW_DMA_0) + PIO2, // MDMA0 = PIO2
527 TRUE,//DMAEnable,
528 PrefetchPostingEnable
529 );
530
531 ATAHostAdapter_SetSecondaryUDMA(
532 pdev,
533 DeviceID,
534 FALSE,//UDMAEnable,
535 UDMA0
536 );
537 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0));
538 }
539 }
540} 469}
541 470
542// modified PCIDeviceIO code. 471/* modified PCIDeviceIO code. */
543 472
544static uint 473static uint PCIDeviceIO_ReadPCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer)
545PCIDeviceIO_ReadPCIConfiguration(
546 struct pci_dev *pdev,
547 uint Offset,
548 uint Length,
549 void* pBuffer
550 )
551{ 474{
552 uint funcresult; 475 uint funcresult;
476 unchar *pchar;
477 uint i;
553 478
554 unchar* pchar; 479 funcresult = TRUE;
555 480
556 uint i; 481 pchar = pBuffer;
557 482
558 funcresult = TRUE; 483 for (i = 0; i < Length; i++) {
484 pci_read_config_byte(pdev, Offset, pchar);
485 Offset++;
486 pchar++;
487 }
559 488
560 pchar = pBuffer; 489 funcresult = TRUE;
561 490
562 for (i = 0; i < Length; i++) 491 goto funcexit;
563 {
564 pci_read_config_byte(pdev, Offset, pchar);
565 Offset++;
566 pchar++;
567 }
568
569 funcresult = TRUE;
570
571 goto funcexit;
572funcexit: 492funcexit:
573 493
574 return funcresult; 494 return funcresult;
575} 495}
576 496
577static uint 497static uint PCIDeviceIO_WritePCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer)
578PCIDeviceIO_WritePCIConfiguration(
579 struct pci_dev *pdev,
580 uint Offset,
581 uint Length,
582 void* pBuffer
583 )
584{ 498{
585 uint funcresult; 499 uint funcresult;
586 500 unchar *pchar;
587 unchar* pchar; 501 uint i;
588 502
589 uint i; 503 funcresult = TRUE;
590 504
591 funcresult = TRUE; 505 pchar = pBuffer;
592 506
593 pchar = pBuffer; 507 for (i = 0; i < Length; i++) {
508 pci_write_config_byte(pdev, Offset, *pchar);
509 Offset++;
510 pchar++;
511 }
594 512
595 for (i = 0; i < Length; i++) 513 funcresult = TRUE;
596 {
597 pci_write_config_byte(pdev, Offset, *pchar);
598 Offset++;
599 pchar++;
600 }
601 514
602 funcresult = TRUE; 515 goto funcexit;
603
604 goto funcexit;
605funcexit: 516funcexit:
606 517
607 return funcresult; 518 return funcresult;
608} 519}
609 520
610 521/* modified ATAHostAdapter code. */
611// modified ATAHostAdapter code. 522static uint ATAHostAdapter_SetPrimaryPIO(struct pci_dev *pdev, uint DeviceID,
612 523 uint PIOTimingMode, uint DMAEnable,
613static uint 524 uint PrefetchPostingEnable)
614ATAHostAdapter_SetPrimaryPIO(
615 struct pci_dev *pdev,
616 uint DeviceID,
617 uint PIOTimingMode,
618 uint DMAEnable,
619 uint PrefetchPostingEnable
620 )
621{ 525{
622 uint funcresult; 526 uint funcresult;
623 527 uint result;
624 uint result; 528 uint ATATimingRegister;
625 529 uint Device1TimingRegister;
626 uint ATATimingRegister; 530
627 uint Device1TimingRegister; 531 funcresult = TRUE;
628 532
629 funcresult = TRUE; 533 ATATimingRegister = 0;
630 534 Device1TimingRegister = 0;
631 ATATimingRegister = 0; 535
632 Device1TimingRegister = 0; 536 result = PCIDeviceIO_ReadPCIConfiguration(pdev,
633 537 ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset,
634 result = PCIDeviceIO_ReadPCIConfiguration( 538 ATAConfiguration_ID_PrimaryTiming_Size,
635 pdev, 539 &ATATimingRegister);
636 ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset, 540 if (result == FALSE) {
637 ATAConfiguration_ID_PrimaryTiming_Size, 541 funcresult = FALSE;
638 &ATATimingRegister 542 goto funcexit;
639 ); 543 }
640 if (result == FALSE) 544
641 { 545 result = PCIDeviceIO_ReadPCIConfiguration(pdev,
642 funcresult = FALSE; 546 ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
643 goto funcexit; 547 ATAConfiguration_ID_Device1Timing_Size,
644 } 548 &Device1TimingRegister);
645 549 if (result == FALSE) {
646 result = PCIDeviceIO_ReadPCIConfiguration( 550 funcresult = FALSE;
647 pdev, 551 goto funcexit;
648 ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset, 552 }
649 ATAConfiguration_ID_Device1Timing_Size, 553
650 &Device1TimingRegister 554 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable;
651 ); 555
652 if (result == FALSE) 556 switch (DeviceID) {
653 { 557 case 0:
654 funcresult = FALSE; 558 /* mask clear */
655 goto funcexit; 559 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable |
656 } 560 ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable |
657 561 ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable |
658 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable; 562 ATAConfiguration_PrimaryTiming_Device0DMATimingEnable |
659 563 ATAConfiguration_PrimaryTiming_Device0RecoveryMode |
660 switch(DeviceID) 564 ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode);
661 { 565
662 case 0: 566 if (PIOTimingMode > PIO0)
663 { 567 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable;
664 // mask clear 568
665 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable 569 if (PIOTimingMode >= PIO3)
666 | ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable 570 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable;
667 | ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable 571
668 | ATAConfiguration_PrimaryTiming_Device0DMATimingEnable 572 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
669 | ATAConfiguration_PrimaryTiming_Device0RecoveryMode 573 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable;
670 | ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode 574
671 ); 575 if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
672 576 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable;
673 if (PIOTimingMode > PIO0) 577
674 { 578 if (PIOTimingMode <= PIO2)
675 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable; 579 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0;
676 } 580 else if (PIOTimingMode == PIO3)
677 581 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1;
678 if (PIOTimingMode >= PIO3) 582 else if (PIOTimingMode == PIO4)
679 { 583 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3;
680 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable; 584
681 } 585 if (PIOTimingMode <= PIO1)
682 586 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0;
683 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) 587 else if (PIOTimingMode == PIO2)
684 { 588 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1;
685 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable; 589 else if (PIOTimingMode <= PIO4)
686 } 590 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2;
687 591 break;
688 if (DMAEnable == TRUE 592 case 1:
689 && PIOTimingMode >= PIO2) 593 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable |
690 { 594 ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable |
691 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable; 595 ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable |
692 } 596 ATAConfiguration_PrimaryTiming_Device1DMATimingEnable);
693 597
694 if (PIOTimingMode <= PIO2) 598 if (PIOTimingMode > PIO0)
695 { 599 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable;
696 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0; 600
697 } 601 if (PIOTimingMode >= PIO3)
698 else if (PIOTimingMode == PIO3) 602 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable;
699 { 603
700 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1; 604 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
701 } 605 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable;
702 else if (PIOTimingMode == PIO4) 606
703 { 607 if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
704 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3; 608 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable;
705 } 609
706 610 Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_PrimaryRecoveryMode |
707 if (PIOTimingMode <= PIO1) 611 ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode);
708 { 612
709 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0; 613 if (PIOTimingMode <= PIO2)
710 } 614 Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0;
711 else if (PIOTimingMode == PIO2) 615 else if (PIOTimingMode == PIO3)
712 { 616 Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1;
713 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1; 617 else if (PIOTimingMode == PIO4)
714 } 618 Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3;
715 else if (PIOTimingMode <= PIO4) 619
716 { 620 if (PIOTimingMode <= PIO1)
717 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2; 621 Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0;
718 } 622 else if (PIOTimingMode == PIO2)
719 } 623 Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1;
720 break; 624 else if (PIOTimingMode <= PIO4)
721 case 1: 625 Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2;
722 { 626 break;
723 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable 627 default:
724 | ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable 628 funcresult = FALSE;
725 | ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable 629 goto funcexit;
726 | ATAConfiguration_PrimaryTiming_Device1DMATimingEnable 630 break;
727 ); 631 }
728 632
729 if (PIOTimingMode > PIO0) 633 result = PCIDeviceIO_WritePCIConfiguration(pdev,
730 { 634 ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset,
731 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable; 635 ATAConfiguration_ID_PrimaryTiming_Size,
732 } 636 &ATATimingRegister);
733 637 if (result == FALSE) {
734 if (PIOTimingMode >= PIO3) 638 funcresult = FALSE;
735 { 639 goto funcexit;
736 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable; 640 }
737 } 641
738 642 result = PCIDeviceIO_WritePCIConfiguration(pdev,
739 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) 643 ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
740 { 644 ATAConfiguration_ID_Device1Timing_Size,
741 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable; 645 &Device1TimingRegister);
742 } 646 if (result == FALSE) {
743 647 funcresult = FALSE;
744 if (DMAEnable == TRUE 648 goto funcexit;
745 && PIOTimingMode >= PIO2) 649 }
746 { 650
747 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable; 651 goto funcexit;
748 }
749
750 Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_PrimaryRecoveryMode | ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode);
751
752 if (PIOTimingMode <= PIO2)
753 {
754 Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0;
755 }
756 else if (PIOTimingMode == PIO3)
757 {
758 Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1;
759 }
760 else if (PIOTimingMode == PIO4)
761 {
762 Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3;
763 }
764
765 if (PIOTimingMode <= PIO1)
766 {
767 Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0;
768 }
769 else if (PIOTimingMode == PIO2)
770 {
771 Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1;
772 }
773 else if (PIOTimingMode <= PIO4)
774 {
775 Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2;
776 }
777 }
778 break;
779 default:
780 {
781 funcresult = FALSE;
782 goto funcexit;
783 }
784 break;
785 }
786
787 result = PCIDeviceIO_WritePCIConfiguration(
788 pdev,
789 ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset,
790 ATAConfiguration_ID_PrimaryTiming_Size,
791 &ATATimingRegister
792 );
793 if (result == FALSE)
794 {
795 funcresult = FALSE;
796 goto funcexit;
797 }
798
799 result = PCIDeviceIO_WritePCIConfiguration(
800 pdev,
801 ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
802 ATAConfiguration_ID_Device1Timing_Size,
803 &Device1TimingRegister
804 );
805 if (result == FALSE)
806 {
807 funcresult = FALSE;
808 goto funcexit;
809 }
810
811 goto funcexit;
812funcexit: 652funcexit:
813 653
814 return funcresult; 654 return funcresult;
815} 655}
816 656
817static uint 657static uint ATAHostAdapter_SetSecondaryPIO(struct pci_dev *pdev, uint DeviceID,
818ATAHostAdapter_SetSecondaryPIO( 658 uint PIOTimingMode, uint DMAEnable,
819 struct pci_dev *pdev, 659 uint PrefetchPostingEnable)
820 uint DeviceID,
821 uint PIOTimingMode,
822 uint DMAEnable,
823 uint PrefetchPostingEnable
824 )
825{ 660{
826 uint funcresult; 661 uint funcresult;
827 662 uint result;
828 uint result; 663 uint ATATimingRegister;
829 664 uint Device1TimingRegister;
830 uint ATATimingRegister; 665
831 uint Device1TimingRegister; 666 funcresult = TRUE;
832 667
833 funcresult = TRUE; 668 ATATimingRegister = 0;
834 669 Device1TimingRegister = 0;
835 ATATimingRegister = 0; 670
836 Device1TimingRegister = 0; 671 result = PCIDeviceIO_ReadPCIConfiguration(pdev,
837 672 ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset,
838 result = PCIDeviceIO_ReadPCIConfiguration( 673 ATAConfiguration_ID_SecondaryTiming_Size,
839 pdev, 674 &ATATimingRegister);
840 ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset, 675 if (result == FALSE) {
841 ATAConfiguration_ID_SecondaryTiming_Size, 676 funcresult = FALSE;
842 &ATATimingRegister 677 goto funcexit;
843 ); 678 }
844 if (result == FALSE) 679
845 { 680 result = PCIDeviceIO_ReadPCIConfiguration(pdev,
846 funcresult = FALSE; 681 ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
847 goto funcexit; 682 ATAConfiguration_ID_Device1Timing_Size,
848 } 683 &Device1TimingRegister);
849 684 if (result == FALSE) {
850 result = PCIDeviceIO_ReadPCIConfiguration( 685 funcresult = FALSE;
851 pdev, 686 goto funcexit;
852 ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset, 687 }
853 ATAConfiguration_ID_Device1Timing_Size, 688
854 &Device1TimingRegister 689 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable;
855 ); 690
856 if (result == FALSE) 691 switch (DeviceID) {
857 { 692 case 0:
858 funcresult = FALSE; 693 /* mask clear */
859 goto funcexit; 694 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable |
860 } 695 ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable |
861 696 ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable |
862 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable; 697 ATAConfiguration_PrimaryTiming_Device0DMATimingEnable |
863 698 ATAConfiguration_PrimaryTiming_Device0RecoveryMode |
864 switch(DeviceID) 699 ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode);
865 { 700
866 case 0: 701 if (PIOTimingMode > PIO0)
867 { 702 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable;
868 // mask clear 703
869 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable 704 if (PIOTimingMode >= PIO3)
870 | ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable 705 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable;
871 | ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable 706
872 | ATAConfiguration_PrimaryTiming_Device0DMATimingEnable 707 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
873 | ATAConfiguration_PrimaryTiming_Device0RecoveryMode 708 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable;
874 | ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode 709
875 ); 710 if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
876 711 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable;
877 if (PIOTimingMode > PIO0) 712
878 { 713 if (PIOTimingMode <= PIO2)
879 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable; 714 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0;
880 } 715 else if (PIOTimingMode == PIO3)
881 716 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1;
882 if (PIOTimingMode >= PIO3) 717 else if (PIOTimingMode == PIO4)
883 { 718 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3;
884 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable; 719
885 } 720 if (PIOTimingMode <= PIO1)
886 721 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0;
887 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) 722 else if (PIOTimingMode == PIO2)
888 { 723 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1;
889 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable; 724 else if (PIOTimingMode <= PIO4)
890 } 725 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2;
891 726 break;
892 if (DMAEnable == TRUE 727 case 1:
893 && PIOTimingMode >= PIO2) 728 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable |
894 { 729 ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable |
895 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable; 730 ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable |
896 } 731 ATAConfiguration_PrimaryTiming_Device1DMATimingEnable);
897 732
898 if (PIOTimingMode <= PIO2) 733 if (PIOTimingMode > PIO0)
899 { 734 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable;
900 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0; 735
901 } 736 if (PIOTimingMode >= PIO3)
902 else if (PIOTimingMode == PIO3) 737 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable;
903 { 738
904 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1; 739 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
905 } 740 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable;
906 else if (PIOTimingMode == PIO4) 741
907 { 742 if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
908 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3; 743 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable;
909 } 744
910 745 Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_SecondaryRecoveryMode |
911 if (PIOTimingMode <= PIO1) 746 ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode);
912 { 747
913 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0; 748 if (PIOTimingMode <= PIO2)
914 } 749 Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0;
915 else if (PIOTimingMode == PIO2) 750 else if (PIOTimingMode == PIO3)
916 { 751 Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1;
917 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1; 752 else if (PIOTimingMode == PIO4)
918 } 753 Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3;
919 else if (PIOTimingMode <= PIO4) 754
920 { 755 if (PIOTimingMode <= PIO1)
921 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2; 756 Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0;
922 } 757 else if (PIOTimingMode == PIO2)
923 } 758 Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1;
924 break; 759 else if (PIOTimingMode <= PIO4)
925 case 1: 760 Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2;
926 { 761 break;
927 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable 762 default:
928 | ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable 763 funcresult = FALSE;
929 | ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable 764 goto funcexit;
930 | ATAConfiguration_PrimaryTiming_Device1DMATimingEnable 765 break;
931 ); 766 }
932 767
933 if (PIOTimingMode > PIO0) 768 result = PCIDeviceIO_WritePCIConfiguration(pdev,
934 { 769 ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset,
935 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable; 770 ATAConfiguration_ID_SecondaryTiming_Size,
936 } 771 &ATATimingRegister);
937 772 if (result == FALSE) {
938 if (PIOTimingMode >= PIO3) 773 funcresult = FALSE;
939 { 774 goto funcexit;
940 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable; 775 }
941 } 776
942 777 result = PCIDeviceIO_WritePCIConfiguration(pdev,
943 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE) 778 ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
944 { 779 ATAConfiguration_ID_Device1Timing_Size,
945 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable; 780 &Device1TimingRegister);
946 } 781 if (result == FALSE) {
947 782 funcresult = FALSE;
948 if (DMAEnable == TRUE 783 goto funcexit;
949 && PIOTimingMode >= PIO2) 784 }
950 { 785
951 ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable; 786 goto funcexit;
952 }
953
954 Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_SecondaryRecoveryMode | ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode);
955
956 if (PIOTimingMode <= PIO2)
957 {
958 Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0;
959 }
960 else if (PIOTimingMode == PIO3)
961 {
962 Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1;
963 }
964 else if (PIOTimingMode == PIO4)
965 {
966 Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3;
967 }
968
969 if (PIOTimingMode <= PIO1)
970 {
971 Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0;
972 }
973 else if (PIOTimingMode == PIO2)
974 {
975 Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1;
976 }
977 else if (PIOTimingMode <= PIO4)
978 {
979 Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2;
980 }
981 }
982 break;
983 default:
984 {
985 funcresult = FALSE;
986 goto funcexit;
987 }
988 break;
989 }
990
991 result = PCIDeviceIO_WritePCIConfiguration(
992 pdev,
993 ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset,
994 ATAConfiguration_ID_SecondaryTiming_Size,
995 &ATATimingRegister
996 );
997 if (result == FALSE)
998 {
999 funcresult = FALSE;
1000 goto funcexit;
1001 }
1002
1003 result = PCIDeviceIO_WritePCIConfiguration(
1004 pdev,
1005 ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
1006 ATAConfiguration_ID_Device1Timing_Size,
1007 &Device1TimingRegister
1008 );
1009 if (result == FALSE)
1010 {
1011 funcresult = FALSE;
1012 goto funcexit;
1013 }
1014
1015 goto funcexit;
1016funcexit: 787funcexit:
1017 788 return funcresult;
1018 return funcresult;
1019} 789}
1020 790
1021static uint 791static uint ATAHostAdapter_SetPrimaryUDMA(struct pci_dev *pdev, uint DeviceID,
1022ATAHostAdapter_SetPrimaryUDMA( 792 uint UDMAEnable, uint UDMATimingMode)
1023 struct pci_dev *pdev,
1024 uint DeviceID,
1025 uint UDMAEnable,
1026 uint UDMATimingMode
1027 )
1028{ 793{
1029 uint funcresult; 794 uint funcresult;
1030 795 uint result;
1031 uint result; 796 uint UDMAControlRegister;
1032 797 uint UDMATimingRegister;
1033 uint UDMAControlRegister; 798 ulong IDEIOConfigurationRegister;
1034 uint UDMATimingRegister; 799
1035 ulong IDEIOConfigurationRegister; 800 funcresult = TRUE;
1036 801 UDMAControlRegister = 0;
1037 funcresult = TRUE; 802 UDMATimingRegister = 0;
1038 803 IDEIOConfigurationRegister = 0;
1039 UDMAControlRegister = 0; 804
1040 UDMATimingRegister = 0; 805 result = PCIDeviceIO_ReadPCIConfiguration(pdev,
1041 IDEIOConfigurationRegister = 0; 806 ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
1042 807 ATAConfiguration_ID_UDMAControl_Size,
1043 result = PCIDeviceIO_ReadPCIConfiguration( 808 &UDMAControlRegister);
1044 pdev, 809 if (result == FALSE) {
1045 ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset, 810 funcresult = FALSE;
1046 ATAConfiguration_ID_UDMAControl_Size, 811 goto funcexit;
1047 &UDMAControlRegister 812 }
1048 ); 813
1049 if (result == FALSE) 814 result = PCIDeviceIO_ReadPCIConfiguration(pdev,
1050 { 815 ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
1051 funcresult = FALSE; 816 ATAConfiguration_ID_UDMATiming_Size,
1052 goto funcexit; 817 &UDMATimingRegister);
1053 } 818 if (result == FALSE) {
1054 819 funcresult = FALSE;
1055 result = PCIDeviceIO_ReadPCIConfiguration( 820 goto funcexit;
1056 pdev, 821 }
1057 ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset, 822
1058 ATAConfiguration_ID_UDMATiming_Size, 823 result = PCIDeviceIO_ReadPCIConfiguration(pdev,
1059 &UDMATimingRegister 824 ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
1060 ); 825 ATAConfiguration_ID_IDEIOConfiguration_Size,
1061 if (result == FALSE) 826 &IDEIOConfigurationRegister);
1062 { 827 if (result == FALSE) {
1063 funcresult = FALSE; 828 funcresult = FALSE;
1064 goto funcexit; 829 goto funcexit;
1065 } 830 }
1066 831
1067 result = PCIDeviceIO_ReadPCIConfiguration( 832 /*Rom Code will determine the device cable type and ATA 100.*/
1068 pdev, 833 /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report;*/
1069 ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, 834 /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported;*/
1070 ATAConfiguration_ID_IDEIOConfiguration_Size, 835
1071 &IDEIOConfigurationRegister 836 switch (DeviceID) {
1072 ); 837 case 0:
1073 if (result == FALSE) 838 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable);
1074 { 839 if (UDMAEnable == TRUE)
1075 funcresult = FALSE; 840 UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable;
1076 goto funcexit; 841
1077 } 842 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable |
1078 843 ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable);
1079 //Rom Code will determine the device cable type and ATA 100. 844
1080 //IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report; 845 if (UDMATimingMode >= UDMA5)
1081 //IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported; 846 IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable;
1082 847 else if (UDMATimingMode >= UDMA3)
1083 switch(DeviceID) 848 IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable;
1084 { 849
1085 case 0: 850 /* if 80 cable report */
1086 { 851 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime);
1087 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable); 852
1088 if (UDMAEnable == TRUE) 853 if (UDMATimingMode == UDMA0) {
1089 { 854 UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0;
1090 UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable; 855 } else if (UDMATimingMode == UDMA1 ||
1091 } 856 UDMATimingMode == UDMA3 ||
1092 857 UDMATimingMode == UDMA5) {
1093 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable 858 UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1;
1094 | ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable 859 } else if (UDMATimingMode == UDMA2 ||
1095 ); 860 UDMATimingMode == UDMA4) {
1096 861 UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2;
1097 if (UDMATimingMode >= UDMA5) 862 }
1098 { 863 break;
1099 IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable; 864 case 1:
1100 } 865 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable);
1101 else if (UDMATimingMode >= UDMA3) 866 if (UDMAEnable == TRUE)
1102 { 867 UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable;
1103 IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable; 868
1104 } 869 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable |
1105 870 ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable);
1106 // if 80 cable report 871
1107 872 if (UDMATimingMode >= UDMA5)
1108 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime); 873 IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable;
1109 874 else if (UDMATimingMode >= UDMA3)
1110 if (UDMATimingMode == UDMA0) 875 IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable;
1111 { 876
1112 UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0; 877 /* if 80 cable report */
1113 } 878 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime);
1114 else if (UDMATimingMode == UDMA1 || UDMATimingMode == UDMA3 || UDMATimingMode == UDMA5) 879
1115 { 880 if (UDMATimingMode == UDMA0) {
1116 UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1; 881 UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0;
1117 } 882 } else if (UDMATimingMode == UDMA1 ||
1118 else if (UDMATimingMode == UDMA2 || UDMATimingMode == UDMA4) 883 UDMATimingMode == UDMA3 ||
1119 { 884 UDMATimingMode == UDMA5) {
1120 UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2; 885 UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1;
1121 } 886 } else if (UDMATimingMode == UDMA2 ||
1122 } 887 UDMATimingMode == UDMA4) {
1123 break; 888 UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2;
1124 case 1: 889 }
1125 { 890 break;
1126 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable); 891 default:
1127 if (UDMAEnable == TRUE) 892 funcresult = FALSE;
1128 { 893 goto funcexit;
1129 UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable; 894 break;
1130 } 895 }
1131 896
1132 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable 897 result = PCIDeviceIO_WritePCIConfiguration(pdev,
1133 | ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable 898 ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
1134 ); 899 ATAConfiguration_ID_UDMAControl_Size,
1135 900 &UDMAControlRegister);
1136 if (UDMATimingMode >= UDMA5) 901 if (result == FALSE) {
1137 { 902 funcresult = FALSE;
1138 IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable; 903 goto funcexit;
1139 } 904 }
1140 else if (UDMATimingMode >= UDMA3) 905
1141 { 906 result = PCIDeviceIO_WritePCIConfiguration(pdev,
1142 IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable; 907 ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
1143 } 908 ATAConfiguration_ID_UDMATiming_Size,
1144 909 &UDMATimingRegister);
1145 // if 80 cable report 910 if (result == FALSE) {
1146 911 funcresult = FALSE;
1147 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime); 912 goto funcexit;
1148 913 }
1149 if (UDMATimingMode == UDMA0) 914
1150 { 915 result = PCIDeviceIO_WritePCIConfiguration(pdev,
1151 UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0; 916 ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
1152 } 917 ATAConfiguration_ID_IDEIOConfiguration_Size,
1153 else if (UDMATimingMode == UDMA1 || UDMATimingMode == UDMA3 || UDMATimingMode == UDMA5) 918 &IDEIOConfigurationRegister);
1154 { 919 if (result == FALSE) {
1155 UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1; 920 funcresult = FALSE;
1156 } 921 goto funcexit;
1157 else if (UDMATimingMode == UDMA2 || UDMATimingMode == UDMA4) 922 }
1158 { 923
1159 UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2; 924 goto funcexit;
1160 }
1161 }
1162 break;
1163 default:
1164 {
1165 funcresult = FALSE;
1166 goto funcexit;
1167 }
1168 break;
1169 }
1170
1171 result = PCIDeviceIO_WritePCIConfiguration(
1172 pdev,
1173 ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
1174 ATAConfiguration_ID_UDMAControl_Size,
1175 &UDMAControlRegister
1176 );
1177 if (result == FALSE)
1178 {
1179 funcresult = FALSE;
1180 goto funcexit;
1181 }
1182
1183 result = PCIDeviceIO_WritePCIConfiguration(
1184 pdev,
1185 ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
1186 ATAConfiguration_ID_UDMATiming_Size,
1187 &UDMATimingRegister
1188 );
1189 if (result == FALSE)
1190 {
1191 funcresult = FALSE;
1192 goto funcexit;
1193 }
1194
1195 result = PCIDeviceIO_WritePCIConfiguration(
1196 pdev,
1197 ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
1198 ATAConfiguration_ID_IDEIOConfiguration_Size,
1199 &IDEIOConfigurationRegister
1200 );
1201 if (result == FALSE)
1202 {
1203 funcresult = FALSE;
1204 goto funcexit;
1205 }
1206
1207 goto funcexit;
1208funcexit: 925funcexit:
1209 926 return funcresult;
1210 return funcresult;
1211} 927}
1212 928
1213static uint 929static uint ATAHostAdapter_SetSecondaryUDMA(struct pci_dev *pdev, uint DeviceID,
1214ATAHostAdapter_SetSecondaryUDMA( 930 uint UDMAEnable, uint UDMATimingMode)
1215 struct pci_dev *pdev,
1216 uint DeviceID,
1217 uint UDMAEnable,
1218 uint UDMATimingMode
1219 )
1220{ 931{
1221 uint funcresult; 932 uint funcresult;
1222 933 uint result;
1223 uint result; 934 uint UDMAControlRegister;
1224 935 uint UDMATimingRegister;
1225 uint UDMAControlRegister; 936 ulong IDEIOConfigurationRegister;
1226 uint UDMATimingRegister; 937
1227 ulong IDEIOConfigurationRegister; 938 funcresult = TRUE;
1228 939
1229 funcresult = TRUE; 940 UDMAControlRegister = 0;
1230 941 UDMATimingRegister = 0;
1231 UDMAControlRegister = 0; 942 IDEIOConfigurationRegister = 0;
1232 UDMATimingRegister = 0; 943
1233 IDEIOConfigurationRegister = 0; 944 result = PCIDeviceIO_ReadPCIConfiguration(pdev,
1234 945 ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
1235 result = PCIDeviceIO_ReadPCIConfiguration( 946 ATAConfiguration_ID_UDMAControl_Size,
1236 pdev, 947 &UDMAControlRegister);
1237 ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset, 948 if (result == FALSE) {
1238 ATAConfiguration_ID_UDMAControl_Size, 949 funcresult = FALSE;
1239 &UDMAControlRegister 950 goto funcexit;
1240 ); 951 }
1241 if (result == FALSE) 952
1242 { 953 result = PCIDeviceIO_ReadPCIConfiguration(pdev,
1243 funcresult = FALSE; 954 ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
1244 goto funcexit; 955 ATAConfiguration_ID_UDMATiming_Size,
1245 } 956 &UDMATimingRegister);
1246 957 if (result == FALSE) {
1247 result = PCIDeviceIO_ReadPCIConfiguration( 958 funcresult = FALSE;
1248 pdev, 959 goto funcexit;
1249 ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset, 960 }
1250 ATAConfiguration_ID_UDMATiming_Size, 961
1251 &UDMATimingRegister 962 result = PCIDeviceIO_ReadPCIConfiguration(pdev,
1252 ); 963 ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
1253 if (result == FALSE) 964 ATAConfiguration_ID_IDEIOConfiguration_Size,
1254 { 965 &IDEIOConfigurationRegister);
1255 funcresult = FALSE; 966 if (result == FALSE) {
1256 goto funcexit; 967 funcresult = FALSE;
1257 } 968 goto funcexit;
1258 969 }
1259 result = PCIDeviceIO_ReadPCIConfiguration( 970
1260 pdev, 971 /* Rom Code will determine the device cable type and ATA 100. */
1261 ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, 972 /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report; */
1262 ATAConfiguration_ID_IDEIOConfiguration_Size, 973 /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported; */
1263 &IDEIOConfigurationRegister 974
1264 ); 975 switch (DeviceID) {
1265 if (result == FALSE) 976 case 0:
1266 { 977 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable);
1267 funcresult = FALSE; 978 if (UDMAEnable == TRUE)
1268 goto funcexit; 979 UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable;
1269 } 980
1270 981 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable |
1271 //Rom Code will determine the device cable type and ATA 100. 982 ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable);
1272 //IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report; 983
1273 //IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported; 984 if (UDMATimingMode >= UDMA5)
1274 985 IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable;
1275 switch(DeviceID) 986 else if (UDMATimingMode >= UDMA3)
1276 { 987 IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable;
1277 case 0: 988
1278 { 989 /* if 80 cable report */
1279 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable); 990 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime);
1280 if (UDMAEnable == TRUE) 991
1281 { 992 if (UDMATimingMode == UDMA0) {
1282 UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable; 993 UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0;
1283 } 994 } else if (UDMATimingMode == UDMA1 ||
1284 995 UDMATimingMode == UDMA3 ||
1285 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable 996 UDMATimingMode == UDMA5) {
1286 | ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable 997 UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1;
1287 ); 998 } else if (UDMATimingMode == UDMA2 ||
1288 999 UDMATimingMode == UDMA4) {
1289 if (UDMATimingMode >= UDMA5) 1000 UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2;
1290 { 1001 }
1291 IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable; 1002 break;
1292 } 1003 case 1:
1293 else if (UDMATimingMode >= UDMA3) 1004 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable);
1294 { 1005 if (UDMAEnable == TRUE)
1295 IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable; 1006 UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable;
1296 } 1007
1297 1008 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable |
1298 // if 80 cable report 1009 ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable);
1299 1010
1300 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime); 1011 if (UDMATimingMode >= UDMA5)
1301 1012 IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable;
1302 if (UDMATimingMode == UDMA0) 1013 else if (UDMATimingMode >= UDMA3)
1303 { 1014 IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable;
1304 UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0; 1015
1305 } 1016 /* if 80 cable report */
1306 else if (UDMATimingMode == UDMA1 || UDMATimingMode == UDMA3 || UDMATimingMode == UDMA5) 1017 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime);
1307 { 1018
1308 UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1; 1019 if (UDMATimingMode == UDMA0) {
1309 } 1020 UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0;
1310 else if (UDMATimingMode == UDMA2 || UDMATimingMode == UDMA4) 1021 } else if (UDMATimingMode == UDMA1 ||
1311 { 1022 UDMATimingMode == UDMA3 ||
1312 UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2; 1023 UDMATimingMode == UDMA5) {
1313 } 1024 UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1;
1314 } 1025 } else if (UDMATimingMode == UDMA2 ||
1315 break; 1026 UDMATimingMode == UDMA4) {
1316 case 1: 1027 UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2;
1317 { 1028 }
1318 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable); 1029 break;
1319 if (UDMAEnable == TRUE) 1030 default:
1320 { 1031 funcresult = FALSE;
1321 UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable; 1032 goto funcexit;
1322 } 1033 break;
1323 1034 }
1324 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable 1035
1325 | ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable 1036 result = PCIDeviceIO_WritePCIConfiguration(pdev,
1326 ); 1037 ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
1327 1038 ATAConfiguration_ID_UDMAControl_Size,
1328 if (UDMATimingMode >= UDMA5) 1039 &UDMAControlRegister);
1329 { 1040 if (result == FALSE) {
1330 IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable; 1041 funcresult = FALSE;
1331 } 1042 goto funcexit;
1332 else if (UDMATimingMode >= UDMA3) 1043 }
1333 { 1044
1334 IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable; 1045 result = PCIDeviceIO_WritePCIConfiguration(pdev,
1335 } 1046 ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
1336 1047 ATAConfiguration_ID_UDMATiming_Size,
1337 // if 80 cable report 1048 &UDMATimingRegister);
1338 1049 if (result == FALSE) {
1339 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime); 1050 funcresult = FALSE;
1340 1051 goto funcexit;
1341 if (UDMATimingMode == UDMA0) 1052 }
1342 { 1053
1343 UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0; 1054 result = PCIDeviceIO_WritePCIConfiguration(pdev,
1344 } 1055 ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
1345 else if (UDMATimingMode == UDMA1 || UDMATimingMode == UDMA3 || UDMATimingMode == UDMA5) 1056 ATAConfiguration_ID_IDEIOConfiguration_Size,
1346 { 1057 &IDEIOConfigurationRegister);
1347 UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1; 1058 if (result == FALSE) {
1348 } 1059 funcresult = FALSE;
1349 else if (UDMATimingMode == UDMA2 || UDMATimingMode == UDMA4) 1060 goto funcexit;
1350 { 1061 }
1351 UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2; 1062
1352 } 1063 goto funcexit;
1353 }
1354 break;
1355 default:
1356 {
1357 funcresult = FALSE;
1358 goto funcexit;
1359 }
1360 break;
1361 }
1362
1363 result = PCIDeviceIO_WritePCIConfiguration(
1364 pdev,
1365 ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
1366 ATAConfiguration_ID_UDMAControl_Size,
1367 &UDMAControlRegister
1368 );
1369 if (result == FALSE)
1370 {
1371 funcresult = FALSE;
1372 goto funcexit;
1373 }
1374
1375 result = PCIDeviceIO_WritePCIConfiguration(
1376 pdev,
1377 ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
1378 ATAConfiguration_ID_UDMATiming_Size,
1379 &UDMATimingRegister
1380 );
1381 if (result == FALSE)
1382 {
1383 funcresult = FALSE;
1384 goto funcexit;
1385 }
1386
1387 result = PCIDeviceIO_WritePCIConfiguration(
1388 pdev,
1389 ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
1390 ATAConfiguration_ID_IDEIOConfiguration_Size,
1391 &IDEIOConfigurationRegister
1392 );
1393 if (result == FALSE)
1394 {
1395 funcresult = FALSE;
1396 goto funcexit;
1397 }
1398
1399 goto funcexit;
1400funcexit: 1064funcexit:
1401 1065 return funcresult;
1402 return funcresult;
1403} 1066}
diff --git a/drivers/staging/pata_rdc/pata_rdc.h b/drivers/staging/pata_rdc/pata_rdc.h
index af1d79e104d..64adca0c53b 100644
--- a/drivers/staging/pata_rdc/pata_rdc.h
+++ b/drivers/staging/pata_rdc/pata_rdc.h
@@ -2,139 +2,136 @@
2#define pata_rdc_H 2#define pata_rdc_H
3 3
4#ifndef TRUE 4#ifndef TRUE
5#define TRUE 1 5#define TRUE 1
6#endif 6#endif
7 7
8#ifndef FALSE 8#ifndef FALSE
9#define FALSE 0 9#define FALSE 0
10#endif 10#endif
11 11
12// ATA Configuration Register ID offset address size 12/* ATA Configuration Register ID offset address size */
13#define ATAConfiguration_PCIOffset 0x40 13#define ATAConfiguration_PCIOffset 0x40
14#define ATAConfiguration_ID_PrimaryTiming 0x00 14#define ATAConfiguration_ID_PrimaryTiming 0x00
15#define ATAConfiguration_ID_SecondaryTiming 0x02 15#define ATAConfiguration_ID_SecondaryTiming 0x02
16#define ATAConfiguration_ID_Device1Timing 0x04 16#define ATAConfiguration_ID_Device1Timing 0x04
17#define ATAConfiguration_ID_UDMAControl 0x08 17#define ATAConfiguration_ID_UDMAControl 0x08
18#define ATAConfiguration_ID_UDMATiming 0x0A 18#define ATAConfiguration_ID_UDMATiming 0x0A
19#define ATAConfiguration_ID_IDEIOConfiguration 0x14 19#define ATAConfiguration_ID_IDEIOConfiguration 0x14
20 20
21#define ATAConfiguration_ID_PrimaryTiming_Size 2 21#define ATAConfiguration_ID_PrimaryTiming_Size 2
22#define ATAConfiguration_ID_SecondaryTiming_Size 2 22#define ATAConfiguration_ID_SecondaryTiming_Size 2
23#define ATAConfiguration_ID_Device1Timing_Size 1 23#define ATAConfiguration_ID_Device1Timing_Size 1
24#define ATAConfiguration_ID_UDMAControl_Size 1 24#define ATAConfiguration_ID_UDMAControl_Size 1
25#define ATAConfiguration_ID_UDMATiming_Size 2 25#define ATAConfiguration_ID_UDMATiming_Size 2
26#define ATAConfiguration_ID_IDEIOConfiguration_Size 4 26#define ATAConfiguration_ID_IDEIOConfiguration_Size 4
27 27
28// ATA Configuration Register bit define 28/* ATA Configuration Register bit define */
29#define ATAConfiguration_PrimaryTiming_Device0FastTimingEnable 0x0001 29#define ATAConfiguration_PrimaryTiming_Device0FastTimingEnable 0x0001
30#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable 0x0002 // PIO 3 or greater 30#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable 0x0002 /* PIO 3 or greater */
31#define ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable 0x0004 // PIO 2 or greater 31#define ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable 0x0004 /* PIO 2 or greater */
32#define ATAConfiguration_PrimaryTiming_Device0DMATimingEnable 0x0008 32#define ATAConfiguration_PrimaryTiming_Device0DMATimingEnable 0x0008
33#define ATAConfiguration_PrimaryTiming_Device1FastTimingEnable 0x0010 33#define ATAConfiguration_PrimaryTiming_Device1FastTimingEnable 0x0010
34#define ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable 0x0020 // PIO 3 or greater 34#define ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable 0x0020 /* PIO 3 or greater */
35#define ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable 0x0040 // PIO 2 or greater 35#define ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable 0x0040 /* PIO 2 or greater */
36#define ATAConfiguration_PrimaryTiming_Device1DMATimingEnable 0x0080 36#define ATAConfiguration_PrimaryTiming_Device1DMATimingEnable 0x0080
37#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode 0x0300 37#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode 0x0300
38#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0 0x0000 // PIO 0, PIO 2, MDMA 0 38#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0 0x0000 /* PIO 0, PIO 2, MDMA 0 */
39#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1 0x0100 // PIO 3, MDMA 1 39#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1 0x0100 /* PIO 3, MDMA 1 */
40#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_2 0x0200 // X 40#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_2 0x0200 /* X */
41#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3 0x0300 // PIO 4, MDMA 2 41#define ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3 0x0300 /* PIO 4, MDMA 2 */
42#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode 0x3000 42#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode 0x3000
43#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0 0x0000 // PIO 0 43#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0 0x0000 /* PIO 0 */
44#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1 0x1000 // PIO 2, MDMA 0 44#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1 0x1000 /* PIO 2, MDMA 0 */
45#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2 0x2000 // PIO 3, PIO 4, MDMA 1, MDMA 2 45#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2 0x2000 /* PIO 3, PIO 4, MDMA 1, MDMA 2 */
46#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_3 0x3000 // X 46#define ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_3 0x3000 /* X */
47#define ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable 0x4000 47#define ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable 0x4000
48#define ATAConfiguration_PrimaryTiming_IDEDecodeEnable 0x8000 48#define ATAConfiguration_PrimaryTiming_IDEDecodeEnable 0x8000
49 49
50#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode 0x0003 50#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode 0x0003
51#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0 0x0000 51#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0 0x0000
52#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1 0x0001 52#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1 0x0001
53#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_2 0x0002 53#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_2 0x0002
54#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3 0x0003 54#define ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3 0x0003
55#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode 0x000C 55#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode 0x000C
56#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0 0x0000 56#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0 0x0000
57#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1 0x0004 57#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1 0x0004
58#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2 0x0008 58#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2 0x0008
59#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_3 0x000C 59#define ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_3 0x000C
60#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode 0x0030 60#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode 0x0030
61#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0 0x0000 61#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0 0x0000
62#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1 0x0010 62#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1 0x0010
63#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_2 0x0020 63#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_2 0x0020
64#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3 0x0030 64#define ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3 0x0030
65#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode 0x00C0 65#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode 0x00C0
66#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0 0x0000 66#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0 0x0000
67#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1 0x0040 67#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1 0x0040
68#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2 0x0080 68#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2 0x0080
69#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_3 0x00C0 69#define ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_3 0x00C0
70 70
71#define ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable 0x0001 71#define ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable 0x0001
72#define ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable 0x0002 72#define ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable 0x0002
73#define ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable 0x0004 73#define ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable 0x0004
74#define ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable 0x0008 74#define ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable 0x0008
75 75
76#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime 0x0003 76#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime 0x0003
77#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0 0x0000 // UDMA 0 77#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0 0x0000 /* UDMA 0 */
78#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1 0x0001 // UDMA 1, UDMA 3, UDMA 5 78#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1 0x0001 /* UDMA 1, UDMA 3, UDMA 5 */
79#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2 0x0002 // UDMA 2, UDMA 4 79#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2 0x0002 /* UDMA 2, UDMA 4 */
80#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_3 0x0003 // X 80#define ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_3 0x0003 /* X */
81#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime 0x0030 81#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime 0x0030
82#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0 0x0000 // UDMA 0 82#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0 0x0000 /* UDMA 0 */
83#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1 0x0010 // UDMA 1, UDMA 3, UDMA 5 83#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1 0x0010 /* UDMA 1, UDMA 3, UDMA 5 */
84#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2 0x0020 // UDMA 2, UDMA 4 84#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2 0x0020 /* UDMA 2, UDMA 4 */
85#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_3 0x0030 // X 85#define ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_3 0x0030 /* X */
86#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime 0x0300 86#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime 0x0300
87#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0 0x0000 // UDMA 0 87#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0 0x0000 /* UDMA 0 */
88#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1 0x0100 // UDMA 1, UDMA 3, UDMA 5 88#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1 0x0100 /* UDMA 1, UDMA 3, UDMA 5 */
89#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2 0x0200 // UDMA 2, UDMA 4 89#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2 0x0200 /* UDMA 2, UDMA 4 */
90#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_3 0x0300 // X 90#define ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_3 0x0300 /* X */
91#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime 0x3000 91#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime 0x3000
92#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0 0x0000 // UDMA 0 92#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0 0x0000 /* UDMA 0 */
93#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1 0x1000 // UDMA 1, UDMA 3, UDMA 5 93#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1 0x1000 /* UDMA 1, UDMA 3, UDMA 5 */
94#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2 0x2000 // UDMA 2, UDMA 4 94#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2 0x2000 /* UDMA 2, UDMA 4 */
95#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_3 0x3000 // X 95#define ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_3 0x3000 /* X */
96 96
97#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable 0x00000001 // UDMA 3, UDMA 4 97#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable 0x00000001 /* UDMA 3, UDMA 4 */
98#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable 0x00000002 98#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable 0x00000002
99#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable 0x00000004 99#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable 0x00000004
100#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable 0x00000008 100#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable 0x00000008
101#define ATAConfiguration_IDEIOConfiguration_DeviceCable80Report 0x000000F0 101#define ATAConfiguration_IDEIOConfiguration_DeviceCable80Report 0x000000F0
102#define ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report 0x00000030 102#define ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report 0x00000030
103#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice0Cable80Report 0x00000010 // UDMA 3, UDMA 4, UDMA 5 103#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice0Cable80Report 0x00000010 /* UDMA 3, UDMA 4, UDMA 5 */
104#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice1Cable80Report 0x00000020 104#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice1Cable80Report 0x00000020
105#define ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report 0x000000C0 105#define ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report 0x000000C0
106#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice0Cable80Report 0x00000040 106#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice0Cable80Report 0x00000040
107#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice1Cable80Report 0x00000080 107#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice1Cable80Report 0x00000080
108#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable 0x00001000 // UDMA 5 108#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable 0x00001000 /* UDMA 5 */
109#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable 0x00002000 109#define ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable 0x00002000
110#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable 0x00004000 110#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable 0x00004000
111#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable 0x00008000 111#define ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable 0x00008000
112#define ATAConfiguration_IDEIOConfiguration_ATA100IsSupported 0x00F00000 112#define ATAConfiguration_IDEIOConfiguration_ATA100IsSupported 0x00F00000
113 113
114enum _PIOTimingMode 114enum _PIOTimingMode {
115{ 115 PIO0 = 0,
116 PIO0 = 0, 116 PIO1,
117 PIO1, 117 PIO2, /* MDMA 0 */
118 PIO2, // MDMA 0 118 PIO3, /* MDMA 1 */
119 PIO3, // MDMA 1 119 PIO4 /* MDMA 2 */
120 PIO4 // MDMA 2
121}; 120};
122 121
123enum _DMATimingMode 122enum _DMATimingMode {
124{ 123 MDMA0 = 0,
125 MDMA0 = 0, 124 MDMA1,
126 MDMA1, 125 MDMA2
127 MDMA2
128}; 126};
129 127
130enum _UDMATimingMode 128enum _UDMATimingMode {
131{ 129 UDMA0 = 0,
132 UDMA0 = 0, 130 UDMA1,
133 UDMA1, 131 UDMA2,
134 UDMA2, 132 UDMA3,
135 UDMA3, 133 UDMA4,
136 UDMA4, 134 UDMA5
137 UDMA5
138}; 135};
139 136
140 137
@@ -144,94 +141,34 @@ enum rdc_controller_ids {
144 RDC_17F31012 141 RDC_17F31012
145}; 142};
146 143
147// callback function for driver 144/* callback function for driver */
148 145static int rdc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
149static int __devinit rdc_init_one( 146
150 struct pci_dev *pdev, 147/* callback function for ata_port */
151 const struct pci_device_id *ent 148static int rdc_pata_port_start(struct ata_port *ap);
152 ); 149
153 150static void rdc_pata_port_stop(struct ata_port *ap);
154// callback function for ata_port 151
155 152static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline);
156static int rdc_pata_port_start( 153
157 struct ata_port *ap 154static int rdc_pata_cable_detect(struct ata_port *ap);
158 ); 155
159 156static void rdc_pata_set_piomode(struct ata_port *ap, struct ata_device *adev);
160static void rdc_pata_port_stop( 157
161 struct ata_port *ap 158static void rdc_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev);
162 ); 159
163 160/* modified PCIDeviceIO code. */
164static int rdc_pata_prereset( 161static uint PCIDeviceIO_ReadPCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer);
165 struct ata_link *link, 162
166 unsigned long deadline 163static uint PCIDeviceIO_WritePCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer);
167 ); 164
168 165/* modify ATAHostAdapter code */
169static int rdc_pata_cable_detect( 166static uint ATAHostAdapter_SetPrimaryPIO(struct pci_dev *pdev, uint DeviceID, uint PIOTimingMode, uint DMAEnable, uint PrefetchPostingEnable);
170 struct ata_port *ap 167
171 ); 168static uint ATAHostAdapter_SetSecondaryPIO(struct pci_dev *pdev, uint DeviceID, uint PIOTimingMode, uint DMAEnable, uint PrefetchPostingEnable);
172 169
173static void rdc_pata_set_piomode( 170static uint ATAHostAdapter_SetPrimaryUDMA(struct pci_dev *pdev, uint DeviceID, uint UDMAEnable, uint UDMATimingMode);
174 struct ata_port *ap, 171
175 struct ata_device *adev 172static uint ATAHostAdapter_SetSecondaryUDMA(struct pci_dev *pdev, uint DeviceID, uint UDMAEnable, uint UDMATimingMode);
176 );
177
178static void rdc_pata_set_dmamode(
179 struct ata_port *ap,
180 struct ata_device *adev
181 );
182
183// modified PCIDeviceIO code.
184
185static uint
186PCIDeviceIO_ReadPCIConfiguration(
187 struct pci_dev *pdev,
188 uint Offset,
189 uint Length,
190 void* pBuffer
191 );
192
193static uint
194PCIDeviceIO_WritePCIConfiguration(
195 struct pci_dev *pdev,
196 uint Offset,
197 uint Length,
198 void* pBuffer
199 );
200
201// modify ATAHostAdapter code
202
203static uint
204ATAHostAdapter_SetPrimaryPIO(
205 struct pci_dev *pdev,
206 uint DeviceID,
207 uint PIOTimingMode,
208 uint DMAEnable,
209 uint PrefetchPostingEnable
210 );
211
212static uint
213ATAHostAdapter_SetSecondaryPIO(
214 struct pci_dev *pdev,
215 uint DeviceID,
216 uint PIOTimingMode,
217 uint DMAEnable,
218 uint PrefetchPostingEnable
219 );
220
221static uint
222ATAHostAdapter_SetPrimaryUDMA(
223 struct pci_dev *pdev,
224 uint DeviceID,
225 uint UDMAEnable,
226 uint UDMATimingMode
227 );
228
229static uint
230ATAHostAdapter_SetSecondaryUDMA(
231 struct pci_dev *pdev,
232 uint DeviceID,
233 uint UDMAEnable,
234 uint UDMATimingMode
235 );
236 173
237#endif 174#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 09:02:50 -0500