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authorLinus Torvalds <torvalds@linux-foundation.org>2009-12-09 22:02:46 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2009-12-09 22:02:46 -0500
commitaed886ce777590eac87f7ce2897d9f8357754331 (patch)
tree9a86f2c0a68f8aa43192e51a3155286a5a95e0c8 /arch/arm/mach-davinci
parent67dd2f5a669f48e48ea1013fb80522adca8287f4 (diff)
parentc16fe26701013b9f55aa554fc0a13a7320b164ee (diff)
Merge branch 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci
* 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci: (69 commits) davinci: Initial support for Neuros OSD2 platform. davinci: remove unused variable in arch/arm/mach-davinci/board-sffsdr.c davinci: fix section mismatch warning in arch/arm/mach-davinci/board-dm646x-evm.c DaVinci: DM365: Enable DaVinci RTC support for DM365 EVM DA8xx/OMAP-L1xx: Add high speed SD/MMC capabilities davinci: DA8XX/OMAP-L1XX: enable cpuidle and regulator in defconfig davinci: DA850/OMAP-L138: avoid using separate initcall for initializing regulator davinci: DA850/OMAP-L138 EVM: register for cpuidle support davinci: DA8XX/OMAP-L1XX: add support for cpuidle driver register davinci: add CPU idle driver davinci: DA8XX/OMAP-L1XX: fix compiler warning davinci: DA850/OMAP-L138: eliminate static function declaration davinci: DA850/OMAP-L138 EVM: simplify configuration of emac in MII/RMII mode davinci: DA850/OMAP-L138 EVM: get rid of DA850_UI_EXP config option davinci: DA850/OMAP-L138 EVM: implement autodetect of RMII PHY davinci: DA830/OMAP-L137 EVM: do not configure NAND on UI card when MMC/SD is selected davinci: DA830/OMAP-L137 EVM: use runtime detection for UI card davinci: DA830/OMAP-L137 EVM: remove ifdefs inside da830_evm_init() davinci: DA830/OMAP-L137 EVM: fix warning with default config davinci: Add NAND support for DA830/OMAP-L137 EVM platform ...
Diffstat (limited to 'arch/arm/mach-davinci')
-rw-r--r--arch/arm/mach-davinci/Kconfig59
-rw-r--r--arch/arm/mach-davinci/Makefile5
-rw-r--r--arch/arm/mach-davinci/board-da830-evm.c466
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c437
-rw-r--r--arch/arm/mach-davinci/board-dm355-evm.c16
-rw-r--r--arch/arm/mach-davinci/board-dm355-leopard.c13
-rw-r--r--arch/arm/mach-davinci/board-dm365-evm.c57
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c15
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c86
-rw-r--r--arch/arm/mach-davinci/board-neuros-osd2.c323
-rw-r--r--arch/arm/mach-davinci/board-sffsdr.c20
-rw-r--r--arch/arm/mach-davinci/clock.c231
-rw-r--r--arch/arm/mach-davinci/clock.h17
-rw-r--r--arch/arm/mach-davinci/common.c4
-rw-r--r--arch/arm/mach-davinci/cp_intc.c3
-rw-r--r--arch/arm/mach-davinci/cpufreq.c226
-rw-r--r--arch/arm/mach-davinci/cpuidle.c197
-rw-r--r--arch/arm/mach-davinci/da830.c75
-rw-r--r--arch/arm/mach-davinci/da850.c298
-rw-r--r--arch/arm/mach-davinci/devices-da8xx.c106
-rw-r--r--arch/arm/mach-davinci/devices.c6
-rw-r--r--arch/arm/mach-davinci/dm355.c2
-rw-r--r--arch/arm/mach-davinci/dm365.c107
-rw-r--r--arch/arm/mach-davinci/dm644x.c7
-rw-r--r--arch/arm/mach-davinci/dm646x.c11
-rw-r--r--arch/arm/mach-davinci/dma.c105
-rw-r--r--arch/arm/mach-davinci/gpio.c9
-rw-r--r--arch/arm/mach-davinci/include/mach/asp.h3
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h6
-rw-r--r--arch/arm/mach-davinci/include/mach/cpufreq.h26
-rw-r--r--arch/arm/mach-davinci/include/mach/cpuidle.h17
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h26
-rw-r--r--arch/arm/mach-davinci/include/mach/dm365.h10
-rw-r--r--arch/arm/mach-davinci/include/mach/dm644x.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h20
-rw-r--r--arch/arm/mach-davinci/include/mach/system.h3
-rw-r--r--arch/arm/mach-davinci/include/mach/usb.h59
-rw-r--r--arch/arm/mach-davinci/mux.c1
-rw-r--r--arch/arm/mach-davinci/psc.c3
-rw-r--r--arch/arm/mach-davinci/serial.c6
-rw-r--r--arch/arm/mach-davinci/sram.c3
-rw-r--r--arch/arm/mach-davinci/time.c6
-rw-r--r--arch/arm/mach-davinci/usb.c84
44 files changed, 2783 insertions, 393 deletions
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 40866c643f1..033bfede6b6 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -32,11 +32,13 @@ config ARCH_DAVINCI_DA830
32 bool "DA830/OMAP-L137 based system" 32 bool "DA830/OMAP-L137 based system"
33 select CP_INTC 33 select CP_INTC
34 select ARCH_DAVINCI_DA8XX 34 select ARCH_DAVINCI_DA8XX
35 select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1
35 36
36config ARCH_DAVINCI_DA850 37config ARCH_DAVINCI_DA850
37 bool "DA850/OMAP-L138 based system" 38 bool "DA850/OMAP-L138 based system"
38 select CP_INTC 39 select CP_INTC
39 select ARCH_DAVINCI_DA8XX 40 select ARCH_DAVINCI_DA8XX
41 select ARCH_HAS_CPUFREQ
40 42
41config ARCH_DAVINCI_DA8XX 43config ARCH_DAVINCI_DA8XX
42 bool 44 bool
@@ -63,6 +65,13 @@ config MACH_SFFSDR
63 Say Y here to select the Lyrtech Small Form Factor 65 Say Y here to select the Lyrtech Small Form Factor
64 Software Defined Radio (SFFSDR) board. 66 Software Defined Radio (SFFSDR) board.
65 67
68config MACH_NEUROS_OSD2
69 bool "Neuros OSD2 Open Television Set Top Box"
70 depends on ARCH_DAVINCI_DM644x
71 help
72 Configure this option to specify the whether the board used
73 for development is a Neuros OSD2 Open Set Top Box.
74
66config MACH_DAVINCI_DM355_EVM 75config MACH_DAVINCI_DM355_EVM
67 bool "TI DM355 EVM" 76 bool "TI DM355 EVM"
68 default ARCH_DAVINCI_DM355 77 default ARCH_DAVINCI_DM355
@@ -98,16 +107,66 @@ config MACH_DAVINCI_DA830_EVM
98 bool "TI DA830/OMAP-L137 Reference Platform" 107 bool "TI DA830/OMAP-L137 Reference Platform"
99 default ARCH_DAVINCI_DA830 108 default ARCH_DAVINCI_DA830
100 depends on ARCH_DAVINCI_DA830 109 depends on ARCH_DAVINCI_DA830
110 select GPIO_PCF857X
101 help 111 help
102 Say Y here to select the TI DA830/OMAP-L137 Evaluation Module. 112 Say Y here to select the TI DA830/OMAP-L137 Evaluation Module.
103 113
114choice
115 prompt "Select DA830/OMAP-L137 UI board peripheral"
116 depends on MACH_DAVINCI_DA830_EVM
117 help
118 The presence of UI card on the DA830/OMAP-L137 EVM is detected
119 automatically based on successful probe of the I2C based GPIO
120 expander on that board. This option selected in this menu has
121 an effect only in case of a successful UI card detection.
122
123config DA830_UI_LCD
124 bool "LCD"
125 help
126 Say Y here to use the LCD as a framebuffer or simple character
127 display.
128
129config DA830_UI_NAND
130 bool "NAND flash"
131 help
132 Say Y here to use the NAND flash. Do not forget to setup
133 the switch correctly.
134endchoice
135
104config MACH_DAVINCI_DA850_EVM 136config MACH_DAVINCI_DA850_EVM
105 bool "TI DA850/OMAP-L138 Reference Platform" 137 bool "TI DA850/OMAP-L138 Reference Platform"
106 default ARCH_DAVINCI_DA850 138 default ARCH_DAVINCI_DA850
107 depends on ARCH_DAVINCI_DA850 139 depends on ARCH_DAVINCI_DA850
140 select GPIO_PCA953X
108 help 141 help
109 Say Y here to select the TI DA850/OMAP-L138 Evaluation Module. 142 Say Y here to select the TI DA850/OMAP-L138 Evaluation Module.
110 143
144choice
145 prompt "Select peripherals connected to expander on UI board"
146 depends on MACH_DAVINCI_DA850_EVM
147 help
148 The presence of User Interface (UI) card on the DA850/OMAP-L138
149 EVM is detected automatically based on successful probe of the I2C
150 based GPIO expander on that card. This option selected in this
151 menu has an effect only in case of a successful UI card detection.
152
153config DA850_UI_NONE
154 bool "No peripheral is enabled"
155 help
156 Say Y if you do not want to enable any of the peripherals connected
157 to TCA6416 expander on DA850/OMAP-L138 EVM UI card
158
159config DA850_UI_RMII
160 bool "RMII Ethernet PHY"
161 help
162 Say Y if you want to use the RMII PHY on the DA850/OMAP-L138 EVM.
163 This PHY is found on the UI daughter card that is supplied with
164 the EVM.
165 NOTE: Please take care while choosing this option, MII PHY will
166 not be functional if RMII mode is selected.
167
168endchoice
169
111config DAVINCI_MUX 170config DAVINCI_MUX
112 bool "DAVINCI multiplexing support" 171 bool "DAVINCI multiplexing support"
113 depends on ARCH_DAVINCI 172 depends on ARCH_DAVINCI
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 2e11e847313..eeb9230d884 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -23,9 +23,14 @@ obj-$(CONFIG_CP_INTC) += cp_intc.o
23# Board specific 23# Board specific
24obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o 24obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o
25obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o 25obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o
26obj-$(CONFIG_MACH_NEUROS_OSD2) += board-neuros-osd2.o
26obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o 27obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o
27obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o 28obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o
28obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o 29obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o
29obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o 30obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o
30obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o 31obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o
31obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o 32obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
33
34# Power Management
35obj-$(CONFIG_CPU_FREQ) += cpufreq.o
36obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index bfbb63936f3..31dc9901e55 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -10,51 +10,194 @@
10 * or implied. 10 * or implied.
11 */ 11 */
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/init.h> 13#include <linux/init.h>
15#include <linux/console.h> 14#include <linux/console.h>
15#include <linux/interrupt.h>
16#include <linux/gpio.h>
17#include <linux/platform_device.h>
16#include <linux/i2c.h> 18#include <linux/i2c.h>
19#include <linux/i2c/pcf857x.h>
17#include <linux/i2c/at24.h> 20#include <linux/i2c/at24.h>
21#include <linux/mtd/mtd.h>
22#include <linux/mtd/partitions.h>
18 23
19#include <asm/mach-types.h> 24#include <asm/mach-types.h>
20#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
21 26
22#include <mach/common.h>
23#include <mach/irqs.h>
24#include <mach/cp_intc.h> 27#include <mach/cp_intc.h>
28#include <mach/mux.h>
29#include <mach/nand.h>
25#include <mach/da8xx.h> 30#include <mach/da8xx.h>
26#include <mach/asp.h> 31#include <mach/usb.h>
27 32
28#define DA830_EVM_PHY_MASK 0x0 33#define DA830_EVM_PHY_MASK 0x0
29#define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ 34#define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
30 35
31static struct at24_platform_data da830_evm_i2c_eeprom_info = { 36#define DA830_EMIF25_ASYNC_DATA_CE3_BASE 0x62000000
32 .byte_len = SZ_256K / 8, 37#define DA830_EMIF25_CONTROL_BASE 0x68000000
33 .page_size = 64,
34 .flags = AT24_FLAG_ADDR16,
35 .setup = davinci_get_mac_addr,
36 .context = (void *)0x7f00,
37};
38 38
39static struct i2c_board_info __initdata da830_evm_i2c_devices[] = { 39/*
40 { 40 * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
41 I2C_BOARD_INFO("24c256", 0x50), 41 */
42 .platform_data = &da830_evm_i2c_eeprom_info, 42#define ON_BD_USB_DRV GPIO_TO_PIN(1, 15)
43 }, 43#define ON_BD_USB_OVC GPIO_TO_PIN(2, 4)
44 { 44
45 I2C_BOARD_INFO("tlv320aic3x", 0x18), 45static const short da830_evm_usb11_pins[] = {
46 } 46 DA830_GPIO1_15, DA830_GPIO2_4,
47 -1
47}; 48};
48 49
49static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = { 50static da8xx_ocic_handler_t da830_evm_usb_ocic_handler;
50 .bus_freq = 100, /* kHz */ 51
51 .bus_delay = 0, /* usec */ 52static int da830_evm_usb_set_power(unsigned port, int on)
53{
54 gpio_set_value(ON_BD_USB_DRV, on);
55 return 0;
56}
57
58static int da830_evm_usb_get_power(unsigned port)
59{
60 return gpio_get_value(ON_BD_USB_DRV);
61}
62
63static int da830_evm_usb_get_oci(unsigned port)
64{
65 return !gpio_get_value(ON_BD_USB_OVC);
66}
67
68static irqreturn_t da830_evm_usb_ocic_irq(int, void *);
69
70static int da830_evm_usb_ocic_notify(da8xx_ocic_handler_t handler)
71{
72 int irq = gpio_to_irq(ON_BD_USB_OVC);
73 int error = 0;
74
75 if (handler != NULL) {
76 da830_evm_usb_ocic_handler = handler;
77
78 error = request_irq(irq, da830_evm_usb_ocic_irq, IRQF_DISABLED |
79 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
80 "OHCI over-current indicator", NULL);
81 if (error)
82 printk(KERN_ERR "%s: could not request IRQ to watch "
83 "over-current indicator changes\n", __func__);
84 } else
85 free_irq(irq, NULL);
86
87 return error;
88}
89
90static struct da8xx_ohci_root_hub da830_evm_usb11_pdata = {
91 .set_power = da830_evm_usb_set_power,
92 .get_power = da830_evm_usb_get_power,
93 .get_oci = da830_evm_usb_get_oci,
94 .ocic_notify = da830_evm_usb_ocic_notify,
95
96 /* TPS2065 switch @ 5V */
97 .potpgt = (3 + 1) / 2, /* 3 ms max */
52}; 98};
53 99
100static irqreturn_t da830_evm_usb_ocic_irq(int irq, void *dev_id)
101{
102 da830_evm_usb_ocic_handler(&da830_evm_usb11_pdata, 1);
103 return IRQ_HANDLED;
104}
105
106static __init void da830_evm_usb_init(void)
107{
108 u32 cfgchip2;
109 int ret;
110
111 /*
112 * Set up USB clock/mode in the CFGCHIP2 register.
113 * FYI: CFGCHIP2 is 0x0000ef00 initially.
114 */
115 cfgchip2 = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP2_REG));
116
117 /* USB2.0 PHY reference clock is 24 MHz */
118 cfgchip2 &= ~CFGCHIP2_REFFREQ;
119 cfgchip2 |= CFGCHIP2_REFFREQ_24MHZ;
120
121 /*
122 * Select internal reference clock for USB 2.0 PHY
123 * and use it as a clock source for USB 1.1 PHY
124 * (this is the default setting anyway).
125 */
126 cfgchip2 &= ~CFGCHIP2_USB1PHYCLKMUX;
127 cfgchip2 |= CFGCHIP2_USB2PHYCLKMUX;
128
129 /*
130 * We have to override VBUS/ID signals when MUSB is configured into the
131 * host-only mode -- ID pin will float if no cable is connected, so the
132 * controller won't be able to drive VBUS thinking that it's a B-device.
133 * Otherwise, we want to use the OTG mode and enable VBUS comparators.
134 */
135 cfgchip2 &= ~CFGCHIP2_OTGMODE;
136#ifdef CONFIG_USB_MUSB_HOST
137 cfgchip2 |= CFGCHIP2_FORCE_HOST;
138#else
139 cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN;
140#endif
141
142 __raw_writel(cfgchip2, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP2_REG));
143
144 /* USB_REFCLKIN is not used. */
145 ret = davinci_cfg_reg(DA830_USB0_DRVVBUS);
146 if (ret)
147 pr_warning("%s: USB 2.0 PinMux setup failed: %d\n",
148 __func__, ret);
149 else {
150 /*
151 * TPS2065 switch @ 5V supplies 1 A (sustains 1.5 A),
152 * with the power on to power good time of 3 ms.
153 */
154 ret = da8xx_register_usb20(1000, 3);
155 if (ret)
156 pr_warning("%s: USB 2.0 registration failed: %d\n",
157 __func__, ret);
158 }
159
160 ret = da8xx_pinmux_setup(da830_evm_usb11_pins);
161 if (ret) {
162 pr_warning("%s: USB 1.1 PinMux setup failed: %d\n",
163 __func__, ret);
164 return;
165 }
166
167 ret = gpio_request(ON_BD_USB_DRV, "ON_BD_USB_DRV");
168 if (ret) {
169 printk(KERN_ERR "%s: failed to request GPIO for USB 1.1 port "
170 "power control: %d\n", __func__, ret);
171 return;
172 }
173 gpio_direction_output(ON_BD_USB_DRV, 0);
174
175 ret = gpio_request(ON_BD_USB_OVC, "ON_BD_USB_OVC");
176 if (ret) {
177 printk(KERN_ERR "%s: failed to request GPIO for USB 1.1 port "
178 "over-current indicator: %d\n", __func__, ret);
179 return;
180 }
181 gpio_direction_input(ON_BD_USB_OVC);
182
183 ret = da8xx_register_usb11(&da830_evm_usb11_pdata);
184 if (ret)
185 pr_warning("%s: USB 1.1 registration failed: %d\n",
186 __func__, ret);
187}
188
54static struct davinci_uart_config da830_evm_uart_config __initdata = { 189static struct davinci_uart_config da830_evm_uart_config __initdata = {
55 .enabled_uarts = 0x7, 190 .enabled_uarts = 0x7,
56}; 191};
57 192
193static const short da830_evm_mcasp1_pins[] = {
194 DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1,
195 DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5,
196 DA830_ACLKR1, DA830_AXR1_6, DA830_AXR1_7, DA830_AXR1_8, DA830_AXR1_10,
197 DA830_AXR1_11,
198 -1
199};
200
58static u8 da830_iis_serializer_direction[] = { 201static u8 da830_iis_serializer_direction[] = {
59 RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, 202 RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
60 INACTIVE_MODE, TX_MODE, INACTIVE_MODE, INACTIVE_MODE, 203 INACTIVE_MODE, TX_MODE, INACTIVE_MODE, INACTIVE_MODE,
@@ -74,6 +217,271 @@ static struct snd_platform_data da830_evm_snd_data = {
74 .rxnumevt = 1, 217 .rxnumevt = 1,
75}; 218};
76 219
220/*
221 * GPIO2[1] is used as MMC_SD_WP and GPIO2[2] as MMC_SD_INS.
222 */
223static const short da830_evm_mmc_sd_pins[] = {
224 DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
225 DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
226 DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
227 DA830_MMCSD_CMD, DA830_GPIO2_1, DA830_GPIO2_2,
228 -1
229};
230
231#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1)
232
233static int da830_evm_mmc_get_ro(int index)
234{
235 return gpio_get_value(DA830_MMCSD_WP_PIN);
236}
237
238static struct davinci_mmc_config da830_evm_mmc_config = {
239 .get_ro = da830_evm_mmc_get_ro,
240 .wires = 4,
241 .max_freq = 50000000,
242 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
243 .version = MMC_CTLR_VERSION_2,
244};
245
246static inline void da830_evm_init_mmc(void)
247{
248 int ret;
249
250 ret = da8xx_pinmux_setup(da830_evm_mmc_sd_pins);
251 if (ret) {
252 pr_warning("da830_evm_init: mmc/sd mux setup failed: %d\n",
253 ret);
254 return;
255 }
256
257 ret = gpio_request(DA830_MMCSD_WP_PIN, "MMC WP");
258 if (ret) {
259 pr_warning("da830_evm_init: can not open GPIO %d\n",
260 DA830_MMCSD_WP_PIN);
261 return;
262 }
263 gpio_direction_input(DA830_MMCSD_WP_PIN);
264
265 ret = da8xx_register_mmcsd0(&da830_evm_mmc_config);
266 if (ret) {
267 pr_warning("da830_evm_init: mmc/sd registration failed: %d\n",
268 ret);
269 gpio_free(DA830_MMCSD_WP_PIN);
270 }
271}
272
273/*
274 * UI board NAND/NOR flashes only use 8-bit data bus.
275 */
276static const short da830_evm_emif25_pins[] = {
277 DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
278 DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
279 DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
280 DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
281 DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
282 DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_NEMA_WE,
283 DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, DA830_EMA_WAIT_0,
284 -1
285};
286
287#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
288#define HAS_MMC 1
289#else
290#define HAS_MMC 0
291#endif
292
293#ifdef CONFIG_DA830_UI_NAND
294static struct mtd_partition da830_evm_nand_partitions[] = {
295 /* bootloader (U-Boot, etc) in first sector */
296 [0] = {
297 .name = "bootloader",
298 .offset = 0,
299 .size = SZ_128K,
300 .mask_flags = MTD_WRITEABLE, /* force read-only */
301 },
302 /* bootloader params in the next sector */
303 [1] = {
304 .name = "params",
305 .offset = MTDPART_OFS_APPEND,
306 .size = SZ_128K,
307 .mask_flags = MTD_WRITEABLE, /* force read-only */
308 },
309 /* kernel */
310 [2] = {
311 .name = "kernel",
312 .offset = MTDPART_OFS_APPEND,
313 .size = SZ_2M,
314 .mask_flags = 0,
315 },
316 /* file system */
317 [3] = {
318 .name = "filesystem",
319 .offset = MTDPART_OFS_APPEND,
320 .size = MTDPART_SIZ_FULL,
321 .mask_flags = 0,
322 }
323};
324
325/* flash bbt decriptors */
326static uint8_t da830_evm_nand_bbt_pattern[] = { 'B', 'b', 't', '0' };
327static uint8_t da830_evm_nand_mirror_pattern[] = { '1', 't', 'b', 'B' };
328
329static struct nand_bbt_descr da830_evm_nand_bbt_main_descr = {
330 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE |
331 NAND_BBT_WRITE | NAND_BBT_2BIT |
332 NAND_BBT_VERSION | NAND_BBT_PERCHIP,
333 .offs = 2,
334 .len = 4,
335 .veroffs = 16,
336 .maxblocks = 4,
337 .pattern = da830_evm_nand_bbt_pattern
338};
339
340static struct nand_bbt_descr da830_evm_nand_bbt_mirror_descr = {
341 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE |
342 NAND_BBT_WRITE | NAND_BBT_2BIT |
343 NAND_BBT_VERSION | NAND_BBT_PERCHIP,
344 .offs = 2,
345 .len = 4,
346 .veroffs = 16,
347 .maxblocks = 4,
348 .pattern = da830_evm_nand_mirror_pattern
349};
350
351static struct davinci_nand_pdata da830_evm_nand_pdata = {
352 .parts = da830_evm_nand_partitions,
353 .nr_parts = ARRAY_SIZE(da830_evm_nand_partitions),
354 .ecc_mode = NAND_ECC_HW,
355 .ecc_bits = 4,
356 .options = NAND_USE_FLASH_BBT,
357 .bbt_td = &da830_evm_nand_bbt_main_descr,
358 .bbt_md = &da830_evm_nand_bbt_mirror_descr,
359};
360
361static struct resource da830_evm_nand_resources[] = {
362 [0] = { /* First memory resource is NAND I/O window */
363 .start = DA830_EMIF25_ASYNC_DATA_CE3_BASE,
364 .end = DA830_EMIF25_ASYNC_DATA_CE3_BASE + PAGE_SIZE - 1,
365 .flags = IORESOURCE_MEM,
366 },
367 [1] = { /* Second memory resource is AEMIF control registers */
368 .start = DA830_EMIF25_CONTROL_BASE,
369 .end = DA830_EMIF25_CONTROL_BASE + SZ_32K - 1,
370 .flags = IORESOURCE_MEM,
371 },
372};
373
374static struct platform_device da830_evm_nand_device = {
375 .name = "davinci_nand",
376 .id = 1,
377 .dev = {
378 .platform_data = &da830_evm_nand_pdata,
379 },
380 .num_resources = ARRAY_SIZE(da830_evm_nand_resources),
381 .resource = da830_evm_nand_resources,
382};
383
384static inline void da830_evm_init_nand(int mux_mode)
385{
386 int ret;
387
388 if (HAS_MMC) {
389 pr_warning("WARNING: both MMC/SD and NAND are "
390 "enabled, but they share AEMIF pins.\n"
391 "\tDisable MMC/SD for NAND support.\n");
392 return;
393 }
394
395 ret = da8xx_pinmux_setup(da830_evm_emif25_pins);
396 if (ret)
397 pr_warning("da830_evm_init: emif25 mux setup failed: %d\n",
398 ret);
399
400 ret = platform_device_register(&da830_evm_nand_device);
401 if (ret)
402 pr_warning("da830_evm_init: NAND device not registered.\n");
403
404 gpio_direction_output(mux_mode, 1);
405}
406#else
407static inline void da830_evm_init_nand(int mux_mode) { }
408#endif
409
410#ifdef CONFIG_DA830_UI_LCD
411static inline void da830_evm_init_lcdc(int mux_mode)
412{
413 int ret;
414
415 ret = da8xx_pinmux_setup(da830_lcdcntl_pins);
416 if (ret)
417 pr_warning("da830_evm_init: lcdcntl mux setup failed: %d\n",
418 ret);
419
420 ret = da8xx_register_lcdc(&sharp_lcd035q3dg01_pdata);
421 if (ret)
422 pr_warning("da830_evm_init: lcd setup failed: %d\n", ret);
423
424 gpio_direction_output(mux_mode, 0);
425}
426#else
427static inline void da830_evm_init_lcdc(int mux_mode) { }
428#endif
429
430static struct at24_platform_data da830_evm_i2c_eeprom_info = {
431 .byte_len = SZ_256K / 8,
432 .page_size = 64,
433 .flags = AT24_FLAG_ADDR16,
434 .setup = davinci_get_mac_addr,
435 .context = (void *)0x7f00,
436};
437
438static int __init da830_evm_ui_expander_setup(struct i2c_client *client,
439 int gpio, unsigned ngpio, void *context)
440{
441 gpio_request(gpio + 6, "UI MUX_MODE");
442
443 /* Drive mux mode low to match the default without UI card */
444 gpio_direction_output(gpio + 6, 0);
445
446 da830_evm_init_lcdc(gpio + 6);
447
448 da830_evm_init_nand(gpio + 6);
449
450 return 0;
451}
452
453static int da830_evm_ui_expander_teardown(struct i2c_client *client, int gpio,
454 unsigned ngpio, void *context)
455{
456 gpio_free(gpio + 6);
457 return 0;
458}
459
460static struct pcf857x_platform_data __initdata da830_evm_ui_expander_info = {
461 .gpio_base = DAVINCI_N_GPIO,
462 .setup = da830_evm_ui_expander_setup,
463 .teardown = da830_evm_ui_expander_teardown,
464};
465
466static struct i2c_board_info __initdata da830_evm_i2c_devices[] = {
467 {
468 I2C_BOARD_INFO("24c256", 0x50),
469 .platform_data = &da830_evm_i2c_eeprom_info,
470 },
471 {
472 I2C_BOARD_INFO("tlv320aic3x", 0x18),
473 },
474 {
475 I2C_BOARD_INFO("pcf8574", 0x3f),
476 .platform_data = &da830_evm_ui_expander_info,
477 },
478};
479
480static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = {
481 .bus_freq = 100, /* kHz */
482 .bus_delay = 0, /* usec */
483};
484
77static __init void da830_evm_init(void) 485static __init void da830_evm_init(void)
78{ 486{
79 struct davinci_soc_info *soc_info = &davinci_soc_info; 487 struct davinci_soc_info *soc_info = &davinci_soc_info;
@@ -94,6 +502,8 @@ static __init void da830_evm_init(void)
94 pr_warning("da830_evm_init: i2c0 registration failed: %d\n", 502 pr_warning("da830_evm_init: i2c0 registration failed: %d\n",
95 ret); 503 ret);
96 504
505 da830_evm_usb_init();
506
97 soc_info->emac_pdata->phy_mask = DA830_EVM_PHY_MASK; 507 soc_info->emac_pdata->phy_mask = DA830_EVM_PHY_MASK;
98 soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY; 508 soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY;
99 soc_info->emac_pdata->rmii_en = 1; 509 soc_info->emac_pdata->rmii_en = 1;
@@ -117,12 +527,18 @@ static __init void da830_evm_init(void)
117 i2c_register_board_info(1, da830_evm_i2c_devices, 527 i2c_register_board_info(1, da830_evm_i2c_devices,
118 ARRAY_SIZE(da830_evm_i2c_devices)); 528 ARRAY_SIZE(da830_evm_i2c_devices));
119 529
120 ret = da8xx_pinmux_setup(da830_mcasp1_pins); 530 ret = da8xx_pinmux_setup(da830_evm_mcasp1_pins);
121 if (ret) 531 if (ret)
122 pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n", 532 pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n",
123 ret); 533 ret);
124 534
125 da8xx_init_mcasp(1, &da830_evm_snd_data); 535 da8xx_register_mcasp(1, &da830_evm_snd_data);
536
537 da830_evm_init_mmc();
538
539 ret = da8xx_register_rtc();
540 if (ret)
541 pr_warning("da830_evm_init: rtc setup failed: %d\n", ret);
126} 542}
127 543
128#ifdef CONFIG_SERIAL_8250_CONSOLE 544#ifdef CONFIG_SERIAL_8250_CONSOLE
@@ -146,7 +562,7 @@ static void __init da830_evm_map_io(void)
146 da830_init(); 562 da830_init();
147} 563}
148 564
149MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP L137 EVM") 565MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM")
150 .phys_io = IO_PHYS, 566 .phys_io = IO_PHYS,
151 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 567 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
152 .boot_params = (DA8XX_DDR_BASE + 0x100), 568 .boot_params = (DA8XX_DDR_BASE + 0x100),
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index c759d72494e..62b98bffc15 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -12,36 +12,38 @@
12 * or implied. 12 * or implied.
13 */ 13 */
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/init.h> 15#include <linux/init.h>
17#include <linux/console.h> 16#include <linux/console.h>
18#include <linux/i2c.h> 17#include <linux/i2c.h>
19#include <linux/i2c/at24.h> 18#include <linux/i2c/at24.h>
19#include <linux/i2c/pca953x.h>
20#include <linux/gpio.h> 20#include <linux/gpio.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/mtd/mtd.h> 22#include <linux/mtd/mtd.h>
23#include <linux/mtd/nand.h> 23#include <linux/mtd/nand.h>
24#include <linux/mtd/partitions.h> 24#include <linux/mtd/partitions.h>
25#include <linux/mtd/physmap.h> 25#include <linux/mtd/physmap.h>
26#include <linux/regulator/machine.h>
26 27
27#include <asm/mach-types.h> 28#include <asm/mach-types.h>
28#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
29 30
30#include <mach/common.h>
31#include <mach/irqs.h>
32#include <mach/cp_intc.h> 31#include <mach/cp_intc.h>
33#include <mach/da8xx.h> 32#include <mach/da8xx.h>
34#include <mach/nand.h> 33#include <mach/nand.h>
34#include <mach/mux.h>
35 35
36#define DA850_EVM_PHY_MASK 0x1 36#define DA850_EVM_PHY_MASK 0x1
37#define DA850_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ 37#define DA850_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
38 38
39#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
39#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) 40#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
40#define DA850_LCD_PWR_PIN GPIO_TO_PIN(8, 10)
41 41
42#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) 42#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
43#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) 43#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
44 44
45#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6)
46
45static struct mtd_partition da850_evm_norflash_partition[] = { 47static struct mtd_partition da850_evm_norflash_partition[] = {
46 { 48 {
47 .name = "NOR filesystem", 49 .name = "NOR filesystem",
@@ -143,10 +145,149 @@ static struct platform_device da850_evm_nandflash_device = {
143 .resource = da850_evm_nandflash_resource, 145 .resource = da850_evm_nandflash_resource,
144}; 146};
145 147
148static struct platform_device *da850_evm_devices[] __initdata = {
149 &da850_evm_nandflash_device,
150 &da850_evm_norflash_device,
151};
152
153#define DA8XX_AEMIF_CE2CFG_OFFSET 0x10
154#define DA8XX_AEMIF_ASIZE_16BIT 0x1
155
156static void __init da850_evm_init_nor(void)
157{
158 void __iomem *aemif_addr;
159
160 aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K);
161
162 /* Configure data bus width of CS2 to 16 bit */
163 writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) |
164 DA8XX_AEMIF_ASIZE_16BIT,
165 aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET);
166
167 iounmap(aemif_addr);
168}
169
170static u32 ui_card_detected;
171
172#if defined(CONFIG_MMC_DAVINCI) || \
173 defined(CONFIG_MMC_DAVINCI_MODULE)
174#define HAS_MMC 1
175#else
176#define HAS_MMC 0
177#endif
178
179static __init void da850_evm_setup_nor_nand(void)
180{
181 int ret = 0;
182
183 if (ui_card_detected & !HAS_MMC) {
184 ret = da8xx_pinmux_setup(da850_nand_pins);
185 if (ret)
186 pr_warning("da850_evm_init: nand mux setup failed: "
187 "%d\n", ret);
188
189 ret = da8xx_pinmux_setup(da850_nor_pins);
190 if (ret)
191 pr_warning("da850_evm_init: nor mux setup failed: %d\n",
192 ret);
193
194 da850_evm_init_nor();
195
196 platform_add_devices(da850_evm_devices,
197 ARRAY_SIZE(da850_evm_devices));
198 }
199}
200
201#ifdef CONFIG_DA850_UI_RMII
202static inline void da850_evm_setup_emac_rmii(int rmii_sel)
203{
204 struct davinci_soc_info *soc_info = &davinci_soc_info;
205
206 soc_info->emac_pdata->rmii_en = 1;
207 gpio_set_value(rmii_sel, 0);
208}
209#else
210static inline void da850_evm_setup_emac_rmii(int rmii_sel) { }
211#endif
212
213static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
214 unsigned ngpio, void *c)
215{
216 int sel_a, sel_b, sel_c, ret;
217
218 sel_a = gpio + 7;
219 sel_b = gpio + 6;
220 sel_c = gpio + 5;
221
222 ret = gpio_request(sel_a, "sel_a");
223 if (ret) {
224 pr_warning("Cannot open UI expander pin %d\n", sel_a);
225 goto exp_setup_sela_fail;
226 }
227
228 ret = gpio_request(sel_b, "sel_b");
229 if (ret) {
230 pr_warning("Cannot open UI expander pin %d\n", sel_b);
231 goto exp_setup_selb_fail;
232 }
233
234 ret = gpio_request(sel_c, "sel_c");
235 if (ret) {
236 pr_warning("Cannot open UI expander pin %d\n", sel_c);
237 goto exp_setup_selc_fail;
238 }
239
240 /* deselect all functionalities */
241 gpio_direction_output(sel_a, 1);
242 gpio_direction_output(sel_b, 1);
243 gpio_direction_output(sel_c, 1);
244
245 ui_card_detected = 1;
246 pr_info("DA850/OMAP-L138 EVM UI card detected\n");
247
248 da850_evm_setup_nor_nand();
249
250 da850_evm_setup_emac_rmii(sel_a);
251
252 return 0;
253
254exp_setup_selc_fail:
255 gpio_free(sel_b);
256exp_setup_selb_fail:
257 gpio_free(sel_a);
258exp_setup_sela_fail:
259 return ret;
260}
261
262static int da850_evm_ui_expander_teardown(struct i2c_client *client,
263 unsigned gpio, unsigned ngpio, void *c)
264{
265 /* deselect all functionalities */
266 gpio_set_value(gpio + 5, 1);
267 gpio_set_value(gpio + 6, 1);
268 gpio_set_value(gpio + 7, 1);
269
270 gpio_free(gpio + 5);
271 gpio_free(gpio + 6);
272 gpio_free(gpio + 7);
273
274 return 0;
275}
276
277static struct pca953x_platform_data da850_evm_ui_expander_info = {
278 .gpio_base = DAVINCI_N_GPIO,
279 .setup = da850_evm_ui_expander_setup,
280 .teardown = da850_evm_ui_expander_teardown,
281};
282
146static struct i2c_board_info __initdata da850_evm_i2c_devices[] = { 283static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
147 { 284 {
148 I2C_BOARD_INFO("tlv320aic3x", 0x18), 285 I2C_BOARD_INFO("tlv320aic3x", 0x18),
149 } 286 },
287 {
288 I2C_BOARD_INFO("tca6416", 0x20),
289 .platform_data = &da850_evm_ui_expander_info,
290 },
150}; 291};
151 292
152static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = { 293static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
@@ -158,11 +299,6 @@ static struct davinci_uart_config da850_evm_uart_config __initdata = {
158 .enabled_uarts = 0x7, 299 .enabled_uarts = 0x7,
159}; 300};
160 301
161static struct platform_device *da850_evm_devices[] __initdata = {
162 &da850_evm_nandflash_device,
163 &da850_evm_norflash_device,
164};
165
166/* davinci da850 evm audio machine driver */ 302/* davinci da850 evm audio machine driver */
167static u8 da850_iis_serializer_direction[] = { 303static u8 da850_iis_serializer_direction[] = {
168 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, 304 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
@@ -198,6 +334,8 @@ static struct davinci_mmc_config da850_mmc_config = {
198 .get_ro = da850_evm_mmc_get_ro, 334 .get_ro = da850_evm_mmc_get_ro,
199 .get_cd = da850_evm_mmc_get_cd, 335 .get_cd = da850_evm_mmc_get_cd,
200 .wires = 4, 336 .wires = 4,
337 .max_freq = 50000000,
338 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
201 .version = MMC_CTLR_VERSION_2, 339 .version = MMC_CTLR_VERSION_2,
202}; 340};
203 341
@@ -233,56 +371,227 @@ static int da850_lcd_hw_init(void)
233 return 0; 371 return 0;
234} 372}
235 373
236#define DA8XX_AEMIF_CE2CFG_OFFSET 0x10 374/* TPS65070 voltage regulator support */
237#define DA8XX_AEMIF_ASIZE_16BIT 0x1
238 375
239static void __init da850_evm_init_nor(void) 376/* 3.3V */
240{ 377struct regulator_consumer_supply tps65070_dcdc1_consumers[] = {
241 void __iomem *aemif_addr; 378 {
379 .supply = "usb0_vdda33",
380 },
381 {
382 .supply = "usb1_vdda33",
383 },
384};
242 385
243 aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K); 386/* 3.3V or 1.8V */
387struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
388 {
389 .supply = "dvdd3318_a",
390 },
391 {
392 .supply = "dvdd3318_b",
393 },
394 {
395 .supply = "dvdd3318_c",
396 },
397};
244 398
245 /* Configure data bus width of CS2 to 16 bit */ 399/* 1.2V */
246 writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) | 400struct regulator_consumer_supply tps65070_dcdc3_consumers[] = {
247 DA8XX_AEMIF_ASIZE_16BIT, 401 {
248 aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET); 402 .supply = "cvdd",
403 },
404};
249 405
250 iounmap(aemif_addr); 406/* 1.8V LDO */
251} 407struct regulator_consumer_supply tps65070_ldo1_consumers[] = {
408 {
409 .supply = "sata_vddr",
410 },
411 {
412 .supply = "usb0_vdda18",
413 },
414 {
415 .supply = "usb1_vdda18",
416 },
417 {
418 .supply = "ddr_dvdd18",
419 },
420};
252 421
253#if defined(CONFIG_MTD_PHYSMAP) || \ 422/* 1.2V LDO */
254 defined(CONFIG_MTD_PHYSMAP_MODULE) 423struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
255#define HAS_NOR 1 424 {
256#else 425 .supply = "sata_vdd",
257#define HAS_NOR 0 426 },
258#endif 427 {
428 .supply = "pll0_vdda",
429 },
430 {
431 .supply = "pll1_vdda",
432 },
433 {
434 .supply = "usbs_cvdd",
435 },
436 {
437 .supply = "vddarnwa1",
438 },
439};
259 440
260#if defined(CONFIG_MMC_DAVINCI) || \ 441struct regulator_init_data tps65070_regulator_data[] = {
261 defined(CONFIG_MMC_DAVINCI_MODULE) 442 /* dcdc1 */
262#define HAS_MMC 1 443 {
263#else 444 .constraints = {
264#define HAS_MMC 0 445 .min_uV = 3150000,
265#endif 446 .max_uV = 3450000,
447 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
448 REGULATOR_CHANGE_STATUS),
449 .boot_on = 1,
450 },
451 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc1_consumers),
452 .consumer_supplies = tps65070_dcdc1_consumers,
453 },
266 454
267static __init void da850_evm_init(void) 455 /* dcdc2 */
456 {
457 .constraints = {
458 .min_uV = 1710000,
459 .max_uV = 3450000,
460 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
461 REGULATOR_CHANGE_STATUS),
462 .boot_on = 1,
463 },
464 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers),
465 .consumer_supplies = tps65070_dcdc2_consumers,
466 },
467
468 /* dcdc3 */
469 {
470 .constraints = {
471 .min_uV = 950000,
472 .max_uV = 1320000,
473 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
474 REGULATOR_CHANGE_STATUS),
475 .boot_on = 1,
476 },
477 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers),
478 .consumer_supplies = tps65070_dcdc3_consumers,
479 },
480
481 /* ldo1 */
482 {
483 .constraints = {
484 .min_uV = 1710000,
485 .max_uV = 1890000,
486 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
487 REGULATOR_CHANGE_STATUS),
488 .boot_on = 1,
489 },
490 .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo1_consumers),
491 .consumer_supplies = tps65070_ldo1_consumers,
492 },
493
494 /* ldo2 */
495 {
496 .constraints = {
497 .min_uV = 1140000,
498 .max_uV = 1320000,
499 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
500 REGULATOR_CHANGE_STATUS),
501 .boot_on = 1,
502 },
503 .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo2_consumers),
504 .consumer_supplies = tps65070_ldo2_consumers,
505 },
506};
507
508static struct i2c_board_info __initdata da850evm_tps65070_info[] = {
509 {
510 I2C_BOARD_INFO("tps6507x", 0x48),
511 .platform_data = &tps65070_regulator_data[0],
512 },
513};
514
515static int __init pmic_tps65070_init(void)
268{ 516{
269 struct davinci_soc_info *soc_info = &davinci_soc_info; 517 return i2c_register_board_info(1, da850evm_tps65070_info,
518 ARRAY_SIZE(da850evm_tps65070_info));
519}
520
521static const short da850_evm_lcdc_pins[] = {
522 DA850_GPIO2_8, DA850_GPIO2_15,
523 -1
524};
525
526static int __init da850_evm_config_emac(void)
527{
528 void __iomem *cfg_chip3_base;
270 int ret; 529 int ret;
530 u32 val;
531 struct davinci_soc_info *soc_info = &davinci_soc_info;
532 u8 rmii_en = soc_info->emac_pdata->rmii_en;
533
534 if (!machine_is_davinci_da850_evm())
535 return 0;
536
537 cfg_chip3_base = DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG);
538
539 val = __raw_readl(cfg_chip3_base);
540
541 if (rmii_en) {
542 val |= BIT(8);
543 ret = da8xx_pinmux_setup(da850_rmii_pins);
544 pr_info("EMAC: RMII PHY configured, MII PHY will not be"
545 " functional\n");
546 } else {
547 val &= ~BIT(8);
548 ret = da8xx_pinmux_setup(da850_cpgmac_pins);
549 pr_info("EMAC: MII PHY configured, RMII PHY will not be"
550 " functional\n");
551 }
271 552
272 ret = da8xx_pinmux_setup(da850_nand_pins);
273 if (ret) 553 if (ret)
274 pr_warning("da850_evm_init: nand mux setup failed: %d\n", 554 pr_warning("da850_evm_init: cpgmac/rmii mux setup failed: %d\n",
275 ret); 555 ret);
276 556
277 ret = da8xx_pinmux_setup(da850_nor_pins); 557 /* configure the CFGCHIP3 register for RMII or MII */
558 __raw_writel(val, cfg_chip3_base);
559
560 ret = davinci_cfg_reg(DA850_GPIO2_6);
278 if (ret) 561 if (ret)
279 pr_warning("da850_evm_init: nor mux setup failed: %d\n", 562 pr_warning("da850_evm_init:GPIO(2,6) mux setup "
563 "failed\n");
564
565 ret = gpio_request(DA850_MII_MDIO_CLKEN_PIN, "mdio_clk_en");
566 if (ret) {
567 pr_warning("Cannot open GPIO %d\n",
568 DA850_MII_MDIO_CLKEN_PIN);
569 return ret;
570 }
571
572 /* Enable/Disable MII MDIO clock */
573 gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en);
574
575 soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK;
576 soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY;
577
578 ret = da8xx_register_emac();
579 if (ret)
580 pr_warning("da850_evm_init: emac registration failed: %d\n",
280 ret); 581 ret);
281 582
282 da850_evm_init_nor(); 583 return 0;
584}
585device_initcall(da850_evm_config_emac);
586
587static __init void da850_evm_init(void)
588{
589 int ret;
283 590
284 platform_add_devices(da850_evm_devices, 591 ret = pmic_tps65070_init();
285 ARRAY_SIZE(da850_evm_devices)); 592 if (ret)
593 pr_warning("da850_evm_init: TPS65070 PMIC init failed: %d\n",
594 ret);
286 595
287 ret = da8xx_register_edma(); 596 ret = da8xx_register_edma();
288 if (ret) 597 if (ret)
@@ -299,19 +608,6 @@ static __init void da850_evm_init(void)
299 pr_warning("da850_evm_init: i2c0 registration failed: %d\n", 608 pr_warning("da850_evm_init: i2c0 registration failed: %d\n",
300 ret); 609 ret);
301 610
302 soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK;
303 soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY;
304 soc_info->emac_pdata->rmii_en = 0;
305
306 ret = da8xx_pinmux_setup(da850_cpgmac_pins);
307 if (ret)
308 pr_warning("da850_evm_init: cpgmac mux setup failed: %d\n",
309 ret);
310
311 ret = da8xx_register_emac();
312 if (ret)
313 pr_warning("da850_evm_init: emac registration failed: %d\n",
314 ret);
315 611
316 ret = da8xx_register_watchdog(); 612 ret = da8xx_register_watchdog();
317 if (ret) 613 if (ret)
@@ -319,11 +615,6 @@ static __init void da850_evm_init(void)
319 ret); 615 ret);
320 616
321 if (HAS_MMC) { 617 if (HAS_MMC) {
322 if (HAS_NOR)
323 pr_warning("WARNING: both NOR Flash and MMC/SD are "
324 "enabled, but they share AEMIF pins.\n"
325 "\tDisable one of them.\n");
326
327 ret = da8xx_pinmux_setup(da850_mmcsd0_pins); 618 ret = da8xx_pinmux_setup(da850_mmcsd0_pins);
328 if (ret) 619 if (ret)
329 pr_warning("da850_evm_init: mmcsd0 mux setup failed:" 620 pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
@@ -365,22 +656,42 @@ static __init void da850_evm_init(void)
365 pr_warning("da850_evm_init: mcasp mux setup failed: %d\n", 656 pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
366 ret); 657 ret);
367 658
368 da8xx_init_mcasp(0, &da850_evm_snd_data); 659 da8xx_register_mcasp(0, &da850_evm_snd_data);
369 660
370 ret = da8xx_pinmux_setup(da850_lcdcntl_pins); 661 ret = da8xx_pinmux_setup(da850_lcdcntl_pins);
371 if (ret) 662 if (ret)
372 pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n", 663 pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
373 ret); 664 ret);
374 665
666 /* Handle board specific muxing for LCD here */
667 ret = da8xx_pinmux_setup(da850_evm_lcdc_pins);
668 if (ret)
669 pr_warning("da850_evm_init: evm specific lcd mux setup "
670 "failed: %d\n", ret);
671
375 ret = da850_lcd_hw_init(); 672 ret = da850_lcd_hw_init();
376 if (ret) 673 if (ret)
377 pr_warning("da850_evm_init: lcd initialization failed: %d\n", 674 pr_warning("da850_evm_init: lcd initialization failed: %d\n",
378 ret); 675 ret);
379 676
380 ret = da8xx_register_lcdc(); 677 ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata);
381 if (ret) 678 if (ret)
382 pr_warning("da850_evm_init: lcdc registration failed: %d\n", 679 pr_warning("da850_evm_init: lcdc registration failed: %d\n",
383 ret); 680 ret);
681
682 ret = da8xx_register_rtc();
683 if (ret)
684 pr_warning("da850_evm_init: rtc setup failed: %d\n", ret);
685
686 ret = da850_register_cpufreq();
687 if (ret)
688 pr_warning("da850_evm_init: cpufreq registration failed: %d\n",
689 ret);
690
691 ret = da8xx_register_cpuidle();
692 if (ret)
693 pr_warning("da850_evm_init: cpuidle registration failed: %d\n",
694 ret);
384} 695}
385 696
386#ifdef CONFIG_SERIAL_8250_CONSOLE 697#ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 77e80679882..a9b650dcc17 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -9,15 +9,13 @@
9 * or implied. 9 * or implied.
10 */ 10 */
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/init.h> 12#include <linux/init.h>
14#include <linux/dma-mapping.h> 13#include <linux/err.h>
15#include <linux/platform_device.h> 14#include <linux/platform_device.h>
16#include <linux/mtd/mtd.h> 15#include <linux/mtd/mtd.h>
17#include <linux/mtd/partitions.h> 16#include <linux/mtd/partitions.h>
18#include <linux/mtd/nand.h> 17#include <linux/mtd/nand.h>
19#include <linux/i2c.h> 18#include <linux/i2c.h>
20#include <linux/io.h>
21#include <linux/gpio.h> 19#include <linux/gpio.h>
22#include <linux/clk.h> 20#include <linux/clk.h>
23#include <linux/videodev2.h> 21#include <linux/videodev2.h>
@@ -25,20 +23,15 @@
25#include <linux/spi/spi.h> 23#include <linux/spi/spi.h>
26#include <linux/spi/eeprom.h> 24#include <linux/spi/eeprom.h>
27 25
28#include <asm/setup.h>
29#include <asm/mach-types.h> 26#include <asm/mach-types.h>
30#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
31#include <asm/mach/map.h>
32#include <asm/mach/flash.h>
33 28
34#include <mach/hardware.h>
35#include <mach/dm355.h> 29#include <mach/dm355.h>
36#include <mach/psc.h>
37#include <mach/common.h>
38#include <mach/i2c.h> 30#include <mach/i2c.h>
39#include <mach/serial.h> 31#include <mach/serial.h>
40#include <mach/nand.h> 32#include <mach/nand.h>
41#include <mach/mmc.h> 33#include <mach/mmc.h>
34#include <mach/usb.h>
42 35
43#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000 36#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
44#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 37#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
@@ -86,8 +79,9 @@ static struct davinci_nand_pdata davinci_nand_data = {
86 .mask_chipsel = BIT(14), 79 .mask_chipsel = BIT(14),
87 .parts = davinci_nand_partitions, 80 .parts = davinci_nand_partitions,
88 .nr_parts = ARRAY_SIZE(davinci_nand_partitions), 81 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
89 .ecc_mode = NAND_ECC_HW_SYNDROME, 82 .ecc_mode = NAND_ECC_HW,
90 .options = NAND_USE_FLASH_BBT, 83 .options = NAND_USE_FLASH_BBT,
84 .ecc_bits = 4,
91}; 85};
92 86
93static struct resource davinci_nand_resources[] = { 87static struct resource davinci_nand_resources[] = {
@@ -344,7 +338,7 @@ static __init void dm355_evm_init(void)
344 gpio_request(2, "usb_id_toggle"); 338 gpio_request(2, "usb_id_toggle");
345 gpio_direction_output(2, USB_ID_VALUE); 339 gpio_direction_output(2, USB_ID_VALUE);
346 /* irlml6401 switches over 1A in under 8 msec */ 340 /* irlml6401 switches over 1A in under 8 msec */
347 setup_usb(500, 8); 341 davinci_setup_usb(1000, 8);
348 342
349 davinci_setup_mmc(0, &dm355evm_mmc_config); 343 davinci_setup_mmc(0, &dm355evm_mmc_config);
350 davinci_setup_mmc(1, &dm355evm_mmc_config); 344 davinci_setup_mmc(1, &dm355evm_mmc_config);
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 84ad5d161a8..21f32eb41e8 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -8,34 +8,27 @@
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/init.h> 11#include <linux/init.h>
13#include <linux/dma-mapping.h> 12#include <linux/err.h>
14#include <linux/platform_device.h> 13#include <linux/platform_device.h>
15#include <linux/mtd/mtd.h> 14#include <linux/mtd/mtd.h>
16#include <linux/mtd/partitions.h> 15#include <linux/mtd/partitions.h>
17#include <linux/mtd/nand.h> 16#include <linux/mtd/nand.h>
18#include <linux/i2c.h> 17#include <linux/i2c.h>
19#include <linux/io.h>
20#include <linux/gpio.h> 18#include <linux/gpio.h>
21#include <linux/clk.h> 19#include <linux/clk.h>
22#include <linux/spi/spi.h> 20#include <linux/spi/spi.h>
23#include <linux/spi/eeprom.h> 21#include <linux/spi/eeprom.h>
24 22
25#include <asm/setup.h>
26#include <asm/mach-types.h> 23#include <asm/mach-types.h>
27#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/flash.h>
30 25
31#include <mach/hardware.h>
32#include <mach/dm355.h> 26#include <mach/dm355.h>
33#include <mach/psc.h>
34#include <mach/common.h>
35#include <mach/i2c.h> 27#include <mach/i2c.h>
36#include <mach/serial.h> 28#include <mach/serial.h>
37#include <mach/nand.h> 29#include <mach/nand.h>
38#include <mach/mmc.h> 30#include <mach/mmc.h>
31#include <mach/usb.h>
39 32
40#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000 33#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
41#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 34#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
@@ -270,7 +263,7 @@ static __init void dm355_leopard_init(void)
270 gpio_request(2, "usb_id_toggle"); 263 gpio_request(2, "usb_id_toggle");
271 gpio_direction_output(2, USB_ID_VALUE); 264 gpio_direction_output(2, USB_ID_VALUE);
272 /* irlml6401 switches over 1A in under 8 msec */ 265 /* irlml6401 switches over 1A in under 8 msec */
273 setup_usb(500, 8); 266 davinci_setup_usb(1000, 8);
274 267
275 davinci_setup_mmc(0, &dm355leopard_mmc_config); 268 davinci_setup_mmc(0, &dm355leopard_mmc_config);
276 davinci_setup_mmc(1, &dm355leopard_mmc_config); 269 davinci_setup_mmc(1, &dm355leopard_mmc_config);
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 52dd8046b30..289fe1b7d25 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -13,9 +13,8 @@
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/init.h> 16#include <linux/init.h>
18#include <linux/dma-mapping.h> 17#include <linux/err.h>
19#include <linux/i2c.h> 18#include <linux/i2c.h>
20#include <linux/io.h> 19#include <linux/io.h>
21#include <linux/clk.h> 20#include <linux/clk.h>
@@ -24,20 +23,19 @@
24#include <linux/mtd/mtd.h> 23#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h> 24#include <linux/mtd/partitions.h>
26#include <linux/mtd/nand.h> 25#include <linux/mtd/nand.h>
27#include <asm/setup.h> 26#include <linux/input.h>
27
28#include <asm/mach-types.h> 28#include <asm/mach-types.h>
29#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
30#include <asm/mach/map.h> 30
31#include <mach/mux.h> 31#include <mach/mux.h>
32#include <mach/hardware.h>
33#include <mach/dm365.h> 32#include <mach/dm365.h>
34#include <mach/psc.h>
35#include <mach/common.h> 33#include <mach/common.h>
36#include <mach/i2c.h> 34#include <mach/i2c.h>
37#include <mach/serial.h> 35#include <mach/serial.h>
38#include <mach/mmc.h> 36#include <mach/mmc.h>
39#include <mach/nand.h> 37#include <mach/nand.h>
40 38#include <mach/keyscan.h>
41 39
42static inline int have_imager(void) 40static inline int have_imager(void)
43{ 41{
@@ -144,6 +142,7 @@ static struct davinci_nand_pdata davinci_nand_data = {
144 .nr_parts = ARRAY_SIZE(davinci_nand_partitions), 142 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
145 .ecc_mode = NAND_ECC_HW, 143 .ecc_mode = NAND_ECC_HW,
146 .options = NAND_USE_FLASH_BBT, 144 .options = NAND_USE_FLASH_BBT,
145 .ecc_bits = 4,
147}; 146};
148 147
149static struct resource davinci_nand_resources[] = { 148static struct resource davinci_nand_resources[] = {
@@ -176,11 +175,16 @@ static struct at24_platform_data eeprom_info = {
176 .context = (void *)0x7f00, 175 .context = (void *)0x7f00,
177}; 176};
178 177
178static struct snd_platform_data dm365_evm_snd_data;
179
179static struct i2c_board_info i2c_info[] = { 180static struct i2c_board_info i2c_info[] = {
180 { 181 {
181 I2C_BOARD_INFO("24c256", 0x50), 182 I2C_BOARD_INFO("24c256", 0x50),
182 .platform_data = &eeprom_info, 183 .platform_data = &eeprom_info,
183 }, 184 },
185 {
186 I2C_BOARD_INFO("tlv320aic3x", 0x18),
187 },
184}; 188};
185 189
186static struct davinci_i2c_platform_data i2c_pdata = { 190static struct davinci_i2c_platform_data i2c_pdata = {
@@ -188,6 +192,38 @@ static struct davinci_i2c_platform_data i2c_pdata = {
188 .bus_delay = 0 /* usec */, 192 .bus_delay = 0 /* usec */,
189}; 193};
190 194
195#ifdef CONFIG_KEYBOARD_DAVINCI
196static unsigned short dm365evm_keymap[] = {
197 KEY_KP2,
198 KEY_LEFT,
199 KEY_EXIT,
200 KEY_DOWN,
201 KEY_ENTER,
202 KEY_UP,
203 KEY_KP1,
204 KEY_RIGHT,
205 KEY_MENU,
206 KEY_RECORD,
207 KEY_REWIND,
208 KEY_KPMINUS,
209 KEY_STOP,
210 KEY_FASTFORWARD,
211 KEY_KPPLUS,
212 KEY_PLAYPAUSE,
213 0
214};
215
216static struct davinci_ks_platform_data dm365evm_ks_data = {
217 .keymap = dm365evm_keymap,
218 .keymapsize = ARRAY_SIZE(dm365evm_keymap),
219 .rep = 1,
220 /* Scan period = strobe + interval */
221 .strobe = 0x5,
222 .interval = 0x2,
223 .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
224};
225#endif
226
191static int cpld_mmc_get_cd(int module) 227static int cpld_mmc_get_cd(int module)
192{ 228{
193 if (!cpld) 229 if (!cpld)
@@ -472,6 +508,13 @@ static __init void dm365_evm_init(void)
472 508
473 /* maybe setup mmc1/etc ... _after_ mmc0 */ 509 /* maybe setup mmc1/etc ... _after_ mmc0 */
474 evm_init_cpld(); 510 evm_init_cpld();
511
512 dm365_init_asp(&dm365_evm_snd_data);
513 dm365_init_rtc();
514
515#ifdef CONFIG_KEYBOARD_DAVINCI
516 dm365_init_ks(&dm365evm_ks_data);
517#endif
475} 518}
476 519
477static __init void dm365_evm_irq_init(void) 520static __init void dm365_evm_irq_init(void)
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 1213a0087ad..fd0398bc6db 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -9,45 +9,34 @@
9 * or implied. 9 * or implied.
10 */ 10 */
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/init.h> 12#include <linux/init.h>
14#include <linux/dma-mapping.h> 13#include <linux/dma-mapping.h>
15#include <linux/platform_device.h> 14#include <linux/platform_device.h>
16#include <linux/gpio.h> 15#include <linux/gpio.h>
17#include <linux/leds.h>
18#include <linux/memory.h>
19
20#include <linux/i2c.h> 16#include <linux/i2c.h>
21#include <linux/i2c/pcf857x.h> 17#include <linux/i2c/pcf857x.h>
22#include <linux/i2c/at24.h> 18#include <linux/i2c/at24.h>
23#include <linux/etherdevice.h>
24#include <linux/mtd/mtd.h> 19#include <linux/mtd/mtd.h>
25#include <linux/mtd/nand.h> 20#include <linux/mtd/nand.h>
26#include <linux/mtd/partitions.h> 21#include <linux/mtd/partitions.h>
27#include <linux/mtd/physmap.h> 22#include <linux/mtd/physmap.h>
28#include <linux/io.h>
29#include <linux/phy.h> 23#include <linux/phy.h>
30#include <linux/clk.h> 24#include <linux/clk.h>
31#include <linux/videodev2.h> 25#include <linux/videodev2.h>
32 26
33#include <media/tvp514x.h> 27#include <media/tvp514x.h>
34 28
35#include <asm/setup.h>
36#include <asm/mach-types.h> 29#include <asm/mach-types.h>
37
38#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
39#include <asm/mach/map.h>
40#include <asm/mach/flash.h>
41 31
42#include <mach/dm644x.h> 32#include <mach/dm644x.h>
43#include <mach/common.h> 33#include <mach/common.h>
44#include <mach/i2c.h> 34#include <mach/i2c.h>
45#include <mach/serial.h> 35#include <mach/serial.h>
46#include <mach/mux.h> 36#include <mach/mux.h>
47#include <mach/psc.h>
48#include <mach/nand.h> 37#include <mach/nand.h>
49#include <mach/mmc.h> 38#include <mach/mmc.h>
50#include <mach/emac.h> 39#include <mach/usb.h>
51 40
52#define DM644X_EVM_PHY_MASK (0x2) 41#define DM644X_EVM_PHY_MASK (0x2)
53#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ 42#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
@@ -477,7 +466,7 @@ evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
477 /* irlml6401 switches over 1A, in under 8 msec; 466 /* irlml6401 switches over 1A, in under 8 msec;
478 * now it can be managed by nDRV_VBUS ... 467 * now it can be managed by nDRV_VBUS ...
479 */ 468 */
480 setup_usb(500, 8); 469 davinci_setup_usb(1000, 8);
481 470
482 return 0; 471 return 0;
483} 472}
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 24e0e13b149..8d0b0e01c59 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -17,38 +17,28 @@
17 **************************************************************************/ 17 **************************************************************************/
18 18
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/init.h> 20#include <linux/init.h>
22#include <linux/fs.h>
23#include <linux/major.h>
24#include <linux/root_dev.h>
25#include <linux/dma-mapping.h>
26#include <linux/serial.h>
27#include <linux/serial_8250.h>
28#include <linux/leds.h> 21#include <linux/leds.h>
29#include <linux/gpio.h> 22#include <linux/gpio.h>
30#include <linux/io.h>
31#include <linux/platform_device.h> 23#include <linux/platform_device.h>
32#include <linux/i2c.h> 24#include <linux/i2c.h>
33#include <linux/i2c/at24.h> 25#include <linux/i2c/at24.h>
34#include <linux/i2c/pcf857x.h> 26#include <linux/i2c/pcf857x.h>
35#include <linux/etherdevice.h>
36 27
37#include <media/tvp514x.h> 28#include <media/tvp514x.h>
38 29
39#include <asm/setup.h> 30#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h>
32#include <linux/mtd/partitions.h>
33
40#include <asm/mach-types.h> 34#include <asm/mach-types.h>
41#include <asm/mach/arch.h> 35#include <asm/mach/arch.h>
42#include <asm/mach/map.h>
43#include <asm/mach/flash.h>
44 36
45#include <mach/dm646x.h> 37#include <mach/dm646x.h>
46#include <mach/common.h> 38#include <mach/common.h>
47#include <mach/psc.h>
48#include <mach/serial.h> 39#include <mach/serial.h>
49#include <mach/i2c.h> 40#include <mach/i2c.h>
50#include <mach/mmc.h> 41#include <mach/nand.h>
51#include <mach/emac.h>
52 42
53#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ 43#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
54 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) 44 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
@@ -57,6 +47,11 @@
57#define HAS_ATA 0 47#define HAS_ATA 0
58#endif 48#endif
59 49
50#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000
51#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
52
53#define NAND_BLOCK_SIZE SZ_128K
54
60/* CPLD Register 0 bits to control ATA */ 55/* CPLD Register 0 bits to control ATA */
61#define DM646X_EVM_ATA_RST BIT(0) 56#define DM646X_EVM_ATA_RST BIT(0)
62#define DM646X_EVM_ATA_PWD BIT(1) 57#define DM646X_EVM_ATA_PWD BIT(1)
@@ -92,6 +87,63 @@ static struct davinci_uart_config uart_config __initdata = {
92 .enabled_uarts = (1 << 0), 87 .enabled_uarts = (1 << 0),
93}; 88};
94 89
90/* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
91 * and U-Boot environment this avoids dependency on any particular combination
92 * of UBL, U-Boot or flashing tools etc.
93 */
94static struct mtd_partition davinci_nand_partitions[] = {
95 {
96 /* UBL, U-Boot with environment */
97 .name = "bootloader",
98 .offset = MTDPART_OFS_APPEND,
99 .size = 16 * NAND_BLOCK_SIZE,
100 .mask_flags = MTD_WRITEABLE, /* force read-only */
101 }, {
102 .name = "kernel",
103 .offset = MTDPART_OFS_APPEND,
104 .size = SZ_4M,
105 .mask_flags = 0,
106 }, {
107 .name = "filesystem",
108 .offset = MTDPART_OFS_APPEND,
109 .size = MTDPART_SIZ_FULL,
110 .mask_flags = 0,
111 }
112};
113
114static struct davinci_nand_pdata davinci_nand_data = {
115 .mask_cle = 0x80000,
116 .mask_ale = 0x40000,
117 .parts = davinci_nand_partitions,
118 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
119 .ecc_mode = NAND_ECC_HW,
120 .options = 0,
121};
122
123static struct resource davinci_nand_resources[] = {
124 {
125 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
126 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
127 .flags = IORESOURCE_MEM,
128 }, {
129 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
130 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
131 .flags = IORESOURCE_MEM,
132 },
133};
134
135static struct platform_device davinci_nand_device = {
136 .name = "davinci_nand",
137 .id = 0,
138
139 .num_resources = ARRAY_SIZE(davinci_nand_resources),
140 .resource = davinci_nand_resources,
141
142 .dev = {
143 .platform_data = &davinci_nand_data,
144 },
145};
146
95/* CPLD Register 0 Client: used for I/O Control */ 147/* CPLD Register 0 Client: used for I/O Control */
96static int cpld_reg0_probe(struct i2c_client *client, 148static int cpld_reg0_probe(struct i2c_client *client,
97 const struct i2c_device_id *id) 149 const struct i2c_device_id *id)
@@ -142,7 +194,7 @@ static struct gpio_led evm_leds[] = {
142 { .name = "DS4", .active_low = 1, }, 194 { .name = "DS4", .active_low = 1, },
143}; 195};
144 196
145static __initconst struct gpio_led_platform_data evm_led_data = { 197static const struct gpio_led_platform_data evm_led_data = {
146 .num_leds = ARRAY_SIZE(evm_leds), 198 .num_leds = ARRAY_SIZE(evm_leds),
147 .leds = evm_leds, 199 .leds = evm_leds,
148}; 200};
@@ -647,6 +699,8 @@ static __init void evm_init(void)
647 dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); 699 dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
648 dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); 700 dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
649 701
702 platform_device_register(&davinci_nand_device);
703
650 if (HAS_ATA) 704 if (HAS_ATA)
651 dm646x_init_ide(); 705 dm646x_init_ide();
652 706
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
new file mode 100644
index 00000000000..bd9ca079b69
--- /dev/null
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -0,0 +1,323 @@
1/*
2 * Neuros Technologies OSD2 board support
3 *
4 * Modified from original 644X-EVM board support.
5 * 2008 (c) Neuros Technology, LLC.
6 * 2009 (c) Jorge Luis Zapata Muga <jorgeluis.zapata@gmail.com>
7 * 2009 (c) Andrey A. Porodko <Andrey.Porodko@gmail.com>
8 *
9 * The Neuros OSD 2.0 is the hardware component of the Neuros Open
10 * Internet Television Platform. Hardware is very close to TI
11 * DM644X-EVM board. It has:
12 * DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
13 * USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
14 * Additionaly realtime clock, IR remote control receiver,
15 * IR Blaster based on MSP430 (firmware although is different
16 * from used in DM644X-EVM), internal ATA-6 3.5” HDD drive
17 * with PATA interface, two muxed red-green leds.
18 *
19 * For more information please refer to
20 * http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
21 *
22 * This file is licensed under the terms of the GNU General Public
23 * License version 2. This program is licensed "as is" without any
24 * warranty of any kind, whether express or implied.
25 */
26#include <linux/platform_device.h>
27#include <linux/gpio.h>
28#include <linux/mtd/partitions.h>
29
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32
33#include <mach/dm644x.h>
34#include <mach/i2c.h>
35#include <mach/serial.h>
36#include <mach/mux.h>
37#include <mach/nand.h>
38#include <mach/mmc.h>
39#include <mach/usb.h>
40
41#define NEUROS_OSD2_PHY_MASK 0x2
42#define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
43
44#define DAVINCI_CFC_ATA_BASE 0x01C66000
45
46#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
47#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
48
49#define LXT971_PHY_ID 0x001378e2
50#define LXT971_PHY_MASK 0xfffffff0
51
52#define NTOSD2_AUDIOSOC_I2C_ADDR 0x18
53#define NTOSD2_MSP430_I2C_ADDR 0x59
54#define NTOSD2_MSP430_IRQ 2
55
56/* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA,
57 * 2048 blocks in the device, 64 pages per block, 2048 bytes per
58 * page.
59 */
60
61#define NAND_BLOCK_SIZE SZ_128K
62
63struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
64 {
65 /* UBL (a few copies) plus U-Boot */
66 .name = "bootloader",
67 .offset = 0,
68 .size = 15 * NAND_BLOCK_SIZE,
69 .mask_flags = MTD_WRITEABLE, /* force read-only */
70 }, {
71 /* U-Boot environment */
72 .name = "params",
73 .offset = MTDPART_OFS_APPEND,
74 .size = 1 * NAND_BLOCK_SIZE,
75 .mask_flags = 0,
76 }, {
77 /* Kernel */
78 .name = "kernel",
79 .offset = MTDPART_OFS_APPEND,
80 .size = SZ_4M,
81 .mask_flags = 0,
82 }, {
83 /* File System */
84 .name = "filesystem",
85 .offset = MTDPART_OFS_APPEND,
86 .size = MTDPART_SIZ_FULL,
87 .mask_flags = 0,
88 }
89 /* A few blocks at end hold a flash Bad Block Table. */
90};
91
92static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
93 .parts = davinci_ntosd2_nandflash_partition,
94 .nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
95 .ecc_mode = NAND_ECC_HW,
96 .options = NAND_USE_FLASH_BBT,
97};
98
99static struct resource davinci_ntosd2_nandflash_resource[] = {
100 {
101 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
102 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
103 .flags = IORESOURCE_MEM,
104 }, {
105 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
106 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
107 .flags = IORESOURCE_MEM,
108 },
109};
110
111static struct platform_device davinci_ntosd2_nandflash_device = {
112 .name = "davinci_nand",
113 .id = 0,
114 .dev = {
115 .platform_data = &davinci_ntosd2_nandflash_data,
116 },
117 .num_resources = ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
118 .resource = davinci_ntosd2_nandflash_resource,
119};
120
121static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
122
123static struct platform_device davinci_fb_device = {
124 .name = "davincifb",
125 .id = -1,
126 .dev = {
127 .dma_mask = &davinci_fb_dma_mask,
128 .coherent_dma_mask = DMA_BIT_MASK(32),
129 },
130 .num_resources = 0,
131};
132
133static struct resource ide_resources[] = {
134 {
135 .start = DAVINCI_CFC_ATA_BASE,
136 .end = DAVINCI_CFC_ATA_BASE + 0x7ff,
137 .flags = IORESOURCE_MEM,
138 },
139 {
140 .start = IRQ_IDE,
141 .end = IRQ_IDE,
142 .flags = IORESOURCE_IRQ,
143 },
144};
145
146static u64 ide_dma_mask = DMA_BIT_MASK(32);
147
148static struct platform_device ide_dev = {
149 .name = "palm_bk3710",
150 .id = -1,
151 .resource = ide_resources,
152 .num_resources = ARRAY_SIZE(ide_resources),
153 .dev = {
154 .dma_mask = &ide_dma_mask,
155 .coherent_dma_mask = DMA_BIT_MASK(32),
156 },
157};
158
159static struct snd_platform_data dm644x_ntosd2_snd_data;
160
161static struct gpio_led ntosd2_leds[] = {
162 { .name = "led1_green", .gpio = GPIO(10), },
163 { .name = "led1_red", .gpio = GPIO(11), },
164 { .name = "led2_green", .gpio = GPIO(12), },
165 { .name = "led2_red", .gpio = GPIO(13), },
166};
167
168static struct gpio_led_platform_data ntosd2_leds_data = {
169 .num_leds = ARRAY_SIZE(ntosd2_leds),
170 .leds = ntosd2_leds,
171};
172
173static struct platform_device ntosd2_leds_dev = {
174 .name = "leds-gpio",
175 .id = -1,
176 .dev = {
177 .platform_data = &ntosd2_leds_data,
178 },
179};
180
181
182static struct platform_device *davinci_ntosd2_devices[] __initdata = {
183 &davinci_fb_device,
184 &ntosd2_leds_dev,
185};
186
187static struct davinci_uart_config uart_config __initdata = {
188 .enabled_uarts = (1 << 0),
189};
190
191static void __init davinci_ntosd2_map_io(void)
192{
193 dm644x_init();
194}
195
196/*
197 I2C initialization
198*/
199static struct davinci_i2c_platform_data ntosd2_i2c_pdata = {
200 .bus_freq = 20 /* kHz */,
201 .bus_delay = 100 /* usec */,
202};
203
204static struct i2c_board_info __initdata ntosd2_i2c_info[] = {
205};
206
207static int ntosd2_init_i2c(void)
208{
209 int status;
210
211 davinci_init_i2c(&ntosd2_i2c_pdata);
212 status = gpio_request(NTOSD2_MSP430_IRQ, ntosd2_i2c_info[0].type);
213 if (status == 0) {
214 status = gpio_direction_input(NTOSD2_MSP430_IRQ);
215 if (status == 0) {
216 status = gpio_to_irq(NTOSD2_MSP430_IRQ);
217 if (status > 0) {
218 ntosd2_i2c_info[0].irq = status;
219 i2c_register_board_info(1,
220 ntosd2_i2c_info,
221 ARRAY_SIZE(ntosd2_i2c_info));
222 }
223 }
224 }
225 return status;
226}
227
228static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
229 .wires = 4,
230 .version = MMC_CTLR_VERSION_1
231};
232
233
234#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
235 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
236#define HAS_ATA 1
237#else
238#define HAS_ATA 0
239#endif
240
241#if defined(CONFIG_MTD_NAND_DAVINCI) || \
242 defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
243#define HAS_NAND 1
244#else
245#define HAS_NAND 0
246#endif
247
248static __init void davinci_ntosd2_init(void)
249{
250 struct clk *aemif_clk;
251 struct davinci_soc_info *soc_info = &davinci_soc_info;
252 int status;
253
254 aemif_clk = clk_get(NULL, "aemif");
255 clk_enable(aemif_clk);
256
257 if (HAS_ATA) {
258 if (HAS_NAND)
259 pr_warning("WARNING: both IDE and Flash are "
260 "enabled, but they share AEMIF pins.\n"
261 "\tDisable IDE for NAND/NOR support.\n");
262 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
263 davinci_cfg_reg(DM644X_ATAEN);
264 davinci_cfg_reg(DM644X_HDIREN);
265 platform_device_register(&ide_dev);
266 } else if (HAS_NAND) {
267 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
268 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
269
270 /* only one device will be jumpered and detected */
271 if (HAS_NAND)
272 platform_device_register(
273 &davinci_ntosd2_nandflash_device);
274 }
275
276 platform_add_devices(davinci_ntosd2_devices,
277 ARRAY_SIZE(davinci_ntosd2_devices));
278
279 /* Initialize I2C interface specific for this board */
280 status = ntosd2_init_i2c();
281 if (status < 0)
282 pr_warning("davinci_ntosd2_init: msp430 irq setup failed:"
283 " %d\n", status);
284
285 davinci_serial_init(&uart_config);
286 dm644x_init_asp(&dm644x_ntosd2_snd_data);
287
288 soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK;
289 soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY;
290
291 davinci_setup_usb(1000, 8);
292 /*
293 * Mux the pins to be GPIOs, VLYNQEN is already done at startup.
294 * The AEAWx are five new AEAW pins that can be muxed by separately.
295 * They are a bitmask for GPIO management. According TI
296 * documentation (http://www.ti.com/lit/gpn/tms320dm6446) to employ
297 * gpio(10,11,12,13) for leds any combination of bits works except
298 * four last. So we are to reset all five.
299 */
300 davinci_cfg_reg(DM644X_AEAW0);
301 davinci_cfg_reg(DM644X_AEAW1);
302 davinci_cfg_reg(DM644X_AEAW2);
303 davinci_cfg_reg(DM644X_AEAW3);
304 davinci_cfg_reg(DM644X_AEAW4);
305
306 davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
307}
308
309static __init void davinci_ntosd2_irq_init(void)
310{
311 davinci_irq_init();
312}
313
314MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
315 /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
316 .phys_io = IO_PHYS,
317 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
318 .boot_params = (DAVINCI_DDR_BASE + 0x100),
319 .map_io = davinci_ntosd2_map_io,
320 .init_irq = davinci_ntosd2_irq_init,
321 .timer = &davinci_timer,
322 .init_machine = davinci_ntosd2_init,
323MACHINE_END
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 7acdfd8ac07..08d373bfcc8 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -23,35 +23,24 @@
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */ 24 */
25 25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/init.h> 26#include <linux/init.h>
29#include <linux/dma-mapping.h>
30#include <linux/platform_device.h> 27#include <linux/platform_device.h>
31#include <linux/gpio.h>
32
33#include <linux/i2c.h> 28#include <linux/i2c.h>
34#include <linux/i2c/at24.h> 29#include <linux/i2c/at24.h>
35#include <linux/etherdevice.h>
36#include <linux/mtd/mtd.h> 30#include <linux/mtd/mtd.h>
37#include <linux/mtd/nand.h> 31#include <linux/mtd/nand.h>
38#include <linux/mtd/partitions.h> 32#include <linux/mtd/partitions.h>
39#include <linux/mtd/physmap.h>
40#include <linux/io.h>
41 33
42#include <asm/setup.h>
43#include <asm/mach-types.h> 34#include <asm/mach-types.h>
44
45#include <asm/mach/arch.h> 35#include <asm/mach/arch.h>
46#include <asm/mach/map.h>
47#include <asm/mach/flash.h> 36#include <asm/mach/flash.h>
48 37
49#include <mach/dm644x.h> 38#include <mach/dm644x.h>
50#include <mach/common.h> 39#include <mach/common.h>
51#include <mach/i2c.h> 40#include <mach/i2c.h>
52#include <mach/serial.h> 41#include <mach/serial.h>
53#include <mach/psc.h>
54#include <mach/mux.h> 42#include <mach/mux.h>
43#include <mach/usb.h>
55 44
56#define SFFSDR_PHY_MASK (0x2) 45#define SFFSDR_PHY_MASK (0x2)
57#define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ 46#define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
@@ -107,11 +96,6 @@ static struct platform_device davinci_sffsdr_nandflash_device = {
107 .resource = davinci_sffsdr_nandflash_resource, 96 .resource = davinci_sffsdr_nandflash_resource,
108}; 97};
109 98
110static struct emac_platform_data sffsdr_emac_pdata = {
111 .phy_mask = SFFSDR_PHY_MASK,
112 .mdio_max_freq = SFFSDR_MDIO_FREQUENCY,
113};
114
115static struct at24_platform_data eeprom_info = { 99static struct at24_platform_data eeprom_info = {
116 .byte_len = (64*1024) / 8, 100 .byte_len = (64*1024) / 8,
117 .page_size = 32, 101 .page_size = 32,
@@ -164,7 +148,7 @@ static __init void davinci_sffsdr_init(void)
164 davinci_serial_init(&uart_config); 148 davinci_serial_init(&uart_config);
165 soc_info->emac_pdata->phy_mask = SFFSDR_PHY_MASK; 149 soc_info->emac_pdata->phy_mask = SFFSDR_PHY_MASK;
166 soc_info->emac_pdata->mdio_max_freq = SFFSDR_MDIO_FREQUENCY; 150 soc_info->emac_pdata->mdio_max_freq = SFFSDR_MDIO_FREQUENCY;
167 setup_usb(0, 0); /* We support only peripheral mode. */ 151 davinci_setup_usb(0, 0); /* We support only peripheral mode. */
168 152
169 /* mux VLYNQ pins */ 153 /* mux VLYNQ pins */
170 davinci_cfg_reg(DM644X_VLYNQEN); 154 davinci_cfg_reg(DM644X_VLYNQEN);
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 83d54d50b5e..baece65cb9c 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -17,8 +17,8 @@
17#include <linux/clk.h> 17#include <linux/clk.h>
18#include <linux/err.h> 18#include <linux/err.h>
19#include <linux/mutex.h> 19#include <linux/mutex.h>
20#include <linux/platform_device.h>
21#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/delay.h>
22 22
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24 24
@@ -42,8 +42,7 @@ static void __clk_enable(struct clk *clk)
42 if (clk->parent) 42 if (clk->parent)
43 __clk_enable(clk->parent); 43 __clk_enable(clk->parent);
44 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) 44 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
45 davinci_psc_config(psc_domain(clk), clk->psc_ctlr, 45 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 1);
46 clk->lpsc, 1);
47} 46}
48 47
49static void __clk_disable(struct clk *clk) 48static void __clk_disable(struct clk *clk)
@@ -51,8 +50,7 @@ static void __clk_disable(struct clk *clk)
51 if (WARN_ON(clk->usecount == 0)) 50 if (WARN_ON(clk->usecount == 0))
52 return; 51 return;
53 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL)) 52 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
54 davinci_psc_config(psc_domain(clk), clk->psc_ctlr, 53 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 0);
55 clk->lpsc, 0);
56 if (clk->parent) 54 if (clk->parent)
57 __clk_disable(clk->parent); 55 __clk_disable(clk->parent);
58} 56}
@@ -99,20 +97,74 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
99 if (clk == NULL || IS_ERR(clk)) 97 if (clk == NULL || IS_ERR(clk))
100 return -EINVAL; 98 return -EINVAL;
101 99
100 if (clk->round_rate)
101 return clk->round_rate(clk, rate);
102
102 return clk->rate; 103 return clk->rate;
103} 104}
104EXPORT_SYMBOL(clk_round_rate); 105EXPORT_SYMBOL(clk_round_rate);
105 106
107/* Propagate rate to children */
108static void propagate_rate(struct clk *root)
109{
110 struct clk *clk;
111
112 list_for_each_entry(clk, &root->children, childnode) {
113 if (clk->recalc)
114 clk->rate = clk->recalc(clk);
115 propagate_rate(clk);
116 }
117}
118
106int clk_set_rate(struct clk *clk, unsigned long rate) 119int clk_set_rate(struct clk *clk, unsigned long rate)
107{ 120{
121 unsigned long flags;
122 int ret = -EINVAL;
123
108 if (clk == NULL || IS_ERR(clk)) 124 if (clk == NULL || IS_ERR(clk))
109 return -EINVAL; 125 return ret;
110 126
111 /* changing the clk rate is not supported */ 127 spin_lock_irqsave(&clockfw_lock, flags);
112 return -EINVAL; 128 if (clk->set_rate)
129 ret = clk->set_rate(clk, rate);
130 if (ret == 0) {
131 if (clk->recalc)
132 clk->rate = clk->recalc(clk);
133 propagate_rate(clk);
134 }
135 spin_unlock_irqrestore(&clockfw_lock, flags);
136
137 return ret;
113} 138}
114EXPORT_SYMBOL(clk_set_rate); 139EXPORT_SYMBOL(clk_set_rate);
115 140
141int clk_set_parent(struct clk *clk, struct clk *parent)
142{
143 unsigned long flags;
144
145 if (clk == NULL || IS_ERR(clk))
146 return -EINVAL;
147
148 /* Cannot change parent on enabled clock */
149 if (WARN_ON(clk->usecount))
150 return -EINVAL;
151
152 mutex_lock(&clocks_mutex);
153 clk->parent = parent;
154 list_del_init(&clk->childnode);
155 list_add(&clk->childnode, &clk->parent->children);
156 mutex_unlock(&clocks_mutex);
157
158 spin_lock_irqsave(&clockfw_lock, flags);
159 if (clk->recalc)
160 clk->rate = clk->recalc(clk);
161 propagate_rate(clk);
162 spin_unlock_irqrestore(&clockfw_lock, flags);
163
164 return 0;
165}
166EXPORT_SYMBOL(clk_set_parent);
167
116int clk_register(struct clk *clk) 168int clk_register(struct clk *clk)
117{ 169{
118 if (clk == NULL || IS_ERR(clk)) 170 if (clk == NULL || IS_ERR(clk))
@@ -123,16 +175,24 @@ int clk_register(struct clk *clk)
123 clk->name, clk->parent->name)) 175 clk->name, clk->parent->name))
124 return -EINVAL; 176 return -EINVAL;
125 177
178 INIT_LIST_HEAD(&clk->children);
179
126 mutex_lock(&clocks_mutex); 180 mutex_lock(&clocks_mutex);
127 list_add_tail(&clk->node, &clocks); 181 list_add_tail(&clk->node, &clocks);
182 if (clk->parent)
183 list_add_tail(&clk->childnode, &clk->parent->children);
128 mutex_unlock(&clocks_mutex); 184 mutex_unlock(&clocks_mutex);
129 185
130 /* If rate is already set, use it */ 186 /* If rate is already set, use it */
131 if (clk->rate) 187 if (clk->rate)
132 return 0; 188 return 0;
133 189
190 /* Else, see if there is a way to calculate it */
191 if (clk->recalc)
192 clk->rate = clk->recalc(clk);
193
134 /* Otherwise, default to parent rate */ 194 /* Otherwise, default to parent rate */
135 if (clk->parent) 195 else if (clk->parent)
136 clk->rate = clk->parent->rate; 196 clk->rate = clk->parent->rate;
137 197
138 return 0; 198 return 0;
@@ -146,6 +206,7 @@ void clk_unregister(struct clk *clk)
146 206
147 mutex_lock(&clocks_mutex); 207 mutex_lock(&clocks_mutex);
148 list_del(&clk->node); 208 list_del(&clk->node);
209 list_del(&clk->childnode);
149 mutex_unlock(&clocks_mutex); 210 mutex_unlock(&clocks_mutex);
150} 211}
151EXPORT_SYMBOL(clk_unregister); 212EXPORT_SYMBOL(clk_unregister);
@@ -166,11 +227,11 @@ static int __init clk_disable_unused(void)
166 continue; 227 continue;
167 228
168 /* ignore if in Disabled or SwRstDisable states */ 229 /* ignore if in Disabled or SwRstDisable states */
169 if (!davinci_psc_is_clk_active(ck->psc_ctlr, ck->lpsc)) 230 if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc))
170 continue; 231 continue;
171 232
172 pr_info("Clocks: disable unused %s\n", ck->name); 233 pr_info("Clocks: disable unused %s\n", ck->name);
173 davinci_psc_config(psc_domain(ck), ck->psc_ctlr, ck->lpsc, 0); 234 davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, 0);
174 } 235 }
175 spin_unlock_irq(&clockfw_lock); 236 spin_unlock_irq(&clockfw_lock);
176 237
@@ -179,50 +240,62 @@ static int __init clk_disable_unused(void)
179late_initcall(clk_disable_unused); 240late_initcall(clk_disable_unused);
180#endif 241#endif
181 242
182static void clk_sysclk_recalc(struct clk *clk) 243static unsigned long clk_sysclk_recalc(struct clk *clk)
183{ 244{
184 u32 v, plldiv; 245 u32 v, plldiv;
185 struct pll_data *pll; 246 struct pll_data *pll;
247 unsigned long rate = clk->rate;
186 248
187 /* If this is the PLL base clock, no more calculations needed */ 249 /* If this is the PLL base clock, no more calculations needed */
188 if (clk->pll_data) 250 if (clk->pll_data)
189 return; 251 return rate;
190 252
191 if (WARN_ON(!clk->parent)) 253 if (WARN_ON(!clk->parent))
192 return; 254 return rate;
193 255
194 clk->rate = clk->parent->rate; 256 rate = clk->parent->rate;
195 257
196 /* Otherwise, the parent must be a PLL */ 258 /* Otherwise, the parent must be a PLL */
197 if (WARN_ON(!clk->parent->pll_data)) 259 if (WARN_ON(!clk->parent->pll_data))
198 return; 260 return rate;
199 261
200 pll = clk->parent->pll_data; 262 pll = clk->parent->pll_data;
201 263
202 /* If pre-PLL, source clock is before the multiplier and divider(s) */ 264 /* If pre-PLL, source clock is before the multiplier and divider(s) */
203 if (clk->flags & PRE_PLL) 265 if (clk->flags & PRE_PLL)
204 clk->rate = pll->input_rate; 266 rate = pll->input_rate;
205 267
206 if (!clk->div_reg) 268 if (!clk->div_reg)
207 return; 269 return rate;
208 270
209 v = __raw_readl(pll->base + clk->div_reg); 271 v = __raw_readl(pll->base + clk->div_reg);
210 if (v & PLLDIV_EN) { 272 if (v & PLLDIV_EN) {
211 plldiv = (v & PLLDIV_RATIO_MASK) + 1; 273 plldiv = (v & PLLDIV_RATIO_MASK) + 1;
212 if (plldiv) 274 if (plldiv)
213 clk->rate /= plldiv; 275 rate /= plldiv;
214 } 276 }
277
278 return rate;
279}
280
281static unsigned long clk_leafclk_recalc(struct clk *clk)
282{
283 if (WARN_ON(!clk->parent))
284 return clk->rate;
285
286 return clk->parent->rate;
215} 287}
216 288
217static void __init clk_pll_init(struct clk *clk) 289static unsigned long clk_pllclk_recalc(struct clk *clk)
218{ 290{
219 u32 ctrl, mult = 1, prediv = 1, postdiv = 1; 291 u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
220 u8 bypass; 292 u8 bypass;
221 struct pll_data *pll = clk->pll_data; 293 struct pll_data *pll = clk->pll_data;
294 unsigned long rate = clk->rate;
222 295
223 pll->base = IO_ADDRESS(pll->phys_base); 296 pll->base = IO_ADDRESS(pll->phys_base);
224 ctrl = __raw_readl(pll->base + PLLCTL); 297 ctrl = __raw_readl(pll->base + PLLCTL);
225 clk->rate = pll->input_rate = clk->parent->rate; 298 rate = pll->input_rate = clk->parent->rate;
226 299
227 if (ctrl & PLLCTL_PLLEN) { 300 if (ctrl & PLLCTL_PLLEN) {
228 bypass = 0; 301 bypass = 0;
@@ -255,9 +328,9 @@ static void __init clk_pll_init(struct clk *clk)
255 } 328 }
256 329
257 if (!bypass) { 330 if (!bypass) {
258 clk->rate /= prediv; 331 rate /= prediv;
259 clk->rate *= mult; 332 rate *= mult;
260 clk->rate /= postdiv; 333 rate /= postdiv;
261 } 334 }
262 335
263 pr_debug("PLL%d: input = %lu MHz [ ", 336 pr_debug("PLL%d: input = %lu MHz [ ",
@@ -270,8 +343,90 @@ static void __init clk_pll_init(struct clk *clk)
270 pr_debug("* %d ", mult); 343 pr_debug("* %d ", mult);
271 if (postdiv > 1) 344 if (postdiv > 1)
272 pr_debug("/ %d ", postdiv); 345 pr_debug("/ %d ", postdiv);
273 pr_debug("] --> %lu MHz output.\n", clk->rate / 1000000); 346 pr_debug("] --> %lu MHz output.\n", rate / 1000000);
347
348 return rate;
349}
350
351/**
352 * davinci_set_pllrate - set the output rate of a given PLL.
353 *
354 * Note: Currently tested to work with OMAP-L138 only.
355 *
356 * @pll: pll whose rate needs to be changed.
357 * @prediv: The pre divider value. Passing 0 disables the pre-divider.
358 * @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
359 * @postdiv: The post divider value. Passing 0 disables the post-divider.
360 */
361int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
362 unsigned int mult, unsigned int postdiv)
363{
364 u32 ctrl;
365 unsigned int locktime;
366
367 if (pll->base == NULL)
368 return -EINVAL;
369
370 /*
371 * PLL lock time required per OMAP-L138 datasheet is
372 * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
373 * as 4 and OSCIN cycle as 25 MHz.
374 */
375 if (prediv) {
376 locktime = ((2000 * prediv) / 100);
377 prediv = (prediv - 1) | PLLDIV_EN;
378 } else {
379 locktime = 20;
380 }
381 if (postdiv)
382 postdiv = (postdiv - 1) | PLLDIV_EN;
383 if (mult)
384 mult = mult - 1;
385
386 ctrl = __raw_readl(pll->base + PLLCTL);
387
388 /* Switch the PLL to bypass mode */
389 ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
390 __raw_writel(ctrl, pll->base + PLLCTL);
391
392 /*
393 * Wait for 4 OSCIN/CLKIN cycles to ensure that the PLLC has switched
394 * to bypass mode. Delay of 1us ensures we are good for all > 4MHz
395 * OSCIN/CLKIN inputs. Typically the input is ~25MHz.
396 */
397 udelay(1);
398
399 /* Reset and enable PLL */
400 ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
401 __raw_writel(ctrl, pll->base + PLLCTL);
402
403 if (pll->flags & PLL_HAS_PREDIV)
404 __raw_writel(prediv, pll->base + PREDIV);
405
406 __raw_writel(mult, pll->base + PLLM);
407
408 if (pll->flags & PLL_HAS_POSTDIV)
409 __raw_writel(postdiv, pll->base + POSTDIV);
410
411 /*
412 * Wait for PLL to reset properly, OMAP-L138 datasheet says
413 * 'min' time = 125ns
414 */
415 udelay(1);
416
417 /* Bring PLL out of reset */
418 ctrl |= PLLCTL_PLLRST;
419 __raw_writel(ctrl, pll->base + PLLCTL);
420
421 udelay(locktime);
422
423 /* Remove PLL from bypass mode */
424 ctrl |= PLLCTL_PLLEN;
425 __raw_writel(ctrl, pll->base + PLLCTL);
426
427 return 0;
274} 428}
429EXPORT_SYMBOL(davinci_set_pllrate);
275 430
276int __init davinci_clk_init(struct davinci_clk *clocks) 431int __init davinci_clk_init(struct davinci_clk *clocks)
277 { 432 {
@@ -281,12 +436,23 @@ int __init davinci_clk_init(struct davinci_clk *clocks)
281 for (c = clocks; c->lk.clk; c++) { 436 for (c = clocks; c->lk.clk; c++) {
282 clk = c->lk.clk; 437 clk = c->lk.clk;
283 438
284 if (clk->pll_data) 439 if (!clk->recalc) {
285 clk_pll_init(clk); 440
441 /* Check if clock is a PLL */
442 if (clk->pll_data)
443 clk->recalc = clk_pllclk_recalc;
444
445 /* Else, if it is a PLL-derived clock */
446 else if (clk->flags & CLK_PLL)
447 clk->recalc = clk_sysclk_recalc;
448
449 /* Otherwise, it is a leaf clock (PSC clock) */
450 else if (clk->parent)
451 clk->recalc = clk_leafclk_recalc;
452 }
286 453
287 /* Calculate rates for PLL-derived clocks */ 454 if (clk->recalc)
288 else if (clk->flags & CLK_PLL) 455 clk->rate = clk->recalc(clk);
289 clk_sysclk_recalc(clk);
290 456
291 if (clk->lpsc) 457 if (clk->lpsc)
292 clk->flags |= CLK_PSC; 458 clk->flags |= CLK_PSC;
@@ -352,9 +518,8 @@ dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
352 /* REVISIT show device associations too */ 518 /* REVISIT show device associations too */
353 519
354 /* cost is now small, but not linear... */ 520 /* cost is now small, but not linear... */
355 list_for_each_entry(clk, &clocks, node) { 521 list_for_each_entry(clk, &parent->children, childnode) {
356 if (clk->parent == parent) 522 dump_clock(s, nest + NEST_DELTA, clk);
357 dump_clock(s, nest + NEST_DELTA, clk);
358 } 523 }
359} 524}
360 525
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 27233cb4a2f..c92d77a3008 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -22,6 +22,10 @@
22/* PLL/Reset register offsets */ 22/* PLL/Reset register offsets */
23#define PLLCTL 0x100 23#define PLLCTL 0x100
24#define PLLCTL_PLLEN BIT(0) 24#define PLLCTL_PLLEN BIT(0)
25#define PLLCTL_PLLPWRDN BIT(1)
26#define PLLCTL_PLLRST BIT(3)
27#define PLLCTL_PLLDIS BIT(4)
28#define PLLCTL_PLLENSRC BIT(5)
25#define PLLCTL_CLKMODE BIT(8) 29#define PLLCTL_CLKMODE BIT(8)
26 30
27#define PLLM 0x110 31#define PLLM 0x110
@@ -65,15 +69,20 @@ struct clk {
65 const char *name; 69 const char *name;
66 unsigned long rate; 70 unsigned long rate;
67 u8 usecount; 71 u8 usecount;
68 u8 flags;
69 u8 lpsc; 72 u8 lpsc;
70 u8 psc_ctlr; 73 u8 gpsc;
74 u32 flags;
71 struct clk *parent; 75 struct clk *parent;
76 struct list_head children; /* list of children */
77 struct list_head childnode; /* parent's child list node */
72 struct pll_data *pll_data; 78 struct pll_data *pll_data;
73 u32 div_reg; 79 u32 div_reg;
80 unsigned long (*recalc) (struct clk *);
81 int (*set_rate) (struct clk *clk, unsigned long rate);
82 int (*round_rate) (struct clk *clk, unsigned long rate);
74}; 83};
75 84
76/* Clock flags */ 85/* Clock flags: SoC-specific flags start at BIT(16) */
77#define ALWAYS_ENABLED BIT(1) 86#define ALWAYS_ENABLED BIT(1)
78#define CLK_PSC BIT(2) 87#define CLK_PSC BIT(2)
79#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */ 88#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
@@ -94,6 +103,8 @@ struct davinci_clk {
94 } 103 }
95 104
96int davinci_clk_init(struct davinci_clk *clocks); 105int davinci_clk_init(struct davinci_clk *clocks);
106int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
107 unsigned int mult, unsigned int postdiv);
97 108
98extern struct platform_device davinci_wdt_device; 109extern struct platform_device davinci_wdt_device;
99 110
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 61ede19c6b5..c2de94cde56 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -86,6 +86,8 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
86 dip = davinci_get_id(davinci_soc_info.jtag_id); 86 dip = davinci_get_id(davinci_soc_info.jtag_id);
87 if (!dip) { 87 if (!dip) {
88 ret = -EINVAL; 88 ret = -EINVAL;
89 pr_err("Unknown DaVinci JTAG ID 0x%x\n",
90 davinci_soc_info.jtag_id);
89 goto err; 91 goto err;
90 } 92 }
91 93
@@ -104,5 +106,5 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
104 return; 106 return;
105 107
106err: 108err:
107 pr_err("davinci_common_init: SoC Initialization failed\n"); 109 panic("davinci_common_init: SoC Initialization failed\n");
108} 110}
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index 96c8e97a7de..52b287cf3a4 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -10,9 +10,6 @@
10 */ 10 */
11 11
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/sched.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/irq.h> 13#include <linux/irq.h>
17#include <linux/io.h> 14#include <linux/io.h>
18 15
diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c
new file mode 100644
index 00000000000..d3fa6de1e20
--- /dev/null
+++ b/arch/arm/mach-davinci/cpufreq.c
@@ -0,0 +1,226 @@
1/*
2 * CPU frequency scaling for DaVinci
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Based on linux/arch/arm/plat-omap/cpu-omap.c. Original Copyright follows:
7 *
8 * Copyright (C) 2005 Nokia Corporation
9 * Written by Tony Lindgren <tony@atomide.com>
10 *
11 * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
12 *
13 * Copyright (C) 2007-2008 Texas Instruments, Inc.
14 * Updated to support OMAP3
15 * Rajendra Nayak <rnayak@ti.com>
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21#include <linux/types.h>
22#include <linux/cpufreq.h>
23#include <linux/init.h>
24#include <linux/err.h>
25#include <linux/clk.h>
26#include <linux/platform_device.h>
27
28#include <mach/hardware.h>
29#include <mach/cpufreq.h>
30#include <mach/common.h>
31
32#include "clock.h"
33
34struct davinci_cpufreq {
35 struct device *dev;
36 struct clk *armclk;
37};
38static struct davinci_cpufreq cpufreq;
39
40static int davinci_verify_speed(struct cpufreq_policy *policy)
41{
42 struct davinci_cpufreq_config *pdata = cpufreq.dev->platform_data;
43 struct cpufreq_frequency_table *freq_table = pdata->freq_table;
44 struct clk *armclk = cpufreq.armclk;
45
46 if (freq_table)
47 return cpufreq_frequency_table_verify(policy, freq_table);
48
49 if (policy->cpu)
50 return -EINVAL;
51
52 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
53 policy->cpuinfo.max_freq);
54
55 policy->min = clk_round_rate(armclk, policy->min * 1000) / 1000;
56 policy->max = clk_round_rate(armclk, policy->max * 1000) / 1000;
57 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
58 policy->cpuinfo.max_freq);
59 return 0;
60}
61
62static unsigned int davinci_getspeed(unsigned int cpu)
63{
64 if (cpu)
65 return 0;
66
67 return clk_get_rate(cpufreq.armclk) / 1000;
68}
69
70static int davinci_target(struct cpufreq_policy *policy,
71 unsigned int target_freq, unsigned int relation)
72{
73 int ret = 0;
74 unsigned int idx;
75 struct cpufreq_freqs freqs;
76 struct davinci_cpufreq_config *pdata = cpufreq.dev->platform_data;
77 struct clk *armclk = cpufreq.armclk;
78
79 /*
80 * Ensure desired rate is within allowed range. Some govenors
81 * (ondemand) will just pass target_freq=0 to get the minimum.
82 */
83 if (target_freq < policy->cpuinfo.min_freq)
84 target_freq = policy->cpuinfo.min_freq;
85 if (target_freq > policy->cpuinfo.max_freq)
86 target_freq = policy->cpuinfo.max_freq;
87
88 freqs.old = davinci_getspeed(0);
89 freqs.new = clk_round_rate(armclk, target_freq * 1000) / 1000;
90 freqs.cpu = 0;
91
92 if (freqs.old == freqs.new)
93 return ret;
94
95 cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER,
96 dev_driver_string(cpufreq.dev),
97 "transition: %u --> %u\n", freqs.old, freqs.new);
98
99 ret = cpufreq_frequency_table_target(policy, pdata->freq_table,
100 freqs.new, relation, &idx);
101 if (ret)
102 return -EINVAL;
103
104 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
105
106 /* if moving to higher frequency, up the voltage beforehand */
107 if (pdata->set_voltage && freqs.new > freqs.old)
108 pdata->set_voltage(idx);
109
110 ret = clk_set_rate(armclk, idx);
111
112 /* if moving to lower freq, lower the voltage after lowering freq */
113 if (pdata->set_voltage && freqs.new < freqs.old)
114 pdata->set_voltage(idx);
115
116 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
117
118 return ret;
119}
120
121static int __init davinci_cpu_init(struct cpufreq_policy *policy)
122{
123 int result = 0;
124 struct davinci_cpufreq_config *pdata = cpufreq.dev->platform_data;
125 struct cpufreq_frequency_table *freq_table = pdata->freq_table;
126
127 if (policy->cpu != 0)
128 return -EINVAL;
129
130 /* Finish platform specific initialization */
131 if (pdata->init) {
132 result = pdata->init();
133 if (result)
134 return result;
135 }
136
137 policy->cur = policy->min = policy->max = davinci_getspeed(0);
138
139 if (freq_table) {
140 result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
141 if (!result)
142 cpufreq_frequency_table_get_attr(freq_table,
143 policy->cpu);
144 } else {
145 policy->cpuinfo.min_freq = policy->min;
146 policy->cpuinfo.max_freq = policy->max;
147 }
148
149 policy->min = policy->cpuinfo.min_freq;
150 policy->max = policy->cpuinfo.max_freq;
151 policy->cur = davinci_getspeed(0);
152
153 /*
154 * Time measurement across the target() function yields ~1500-1800us
155 * time taken with no drivers on notification list.
156 * Setting the latency to 2000 us to accomodate addition of drivers
157 * to pre/post change notification list.
158 */
159 policy->cpuinfo.transition_latency = 2000 * 1000;
160 return 0;
161}
162
163static int davinci_cpu_exit(struct cpufreq_policy *policy)
164{
165 cpufreq_frequency_table_put_attr(policy->cpu);
166 return 0;
167}
168
169static struct freq_attr *davinci_cpufreq_attr[] = {
170 &cpufreq_freq_attr_scaling_available_freqs,
171 NULL,
172};
173
174static struct cpufreq_driver davinci_driver = {
175 .flags = CPUFREQ_STICKY,
176 .verify = davinci_verify_speed,
177 .target = davinci_target,
178 .get = davinci_getspeed,
179 .init = davinci_cpu_init,
180 .exit = davinci_cpu_exit,
181 .name = "davinci",
182 .attr = davinci_cpufreq_attr,
183};
184
185static int __init davinci_cpufreq_probe(struct platform_device *pdev)
186{
187 struct davinci_cpufreq_config *pdata = pdev->dev.platform_data;
188
189 if (!pdata)
190 return -EINVAL;
191 if (!pdata->freq_table)
192 return -EINVAL;
193
194 cpufreq.dev = &pdev->dev;
195
196 cpufreq.armclk = clk_get(NULL, "arm");
197 if (IS_ERR(cpufreq.armclk)) {
198 dev_err(cpufreq.dev, "Unable to get ARM clock\n");
199 return PTR_ERR(cpufreq.armclk);
200 }
201
202 return cpufreq_register_driver(&davinci_driver);
203}
204
205static int __exit davinci_cpufreq_remove(struct platform_device *pdev)
206{
207 clk_put(cpufreq.armclk);
208
209 return cpufreq_unregister_driver(&davinci_driver);
210}
211
212static struct platform_driver davinci_cpufreq_driver = {
213 .driver = {
214 .name = "cpufreq-davinci",
215 .owner = THIS_MODULE,
216 },
217 .remove = __exit_p(davinci_cpufreq_remove),
218};
219
220static int __init davinci_cpufreq_init(void)
221{
222 return platform_driver_probe(&davinci_cpufreq_driver,
223 davinci_cpufreq_probe);
224}
225late_initcall(davinci_cpufreq_init);
226
diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
new file mode 100644
index 00000000000..97a90f36fc9
--- /dev/null
+++ b/arch/arm/mach-davinci/cpuidle.c
@@ -0,0 +1,197 @@
1/*
2 * CPU idle for DaVinci SoCs
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
5 *
6 * Derived from Marvell Kirkwood CPU idle code
7 * (arch/arm/mach-kirkwood/cpuidle.c)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/cpuidle.h>
18#include <linux/io.h>
19#include <asm/proc-fns.h>
20
21#include <mach/cpuidle.h>
22
23#define DAVINCI_CPUIDLE_MAX_STATES 2
24
25struct davinci_ops {
26 void (*enter) (u32 flags);
27 void (*exit) (u32 flags);
28 u32 flags;
29};
30
31/* fields in davinci_ops.flags */
32#define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN BIT(0)
33
34static struct cpuidle_driver davinci_idle_driver = {
35 .name = "cpuidle-davinci",
36 .owner = THIS_MODULE,
37};
38
39static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
40static void __iomem *ddr2_reg_base;
41
42#define DDR2_SDRCR_OFFSET 0xc
43#define DDR2_SRPD_BIT BIT(23)
44#define DDR2_LPMODEN_BIT BIT(31)
45
46static void davinci_save_ddr_power(int enter, bool pdown)
47{
48 u32 val;
49
50 val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
51
52 if (enter) {
53 if (pdown)
54 val |= DDR2_SRPD_BIT;
55 else
56 val &= ~DDR2_SRPD_BIT;
57 val |= DDR2_LPMODEN_BIT;
58 } else {
59 val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
60 }
61
62 __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
63}
64
65static void davinci_c2state_enter(u32 flags)
66{
67 davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
68}
69
70static void davinci_c2state_exit(u32 flags)
71{
72 davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
73}
74
75static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
76 [1] = {
77 .enter = davinci_c2state_enter,
78 .exit = davinci_c2state_exit,
79 },
80};
81
82/* Actual code that puts the SoC in different idle states */
83static int davinci_enter_idle(struct cpuidle_device *dev,
84 struct cpuidle_state *state)
85{
86 struct davinci_ops *ops = cpuidle_get_statedata(state);
87 struct timeval before, after;
88 int idle_time;
89
90 local_irq_disable();
91 do_gettimeofday(&before);
92
93 if (ops && ops->enter)
94 ops->enter(ops->flags);
95 /* Wait for interrupt state */
96 cpu_do_idle();
97 if (ops && ops->exit)
98 ops->exit(ops->flags);
99
100 do_gettimeofday(&after);
101 local_irq_enable();
102 idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
103 (after.tv_usec - before.tv_usec);
104 return idle_time;
105}
106
107static int __init davinci_cpuidle_probe(struct platform_device *pdev)
108{
109 int ret;
110 struct cpuidle_device *device;
111 struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
112 struct resource *ddr2_regs;
113 resource_size_t len;
114
115 device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
116
117 if (!pdata) {
118 dev_err(&pdev->dev, "cannot get platform data\n");
119 return -ENOENT;
120 }
121
122 ddr2_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
123 if (!ddr2_regs) {
124 dev_err(&pdev->dev, "cannot get DDR2 controller register base");
125 return -ENODEV;
126 }
127
128 len = resource_size(ddr2_regs);
129
130 ddr2_regs = request_mem_region(ddr2_regs->start, len, ddr2_regs->name);
131 if (!ddr2_regs)
132 return -EBUSY;
133
134 ddr2_reg_base = ioremap(ddr2_regs->start, len);
135 if (!ddr2_reg_base) {
136 ret = -ENOMEM;
137 goto ioremap_fail;
138 }
139
140 ret = cpuidle_register_driver(&davinci_idle_driver);
141 if (ret) {
142 dev_err(&pdev->dev, "failed to register driver\n");
143 goto driver_register_fail;
144 }
145
146 /* Wait for interrupt state */
147 device->states[0].enter = davinci_enter_idle;
148 device->states[0].exit_latency = 1;
149 device->states[0].target_residency = 10000;
150 device->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
151 strcpy(device->states[0].name, "WFI");
152 strcpy(device->states[0].desc, "Wait for interrupt");
153
154 /* Wait for interrupt and DDR self refresh state */
155 device->states[1].enter = davinci_enter_idle;
156 device->states[1].exit_latency = 10;
157 device->states[1].target_residency = 10000;
158 device->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
159 strcpy(device->states[1].name, "DDR SR");
160 strcpy(device->states[1].desc, "WFI and DDR Self Refresh");
161 if (pdata->ddr2_pdown)
162 davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
163 cpuidle_set_statedata(&device->states[1], &davinci_states[1]);
164
165 device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
166
167 ret = cpuidle_register_device(device);
168 if (ret) {
169 dev_err(&pdev->dev, "failed to register device\n");
170 goto device_register_fail;
171 }
172
173 return 0;
174
175device_register_fail:
176 cpuidle_unregister_driver(&davinci_idle_driver);
177driver_register_fail:
178 iounmap(ddr2_reg_base);
179ioremap_fail:
180 release_mem_region(ddr2_regs->start, len);
181 return ret;
182}
183
184static struct platform_driver davinci_cpuidle_driver = {
185 .driver = {
186 .name = "cpuidle-davinci",
187 .owner = THIS_MODULE,
188 },
189};
190
191static int __init davinci_cpuidle_init(void)
192{
193 return platform_driver_probe(&davinci_cpuidle_driver,
194 davinci_cpuidle_probe);
195}
196device_initcall(davinci_cpuidle_init);
197
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 19b2748357f..b22b5cf0425 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -8,22 +8,17 @@
8 * is licensed "as is" without any warranty of any kind, whether express 8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 9 * or implied.
10 */ 10 */
11#include <linux/kernel.h>
12#include <linux/init.h> 11#include <linux/init.h>
13#include <linux/clk.h> 12#include <linux/clk.h>
14#include <linux/platform_device.h>
15 13
16#include <asm/mach/map.h> 14#include <asm/mach/map.h>
17 15
18#include <mach/clock.h>
19#include <mach/psc.h> 16#include <mach/psc.h>
20#include <mach/mux.h>
21#include <mach/irqs.h> 17#include <mach/irqs.h>
22#include <mach/cputype.h> 18#include <mach/cputype.h>
23#include <mach/common.h> 19#include <mach/common.h>
24#include <mach/time.h> 20#include <mach/time.h>
25#include <mach/da8xx.h> 21#include <mach/da8xx.h>
26#include <mach/asp.h>
27 22
28#include "clock.h" 23#include "clock.h"
29#include "mux.h" 24#include "mux.h"
@@ -193,14 +188,14 @@ static struct clk uart1_clk = {
193 .name = "uart1", 188 .name = "uart1",
194 .parent = &pll0_sysclk2, 189 .parent = &pll0_sysclk2,
195 .lpsc = DA8XX_LPSC1_UART1, 190 .lpsc = DA8XX_LPSC1_UART1,
196 .psc_ctlr = 1, 191 .gpsc = 1,
197}; 192};
198 193
199static struct clk uart2_clk = { 194static struct clk uart2_clk = {
200 .name = "uart2", 195 .name = "uart2",
201 .parent = &pll0_sysclk2, 196 .parent = &pll0_sysclk2,
202 .lpsc = DA8XX_LPSC1_UART2, 197 .lpsc = DA8XX_LPSC1_UART2,
203 .psc_ctlr = 1, 198 .gpsc = 1,
204}; 199};
205 200
206static struct clk spi0_clk = { 201static struct clk spi0_clk = {
@@ -213,98 +208,98 @@ static struct clk spi1_clk = {
213 .name = "spi1", 208 .name = "spi1",
214 .parent = &pll0_sysclk2, 209 .parent = &pll0_sysclk2,
215 .lpsc = DA8XX_LPSC1_SPI1, 210 .lpsc = DA8XX_LPSC1_SPI1,
216 .psc_ctlr = 1, 211 .gpsc = 1,
217}; 212};
218 213
219static struct clk ecap0_clk = { 214static struct clk ecap0_clk = {
220 .name = "ecap0", 215 .name = "ecap0",
221 .parent = &pll0_sysclk2, 216 .parent = &pll0_sysclk2,
222 .lpsc = DA8XX_LPSC1_ECAP, 217 .lpsc = DA8XX_LPSC1_ECAP,
223 .psc_ctlr = 1, 218 .gpsc = 1,
224}; 219};
225 220
226static struct clk ecap1_clk = { 221static struct clk ecap1_clk = {
227 .name = "ecap1", 222 .name = "ecap1",
228 .parent = &pll0_sysclk2, 223 .parent = &pll0_sysclk2,
229 .lpsc = DA8XX_LPSC1_ECAP, 224 .lpsc = DA8XX_LPSC1_ECAP,
230 .psc_ctlr = 1, 225 .gpsc = 1,
231}; 226};
232 227
233static struct clk ecap2_clk = { 228static struct clk ecap2_clk = {
234 .name = "ecap2", 229 .name = "ecap2",
235 .parent = &pll0_sysclk2, 230 .parent = &pll0_sysclk2,
236 .lpsc = DA8XX_LPSC1_ECAP, 231 .lpsc = DA8XX_LPSC1_ECAP,
237 .psc_ctlr = 1, 232 .gpsc = 1,
238}; 233};
239 234
240static struct clk pwm0_clk = { 235static struct clk pwm0_clk = {
241 .name = "pwm0", 236 .name = "pwm0",
242 .parent = &pll0_sysclk2, 237 .parent = &pll0_sysclk2,
243 .lpsc = DA8XX_LPSC1_PWM, 238 .lpsc = DA8XX_LPSC1_PWM,
244 .psc_ctlr = 1, 239 .gpsc = 1,
245}; 240};
246 241
247static struct clk pwm1_clk = { 242static struct clk pwm1_clk = {
248 .name = "pwm1", 243 .name = "pwm1",
249 .parent = &pll0_sysclk2, 244 .parent = &pll0_sysclk2,
250 .lpsc = DA8XX_LPSC1_PWM, 245 .lpsc = DA8XX_LPSC1_PWM,
251 .psc_ctlr = 1, 246 .gpsc = 1,
252}; 247};
253 248
254static struct clk pwm2_clk = { 249static struct clk pwm2_clk = {
255 .name = "pwm2", 250 .name = "pwm2",
256 .parent = &pll0_sysclk2, 251 .parent = &pll0_sysclk2,
257 .lpsc = DA8XX_LPSC1_PWM, 252 .lpsc = DA8XX_LPSC1_PWM,
258 .psc_ctlr = 1, 253 .gpsc = 1,
259}; 254};
260 255
261static struct clk eqep0_clk = { 256static struct clk eqep0_clk = {
262 .name = "eqep0", 257 .name = "eqep0",
263 .parent = &pll0_sysclk2, 258 .parent = &pll0_sysclk2,
264 .lpsc = DA830_LPSC1_EQEP, 259 .lpsc = DA830_LPSC1_EQEP,
265 .psc_ctlr = 1, 260 .gpsc = 1,
266}; 261};
267 262
268static struct clk eqep1_clk = { 263static struct clk eqep1_clk = {
269 .name = "eqep1", 264 .name = "eqep1",
270 .parent = &pll0_sysclk2, 265 .parent = &pll0_sysclk2,
271 .lpsc = DA830_LPSC1_EQEP, 266 .lpsc = DA830_LPSC1_EQEP,
272 .psc_ctlr = 1, 267 .gpsc = 1,
273}; 268};
274 269
275static struct clk lcdc_clk = { 270static struct clk lcdc_clk = {
276 .name = "lcdc", 271 .name = "lcdc",
277 .parent = &pll0_sysclk2, 272 .parent = &pll0_sysclk2,
278 .lpsc = DA8XX_LPSC1_LCDC, 273 .lpsc = DA8XX_LPSC1_LCDC,
279 .psc_ctlr = 1, 274 .gpsc = 1,
280}; 275};
281 276
282static struct clk mcasp0_clk = { 277static struct clk mcasp0_clk = {
283 .name = "mcasp0", 278 .name = "mcasp0",
284 .parent = &pll0_sysclk2, 279 .parent = &pll0_sysclk2,
285 .lpsc = DA8XX_LPSC1_McASP0, 280 .lpsc = DA8XX_LPSC1_McASP0,
286 .psc_ctlr = 1, 281 .gpsc = 1,
287}; 282};
288 283
289static struct clk mcasp1_clk = { 284static struct clk mcasp1_clk = {
290 .name = "mcasp1", 285 .name = "mcasp1",
291 .parent = &pll0_sysclk2, 286 .parent = &pll0_sysclk2,
292 .lpsc = DA830_LPSC1_McASP1, 287 .lpsc = DA830_LPSC1_McASP1,
293 .psc_ctlr = 1, 288 .gpsc = 1,
294}; 289};
295 290
296static struct clk mcasp2_clk = { 291static struct clk mcasp2_clk = {
297 .name = "mcasp2", 292 .name = "mcasp2",
298 .parent = &pll0_sysclk2, 293 .parent = &pll0_sysclk2,
299 .lpsc = DA830_LPSC1_McASP2, 294 .lpsc = DA830_LPSC1_McASP2,
300 .psc_ctlr = 1, 295 .gpsc = 1,
301}; 296};
302 297
303static struct clk usb20_clk = { 298static struct clk usb20_clk = {
304 .name = "usb20", 299 .name = "usb20",
305 .parent = &pll0_sysclk2, 300 .parent = &pll0_sysclk2,
306 .lpsc = DA8XX_LPSC1_USB20, 301 .lpsc = DA8XX_LPSC1_USB20,
307 .psc_ctlr = 1, 302 .gpsc = 1,
308}; 303};
309 304
310static struct clk aemif_clk = { 305static struct clk aemif_clk = {
@@ -332,36 +327,36 @@ static struct clk emac_clk = {
332 .name = "emac", 327 .name = "emac",
333 .parent = &pll0_sysclk4, 328 .parent = &pll0_sysclk4,
334 .lpsc = DA8XX_LPSC1_CPGMAC, 329 .lpsc = DA8XX_LPSC1_CPGMAC,
335 .psc_ctlr = 1, 330 .gpsc = 1,
336}; 331};
337 332
338static struct clk gpio_clk = { 333static struct clk gpio_clk = {
339 .name = "gpio", 334 .name = "gpio",
340 .parent = &pll0_sysclk4, 335 .parent = &pll0_sysclk4,
341 .lpsc = DA8XX_LPSC1_GPIO, 336 .lpsc = DA8XX_LPSC1_GPIO,
342 .psc_ctlr = 1, 337 .gpsc = 1,
343}; 338};
344 339
345static struct clk i2c1_clk = { 340static struct clk i2c1_clk = {
346 .name = "i2c1", 341 .name = "i2c1",
347 .parent = &pll0_sysclk4, 342 .parent = &pll0_sysclk4,
348 .lpsc = DA8XX_LPSC1_I2C, 343 .lpsc = DA8XX_LPSC1_I2C,
349 .psc_ctlr = 1, 344 .gpsc = 1,
350}; 345};
351 346
352static struct clk usb11_clk = { 347static struct clk usb11_clk = {
353 .name = "usb11", 348 .name = "usb11",
354 .parent = &pll0_sysclk4, 349 .parent = &pll0_sysclk4,
355 .lpsc = DA8XX_LPSC1_USB11, 350 .lpsc = DA8XX_LPSC1_USB11,
356 .psc_ctlr = 1, 351 .gpsc = 1,
357}; 352};
358 353
359static struct clk emif3_clk = { 354static struct clk emif3_clk = {
360 .name = "emif3", 355 .name = "emif3",
361 .parent = &pll0_sysclk5, 356 .parent = &pll0_sysclk5,
362 .lpsc = DA8XX_LPSC1_EMIF3C, 357 .lpsc = DA8XX_LPSC1_EMIF3C,
358 .gpsc = 1,
363 .flags = ALWAYS_ENABLED, 359 .flags = ALWAYS_ENABLED,
364 .psc_ctlr = 1,
365}; 360};
366 361
367static struct clk arm_clk = { 362static struct clk arm_clk = {
@@ -411,7 +406,7 @@ static struct davinci_clk da830_clks[] = {
411 CLK(NULL, "pwm2", &pwm2_clk), 406 CLK(NULL, "pwm2", &pwm2_clk),
412 CLK("eqep.0", NULL, &eqep0_clk), 407 CLK("eqep.0", NULL, &eqep0_clk),
413 CLK("eqep.1", NULL, &eqep1_clk), 408 CLK("eqep.1", NULL, &eqep1_clk),
414 CLK("da830_lcdc", NULL, &lcdc_clk), 409 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
415 CLK("davinci-mcasp.0", NULL, &mcasp0_clk), 410 CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
416 CLK("davinci-mcasp.1", NULL, &mcasp1_clk), 411 CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
417 CLK("davinci-mcasp.2", NULL, &mcasp2_clk), 412 CLK("davinci-mcasp.2", NULL, &mcasp2_clk),
@@ -1143,7 +1138,21 @@ static struct davinci_id da830_ids[] = {
1143 .part_no = 0xb7df, 1138 .part_no = 0xb7df,
1144 .manufacturer = 0x017, /* 0x02f >> 1 */ 1139 .manufacturer = 0x017, /* 0x02f >> 1 */
1145 .cpu_id = DAVINCI_CPU_ID_DA830, 1140 .cpu_id = DAVINCI_CPU_ID_DA830,
1146 .name = "da830/omap l137", 1141 .name = "da830/omap-l137 rev1.0",
1142 },
1143 {
1144 .variant = 0x8,
1145 .part_no = 0xb7df,
1146 .manufacturer = 0x017,
1147 .cpu_id = DAVINCI_CPU_ID_DA830,
1148 .name = "da830/omap-l137 rev1.1",
1149 },
1150 {
1151 .variant = 0x9,
1152 .part_no = 0xb7df,
1153 .manufacturer = 0x017,
1154 .cpu_id = DAVINCI_CPU_ID_DA830,
1155 .name = "da830/omap-l137 rev2.0",
1147 }, 1156 },
1148}; 1157};
1149 1158
@@ -1178,13 +1187,11 @@ static struct davinci_timer_info da830_timer_info = {
1178static struct davinci_soc_info davinci_soc_info_da830 = { 1187static struct davinci_soc_info davinci_soc_info_da830 = {
1179 .io_desc = da830_io_desc, 1188 .io_desc = da830_io_desc,
1180 .io_desc_num = ARRAY_SIZE(da830_io_desc), 1189 .io_desc_num = ARRAY_SIZE(da830_io_desc),
1181 .jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG),
1182 .ids = da830_ids, 1190 .ids = da830_ids,
1183 .ids_num = ARRAY_SIZE(da830_ids), 1191 .ids_num = ARRAY_SIZE(da830_ids),
1184 .cpu_clks = da830_clks, 1192 .cpu_clks = da830_clks,
1185 .psc_bases = da830_psc_bases, 1193 .psc_bases = da830_psc_bases,
1186 .psc_bases_num = ARRAY_SIZE(da830_psc_bases), 1194 .psc_bases_num = ARRAY_SIZE(da830_psc_bases),
1187 .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120),
1188 .pinmux_pins = da830_pins, 1195 .pinmux_pins = da830_pins,
1189 .pinmux_pins_num = ARRAY_SIZE(da830_pins), 1196 .pinmux_pins_num = ARRAY_SIZE(da830_pins),
1190 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, 1197 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
@@ -1201,5 +1208,13 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
1201 1208
1202void __init da830_init(void) 1209void __init da830_init(void)
1203{ 1210{
1211 da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K);
1212 if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module"))
1213 return;
1214
1215 davinci_soc_info_da830.jtag_id_base =
1216 DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG);
1217 davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG_VIRT(0x120);
1218
1204 davinci_common_init(&davinci_soc_info_da830); 1219 davinci_common_init(&davinci_soc_info_da830);
1205} 1220}
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 192d719a47d..717806c6cef 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -11,31 +11,41 @@
11 * is licensed "as is" without any warranty of any kind, whether express 11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied. 12 * or implied.
13 */ 13 */
14#include <linux/kernel.h>
15#include <linux/init.h> 14#include <linux/init.h>
16#include <linux/clk.h> 15#include <linux/clk.h>
17#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/cpufreq.h>
18#include <linux/regulator/consumer.h>
18 19
19#include <asm/mach/map.h> 20#include <asm/mach/map.h>
20 21
21#include <mach/clock.h>
22#include <mach/psc.h> 22#include <mach/psc.h>
23#include <mach/mux.h>
24#include <mach/irqs.h> 23#include <mach/irqs.h>
25#include <mach/cputype.h> 24#include <mach/cputype.h>
26#include <mach/common.h> 25#include <mach/common.h>
27#include <mach/time.h> 26#include <mach/time.h>
28#include <mach/da8xx.h> 27#include <mach/da8xx.h>
28#include <mach/cpufreq.h>
29 29
30#include "clock.h" 30#include "clock.h"
31#include "mux.h" 31#include "mux.h"
32 32
33/* SoC specific clock flags */
34#define DA850_CLK_ASYNC3 BIT(16)
35
33#define DA850_PLL1_BASE 0x01e1a000 36#define DA850_PLL1_BASE 0x01e1a000
34#define DA850_TIMER64P2_BASE 0x01f0c000 37#define DA850_TIMER64P2_BASE 0x01f0c000
35#define DA850_TIMER64P3_BASE 0x01f0d000 38#define DA850_TIMER64P3_BASE 0x01f0d000
36 39
37#define DA850_REF_FREQ 24000000 40#define DA850_REF_FREQ 24000000
38 41
42#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
43#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
44
45static int da850_set_armrate(struct clk *clk, unsigned long rate);
46static int da850_round_armrate(struct clk *clk, unsigned long rate);
47static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
48
39static struct pll_data pll0_data = { 49static struct pll_data pll0_data = {
40 .num = 1, 50 .num = 1,
41 .phys_base = DA8XX_PLL0_BASE, 51 .phys_base = DA8XX_PLL0_BASE,
@@ -52,6 +62,7 @@ static struct clk pll0_clk = {
52 .parent = &ref_clk, 62 .parent = &ref_clk,
53 .pll_data = &pll0_data, 63 .pll_data = &pll0_data,
54 .flags = CLK_PLL, 64 .flags = CLK_PLL,
65 .set_rate = da850_set_pll0rate,
55}; 66};
56 67
57static struct clk pll0_aux_clk = { 68static struct clk pll0_aux_clk = {
@@ -210,16 +221,16 @@ static struct clk tpcc1_clk = {
210 .name = "tpcc1", 221 .name = "tpcc1",
211 .parent = &pll0_sysclk2, 222 .parent = &pll0_sysclk2,
212 .lpsc = DA850_LPSC1_TPCC1, 223 .lpsc = DA850_LPSC1_TPCC1,
224 .gpsc = 1,
213 .flags = CLK_PSC | ALWAYS_ENABLED, 225 .flags = CLK_PSC | ALWAYS_ENABLED,
214 .psc_ctlr = 1,
215}; 226};
216 227
217static struct clk tptc2_clk = { 228static struct clk tptc2_clk = {
218 .name = "tptc2", 229 .name = "tptc2",
219 .parent = &pll0_sysclk2, 230 .parent = &pll0_sysclk2,
220 .lpsc = DA850_LPSC1_TPTC2, 231 .lpsc = DA850_LPSC1_TPTC2,
232 .gpsc = 1,
221 .flags = ALWAYS_ENABLED, 233 .flags = ALWAYS_ENABLED,
222 .psc_ctlr = 1,
223}; 234};
224 235
225static struct clk uart0_clk = { 236static struct clk uart0_clk = {
@@ -232,14 +243,16 @@ static struct clk uart1_clk = {
232 .name = "uart1", 243 .name = "uart1",
233 .parent = &pll0_sysclk2, 244 .parent = &pll0_sysclk2,
234 .lpsc = DA8XX_LPSC1_UART1, 245 .lpsc = DA8XX_LPSC1_UART1,
235 .psc_ctlr = 1, 246 .gpsc = 1,
247 .flags = DA850_CLK_ASYNC3,
236}; 248};
237 249
238static struct clk uart2_clk = { 250static struct clk uart2_clk = {
239 .name = "uart2", 251 .name = "uart2",
240 .parent = &pll0_sysclk2, 252 .parent = &pll0_sysclk2,
241 .lpsc = DA8XX_LPSC1_UART2, 253 .lpsc = DA8XX_LPSC1_UART2,
242 .psc_ctlr = 1, 254 .gpsc = 1,
255 .flags = DA850_CLK_ASYNC3,
243}; 256};
244 257
245static struct clk aintc_clk = { 258static struct clk aintc_clk = {
@@ -253,22 +266,22 @@ static struct clk gpio_clk = {
253 .name = "gpio", 266 .name = "gpio",
254 .parent = &pll0_sysclk4, 267 .parent = &pll0_sysclk4,
255 .lpsc = DA8XX_LPSC1_GPIO, 268 .lpsc = DA8XX_LPSC1_GPIO,
256 .psc_ctlr = 1, 269 .gpsc = 1,
257}; 270};
258 271
259static struct clk i2c1_clk = { 272static struct clk i2c1_clk = {
260 .name = "i2c1", 273 .name = "i2c1",
261 .parent = &pll0_sysclk4, 274 .parent = &pll0_sysclk4,
262 .lpsc = DA8XX_LPSC1_I2C, 275 .lpsc = DA8XX_LPSC1_I2C,
263 .psc_ctlr = 1, 276 .gpsc = 1,
264}; 277};
265 278
266static struct clk emif3_clk = { 279static struct clk emif3_clk = {
267 .name = "emif3", 280 .name = "emif3",
268 .parent = &pll0_sysclk5, 281 .parent = &pll0_sysclk5,
269 .lpsc = DA8XX_LPSC1_EMIF3C, 282 .lpsc = DA8XX_LPSC1_EMIF3C,
283 .gpsc = 1,
270 .flags = ALWAYS_ENABLED, 284 .flags = ALWAYS_ENABLED,
271 .psc_ctlr = 1,
272}; 285};
273 286
274static struct clk arm_clk = { 287static struct clk arm_clk = {
@@ -276,6 +289,8 @@ static struct clk arm_clk = {
276 .parent = &pll0_sysclk6, 289 .parent = &pll0_sysclk6,
277 .lpsc = DA8XX_LPSC0_ARM, 290 .lpsc = DA8XX_LPSC0_ARM,
278 .flags = ALWAYS_ENABLED, 291 .flags = ALWAYS_ENABLED,
292 .set_rate = da850_set_armrate,
293 .round_rate = da850_round_armrate,
279}; 294};
280 295
281static struct clk rmii_clk = { 296static struct clk rmii_clk = {
@@ -287,21 +302,22 @@ static struct clk emac_clk = {
287 .name = "emac", 302 .name = "emac",
288 .parent = &pll0_sysclk4, 303 .parent = &pll0_sysclk4,
289 .lpsc = DA8XX_LPSC1_CPGMAC, 304 .lpsc = DA8XX_LPSC1_CPGMAC,
290 .psc_ctlr = 1, 305 .gpsc = 1,
291}; 306};
292 307
293static struct clk mcasp_clk = { 308static struct clk mcasp_clk = {
294 .name = "mcasp", 309 .name = "mcasp",
295 .parent = &pll0_sysclk2, 310 .parent = &pll0_sysclk2,
296 .lpsc = DA8XX_LPSC1_McASP0, 311 .lpsc = DA8XX_LPSC1_McASP0,
297 .psc_ctlr = 1, 312 .gpsc = 1,
313 .flags = DA850_CLK_ASYNC3,
298}; 314};
299 315
300static struct clk lcdc_clk = { 316static struct clk lcdc_clk = {
301 .name = "lcdc", 317 .name = "lcdc",
302 .parent = &pll0_sysclk2, 318 .parent = &pll0_sysclk2,
303 .lpsc = DA8XX_LPSC1_LCDC, 319 .lpsc = DA8XX_LPSC1_LCDC,
304 .psc_ctlr = 1, 320 .gpsc = 1,
305}; 321};
306 322
307static struct clk mmcsd_clk = { 323static struct clk mmcsd_clk = {
@@ -404,6 +420,14 @@ static const struct mux_config da850_pins[] = {
404 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) 420 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
405 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false) 421 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
406 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false) 422 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
423 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
424 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
425 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
426 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
427 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
428 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
429 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
430 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
407 /* McASP function */ 431 /* McASP function */
408 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false) 432 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
409 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false) 433 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
@@ -506,8 +530,9 @@ static const struct mux_config da850_pins[] = {
506 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false) 530 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
507 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false) 531 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
508 /* GPIO function */ 532 /* GPIO function */
533 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
534 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
509 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false) 535 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
510 MUX_CFG(DA850, GPIO8_10, 18, 28, 15, 8, false)
511 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) 536 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
512 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) 537 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
513#endif 538#endif
@@ -547,6 +572,14 @@ const short da850_cpgmac_pins[] __initdata = {
547 -1 572 -1
548}; 573};
549 574
575const short da850_rmii_pins[] __initdata = {
576 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
577 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
578 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
579 DA850_MDIO_D,
580 -1
581};
582
550const short da850_mcasp_pins[] __initdata = { 583const short da850_mcasp_pins[] __initdata = {
551 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, 584 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
552 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE, 585 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
@@ -555,12 +588,11 @@ const short da850_mcasp_pins[] __initdata = {
555}; 588};
556 589
557const short da850_lcdcntl_pins[] __initdata = { 590const short da850_lcdcntl_pins[] __initdata = {
558 DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, DA850_LCD_D_4, 591 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
559 DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, DA850_LCD_D_8, 592 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
560 DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, DA850_LCD_D_12, 593 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
561 DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, DA850_LCD_PCLK, 594 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
562 DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, DA850_GPIO2_15, 595 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
563 DA850_GPIO8_10,
564 -1 596 -1
565}; 597};
566 598
@@ -790,16 +822,221 @@ static struct davinci_timer_info da850_timer_info = {
790 .clocksource_id = T0_TOP, 822 .clocksource_id = T0_TOP,
791}; 823};
792 824
825static void da850_set_async3_src(int pllnum)
826{
827 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
828 struct davinci_clk *c;
829 unsigned int v;
830 int ret;
831
832 for (c = da850_clks; c->lk.clk; c++) {
833 clk = c->lk.clk;
834 if (clk->flags & DA850_CLK_ASYNC3) {
835 ret = clk_set_parent(clk, newparent);
836 WARN(ret, "DA850: unable to re-parent clock %s",
837 clk->name);
838 }
839 }
840
841 v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
842 if (pllnum)
843 v |= CFGCHIP3_ASYNC3_CLKSRC;
844 else
845 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
846 __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
847}
848
849#ifdef CONFIG_CPU_FREQ
850/*
851 * Notes:
852 * According to the TRM, minimum PLLM results in maximum power savings.
853 * The OPP definitions below should keep the PLLM as low as possible.
854 *
855 * The output of the PLLM must be between 400 to 600 MHz.
856 * This rules out prediv of anything but divide-by-one for 24Mhz OSC input.
857 */
858struct da850_opp {
859 unsigned int freq; /* in KHz */
860 unsigned int prediv;
861 unsigned int mult;
862 unsigned int postdiv;
863 unsigned int cvdd_min; /* in uV */
864 unsigned int cvdd_max; /* in uV */
865};
866
867static const struct da850_opp da850_opp_300 = {
868 .freq = 300000,
869 .prediv = 1,
870 .mult = 25,
871 .postdiv = 2,
872 .cvdd_min = 1140000,
873 .cvdd_max = 1320000,
874};
875
876static const struct da850_opp da850_opp_200 = {
877 .freq = 200000,
878 .prediv = 1,
879 .mult = 25,
880 .postdiv = 3,
881 .cvdd_min = 1050000,
882 .cvdd_max = 1160000,
883};
884
885static const struct da850_opp da850_opp_96 = {
886 .freq = 96000,
887 .prediv = 1,
888 .mult = 20,
889 .postdiv = 5,
890 .cvdd_min = 950000,
891 .cvdd_max = 1050000,
892};
893
894#define OPP(freq) \
895 { \
896 .index = (unsigned int) &da850_opp_##freq, \
897 .frequency = freq * 1000, \
898 }
899
900static struct cpufreq_frequency_table da850_freq_table[] = {
901 OPP(300),
902 OPP(200),
903 OPP(96),
904 {
905 .index = 0,
906 .frequency = CPUFREQ_TABLE_END,
907 },
908};
909
910#ifdef CONFIG_REGULATOR
911static struct regulator *cvdd;
912
913static int da850_set_voltage(unsigned int index)
914{
915 struct da850_opp *opp;
916
917 if (!cvdd)
918 return -ENODEV;
919
920 opp = (struct da850_opp *) da850_freq_table[index].index;
921
922 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
923}
924
925static int da850_regulator_init(void)
926{
927 cvdd = regulator_get(NULL, "cvdd");
928 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
929 " voltage scaling unsupported\n")) {
930 return PTR_ERR(cvdd);
931 }
932
933 return 0;
934}
935#endif
936
937static struct davinci_cpufreq_config cpufreq_info = {
938 .freq_table = &da850_freq_table[0],
939#ifdef CONFIG_REGULATOR
940 .init = da850_regulator_init,
941 .set_voltage = da850_set_voltage,
942#endif
943};
944
945static struct platform_device da850_cpufreq_device = {
946 .name = "cpufreq-davinci",
947 .dev = {
948 .platform_data = &cpufreq_info,
949 },
950};
951
952int __init da850_register_cpufreq(void)
953{
954 return platform_device_register(&da850_cpufreq_device);
955}
956
957static int da850_round_armrate(struct clk *clk, unsigned long rate)
958{
959 int i, ret = 0, diff;
960 unsigned int best = (unsigned int) -1;
961
962 rate /= 1000; /* convert to kHz */
963
964 for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
965 diff = da850_freq_table[i].frequency - rate;
966 if (diff < 0)
967 diff = -diff;
968
969 if (diff < best) {
970 best = diff;
971 ret = da850_freq_table[i].frequency;
972 }
973 }
974
975 return ret * 1000;
976}
977
978static int da850_set_armrate(struct clk *clk, unsigned long index)
979{
980 struct clk *pllclk = &pll0_clk;
981
982 return clk_set_rate(pllclk, index);
983}
984
985static int da850_set_pll0rate(struct clk *clk, unsigned long index)
986{
987 unsigned int prediv, mult, postdiv;
988 struct da850_opp *opp;
989 struct pll_data *pll = clk->pll_data;
990 unsigned int v;
991 int ret;
992
993 opp = (struct da850_opp *) da850_freq_table[index].index;
994 prediv = opp->prediv;
995 mult = opp->mult;
996 postdiv = opp->postdiv;
997
998 /* Unlock writing to PLL registers */
999 v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
1000 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1001 __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
1002
1003 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1004 if (WARN_ON(ret))
1005 return ret;
1006
1007 return 0;
1008}
1009#else
1010int __init da850_register_cpufreq(void)
1011{
1012 return 0;
1013}
1014
1015static int da850_set_armrate(struct clk *clk, unsigned long rate)
1016{
1017 return -EINVAL;
1018}
1019
1020static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1021{
1022 return -EINVAL;
1023}
1024
1025static int da850_round_armrate(struct clk *clk, unsigned long rate)
1026{
1027 return clk->rate;
1028}
1029#endif
1030
1031
793static struct davinci_soc_info davinci_soc_info_da850 = { 1032static struct davinci_soc_info davinci_soc_info_da850 = {
794 .io_desc = da850_io_desc, 1033 .io_desc = da850_io_desc,
795 .io_desc_num = ARRAY_SIZE(da850_io_desc), 1034 .io_desc_num = ARRAY_SIZE(da850_io_desc),
796 .jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG),
797 .ids = da850_ids, 1035 .ids = da850_ids,
798 .ids_num = ARRAY_SIZE(da850_ids), 1036 .ids_num = ARRAY_SIZE(da850_ids),
799 .cpu_clks = da850_clks, 1037 .cpu_clks = da850_clks,
800 .psc_bases = da850_psc_bases, 1038 .psc_bases = da850_psc_bases,
801 .psc_bases_num = ARRAY_SIZE(da850_psc_bases), 1039 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
802 .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120),
803 .pinmux_pins = da850_pins, 1040 .pinmux_pins = da850_pins,
804 .pinmux_pins_num = ARRAY_SIZE(da850_pins), 1041 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
805 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, 1042 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
@@ -816,5 +1053,22 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
816 1053
817void __init da850_init(void) 1054void __init da850_init(void)
818{ 1055{
1056 da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K);
1057 if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module"))
1058 return;
1059
1060 davinci_soc_info_da850.jtag_id_base =
1061 DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG);
1062 davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG_VIRT(0x120);
1063
819 davinci_common_init(&davinci_soc_info_da850); 1064 davinci_common_init(&davinci_soc_info_da850);
1065
1066 /*
1067 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1068 * This helps keeping the peripherals on this domain insulated
1069 * from CPU frequency changes caused by DVFS. The firmware sets
1070 * both PLL0 and PLL1 to the same frequency so, there should not
1071 * be any noticible change even in non-DVFS use cases.
1072 */
1073 da850_set_async3_src(1);
820} 1074}
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 58ad5b66fd6..dd2d32c4ce8 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -10,8 +10,6 @@
10 * the Free Software Foundation; either version 2 of the License, or 10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version. 11 * (at your option) any later version.
12 */ 12 */
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h> 13#include <linux/init.h>
16#include <linux/platform_device.h> 14#include <linux/platform_device.h>
17#include <linux/dma-mapping.h> 15#include <linux/dma-mapping.h>
@@ -21,7 +19,7 @@
21#include <mach/common.h> 19#include <mach/common.h>
22#include <mach/time.h> 20#include <mach/time.h>
23#include <mach/da8xx.h> 21#include <mach/da8xx.h>
24#include <video/da8xx-fb.h> 22#include <mach/cpuidle.h>
25 23
26#include "clock.h" 24#include "clock.h"
27 25
@@ -30,6 +28,7 @@
30#define DA8XX_TPTC1_BASE 0x01c08400 28#define DA8XX_TPTC1_BASE 0x01c08400
31#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ 29#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
32#define DA8XX_I2C0_BASE 0x01c22000 30#define DA8XX_I2C0_BASE 0x01c22000
31#define DA8XX_RTC_BASE 0x01C23000
33#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 32#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
34#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 33#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
35#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 34#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
@@ -43,6 +42,8 @@
43#define DA8XX_MDIO_REG_OFFSET 0x4000 42#define DA8XX_MDIO_REG_OFFSET 0x4000
44#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K 43#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
45 44
45void __iomem *da8xx_syscfg_base;
46
46static struct plat_serial8250_port da8xx_serial_pdata[] = { 47static struct plat_serial8250_port da8xx_serial_pdata[] = {
47 { 48 {
48 .mapbase = DA8XX_UART0_BASE, 49 .mapbase = DA8XX_UART0_BASE,
@@ -282,6 +283,11 @@ static struct platform_device da8xx_emac_device = {
282 .resource = da8xx_emac_resources, 283 .resource = da8xx_emac_resources,
283}; 284};
284 285
286int __init da8xx_register_emac(void)
287{
288 return platform_device_register(&da8xx_emac_device);
289}
290
285static struct resource da830_mcasp1_resources[] = { 291static struct resource da830_mcasp1_resources[] = {
286 { 292 {
287 .name = "mcasp1", 293 .name = "mcasp1",
@@ -338,12 +344,7 @@ static struct platform_device da850_mcasp_device = {
338 .resource = da850_mcasp_resources, 344 .resource = da850_mcasp_resources,
339}; 345};
340 346
341int __init da8xx_register_emac(void) 347void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
342{
343 return platform_device_register(&da8xx_emac_device);
344}
345
346void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata)
347{ 348{
348 /* DA830/OMAP-L137 has 3 instances of McASP */ 349 /* DA830/OMAP-L137 has 3 instances of McASP */
349 if (cpu_is_davinci_da830() && id == 1) { 350 if (cpu_is_davinci_da830() && id == 1) {
@@ -379,10 +380,16 @@ static struct lcd_ctrl_config lcd_cfg = {
379 .raster_order = 0, 380 .raster_order = 0,
380}; 381};
381 382
382static struct da8xx_lcdc_platform_data da850_evm_lcdc_pdata = { 383struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
383 .manu_name = "sharp", 384 .manu_name = "sharp",
384 .controller_data = &lcd_cfg, 385 .controller_data = &lcd_cfg,
385 .type = "Sharp_LK043T1DG01", 386 .type = "Sharp_LCD035Q3DG01",
387};
388
389struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
390 .manu_name = "sharp",
391 .controller_data = &lcd_cfg,
392 .type = "Sharp_LK043T1DG01",
386}; 393};
387 394
388static struct resource da8xx_lcdc_resources[] = { 395static struct resource da8xx_lcdc_resources[] = {
@@ -398,19 +405,17 @@ static struct resource da8xx_lcdc_resources[] = {
398 }, 405 },
399}; 406};
400 407
401static struct platform_device da850_lcdc_device = { 408static struct platform_device da8xx_lcdc_device = {
402 .name = "da8xx_lcdc", 409 .name = "da8xx_lcdc",
403 .id = 0, 410 .id = 0,
404 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), 411 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
405 .resource = da8xx_lcdc_resources, 412 .resource = da8xx_lcdc_resources,
406 .dev = {
407 .platform_data = &da850_evm_lcdc_pdata,
408 }
409}; 413};
410 414
411int __init da8xx_register_lcdc(void) 415int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
412{ 416{
413 return platform_device_register(&da850_lcdc_device); 417 da8xx_lcdc_device.dev.platform_data = pdata;
418 return platform_device_register(&da8xx_lcdc_device);
414} 419}
415 420
416static struct resource da8xx_mmcsd0_resources[] = { 421static struct resource da8xx_mmcsd0_resources[] = {
@@ -448,3 +453,66 @@ int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
448 da8xx_mmcsd0_device.dev.platform_data = config; 453 da8xx_mmcsd0_device.dev.platform_data = config;
449 return platform_device_register(&da8xx_mmcsd0_device); 454 return platform_device_register(&da8xx_mmcsd0_device);
450} 455}
456
457static struct resource da8xx_rtc_resources[] = {
458 {
459 .start = DA8XX_RTC_BASE,
460 .end = DA8XX_RTC_BASE + SZ_4K - 1,
461 .flags = IORESOURCE_MEM,
462 },
463 { /* timer irq */
464 .start = IRQ_DA8XX_RTC,
465 .end = IRQ_DA8XX_RTC,
466 .flags = IORESOURCE_IRQ,
467 },
468 { /* alarm irq */
469 .start = IRQ_DA8XX_RTC,
470 .end = IRQ_DA8XX_RTC,
471 .flags = IORESOURCE_IRQ,
472 },
473};
474
475static struct platform_device da8xx_rtc_device = {
476 .name = "omap_rtc",
477 .id = -1,
478 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
479 .resource = da8xx_rtc_resources,
480};
481
482int da8xx_register_rtc(void)
483{
484 /* Unlock the rtc's registers */
485 __raw_writel(0x83e70b13, IO_ADDRESS(DA8XX_RTC_BASE + 0x6c));
486 __raw_writel(0x95a4f1e0, IO_ADDRESS(DA8XX_RTC_BASE + 0x70));
487
488 return platform_device_register(&da8xx_rtc_device);
489}
490
491static struct resource da8xx_cpuidle_resources[] = {
492 {
493 .start = DA8XX_DDR2_CTL_BASE,
494 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
495 .flags = IORESOURCE_MEM,
496 },
497};
498
499/* DA8XX devices support DDR2 power down */
500static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
501 .ddr2_pdown = 1,
502};
503
504
505static struct platform_device da8xx_cpuidle_device = {
506 .name = "cpuidle-davinci",
507 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
508 .resource = da8xx_cpuidle_resources,
509 .dev = {
510 .platform_data = &da8xx_cpuidle_pdata,
511 },
512};
513
514int __init da8xx_register_cpuidle(void)
515{
516 return platform_device_register(&da8xx_cpuidle_device);
517}
518
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index a55b650db71..147949650c2 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -9,15 +9,11 @@
9 * (at your option) any later version. 9 * (at your option) any later version.
10 */ 10 */
11 11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/init.h> 12#include <linux/init.h>
15#include <linux/platform_device.h> 13#include <linux/platform_device.h>
16#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
17#include <linux/io.h> 15#include <linux/io.h>
18 16
19#include <asm/mach/map.h>
20
21#include <mach/hardware.h> 17#include <mach/hardware.h>
22#include <mach/i2c.h> 18#include <mach/i2c.h>
23#include <mach/irqs.h> 19#include <mach/irqs.h>
@@ -177,7 +173,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
177 mmcsd1_resources[0].start = DM365_MMCSD1_BASE; 173 mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
178 mmcsd1_resources[0].end = DM365_MMCSD1_BASE + 174 mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
179 SZ_4K - 1; 175 SZ_4K - 1;
180 mmcsd0_resources[2].start = IRQ_DM365_SDIOINT1; 176 mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1;
181 } else 177 } else
182 break; 178 break;
183 179
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 059670018af..dedf4d4f3a2 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -8,7 +8,6 @@
8 * is licensed "as is" without any warranty of any kind, whether express 8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 9 * or implied.
10 */ 10 */
11#include <linux/kernel.h>
12#include <linux/init.h> 11#include <linux/init.h>
13#include <linux/clk.h> 12#include <linux/clk.h>
14#include <linux/serial_8250.h> 13#include <linux/serial_8250.h>
@@ -21,7 +20,6 @@
21#include <asm/mach/map.h> 20#include <asm/mach/map.h>
22 21
23#include <mach/dm355.h> 22#include <mach/dm355.h>
24#include <mach/clock.h>
25#include <mach/cputype.h> 23#include <mach/cputype.h>
26#include <mach/edma.h> 24#include <mach/edma.h>
27#include <mach/psc.h> 25#include <mach/psc.h>
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index e8151743470..2ec619ec165 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -12,7 +12,6 @@
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15#include <linux/kernel.h>
16#include <linux/init.h> 15#include <linux/init.h>
17#include <linux/clk.h> 16#include <linux/clk.h>
18#include <linux/serial_8250.h> 17#include <linux/serial_8250.h>
@@ -23,7 +22,6 @@
23#include <asm/mach/map.h> 22#include <asm/mach/map.h>
24 23
25#include <mach/dm365.h> 24#include <mach/dm365.h>
26#include <mach/clock.h>
27#include <mach/cputype.h> 25#include <mach/cputype.h>
28#include <mach/edma.h> 26#include <mach/edma.h>
29#include <mach/psc.h> 27#include <mach/psc.h>
@@ -32,6 +30,8 @@
32#include <mach/time.h> 30#include <mach/time.h>
33#include <mach/serial.h> 31#include <mach/serial.h>
34#include <mach/common.h> 32#include <mach/common.h>
33#include <mach/asp.h>
34#include <mach/keyscan.h>
35 35
36#include "clock.h" 36#include "clock.h"
37#include "mux.h" 37#include "mux.h"
@@ -369,7 +369,7 @@ static struct clk timer3_clk = {
369 369
370static struct clk usb_clk = { 370static struct clk usb_clk = {
371 .name = "usb", 371 .name = "usb",
372 .parent = &pll2_sysclk1, 372 .parent = &pll1_aux_clk,
373 .lpsc = DAVINCI_LPSC_USB, 373 .lpsc = DAVINCI_LPSC_USB,
374}; 374};
375 375
@@ -456,7 +456,7 @@ static struct davinci_clk dm365_clks[] = {
456 CLK(NULL, "usb", &usb_clk), 456 CLK(NULL, "usb", &usb_clk),
457 CLK("davinci_emac.1", NULL, &emac_clk), 457 CLK("davinci_emac.1", NULL, &emac_clk),
458 CLK("voice_codec", NULL, &voicecodec_clk), 458 CLK("voice_codec", NULL, &voicecodec_clk),
459 CLK("soc-audio.0", NULL, &asp0_clk), 459 CLK("davinci-asp.0", NULL, &asp0_clk),
460 CLK(NULL, "rto", &rto_clk), 460 CLK(NULL, "rto", &rto_clk),
461 CLK(NULL, "mjcp", &mjcp_clk), 461 CLK(NULL, "mjcp", &mjcp_clk),
462 CLK(NULL, NULL, NULL), 462 CLK(NULL, NULL, NULL),
@@ -531,7 +531,7 @@ MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
531MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false) 531MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
532MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false) 532MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
533 533
534MUX_CFG(DM365, KEYPAD, 2, 0, 0x3f, 0x3f, false) 534MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
535 535
536MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false) 536MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
537MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false) 537MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
@@ -603,6 +603,9 @@ INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
603INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false) 603INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
604INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false) 604INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
605INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false) 605INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
606
607EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
608EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
606#endif 609#endif
607}; 610};
608 611
@@ -696,6 +699,7 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
696 [IRQ_I2C] = 3, 699 [IRQ_I2C] = 3,
697 [IRQ_UARTINT0] = 3, 700 [IRQ_UARTINT0] = 3,
698 [IRQ_UARTINT1] = 3, 701 [IRQ_UARTINT1] = 3,
702 [IRQ_DM365_RTCINT] = 3,
699 [IRQ_DM365_SPIINT0_0] = 3, 703 [IRQ_DM365_SPIINT0_0] = 3,
700 [IRQ_DM365_SPIINT3_0] = 3, 704 [IRQ_DM365_SPIINT3_0] = 3,
701 [IRQ_DM365_GPIO0] = 3, 705 [IRQ_DM365_GPIO0] = 3,
@@ -806,6 +810,50 @@ static struct platform_device dm365_edma_device = {
806 .resource = edma_resources, 810 .resource = edma_resources,
807}; 811};
808 812
813static struct resource dm365_asp_resources[] = {
814 {
815 .start = DAVINCI_DM365_ASP0_BASE,
816 .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
817 .flags = IORESOURCE_MEM,
818 },
819 {
820 .start = DAVINCI_DMA_ASP0_TX,
821 .end = DAVINCI_DMA_ASP0_TX,
822 .flags = IORESOURCE_DMA,
823 },
824 {
825 .start = DAVINCI_DMA_ASP0_RX,
826 .end = DAVINCI_DMA_ASP0_RX,
827 .flags = IORESOURCE_DMA,
828 },
829};
830
831static struct platform_device dm365_asp_device = {
832 .name = "davinci-asp",
833 .id = 0,
834 .num_resources = ARRAY_SIZE(dm365_asp_resources),
835 .resource = dm365_asp_resources,
836};
837
838static struct resource dm365_rtc_resources[] = {
839 {
840 .start = DM365_RTC_BASE,
841 .end = DM365_RTC_BASE + SZ_1K - 1,
842 .flags = IORESOURCE_MEM,
843 },
844 {
845 .start = IRQ_DM365_RTCINT,
846 .flags = IORESOURCE_IRQ,
847 },
848};
849
850static struct platform_device dm365_rtc_device = {
851 .name = "rtc_davinci",
852 .id = 0,
853 .num_resources = ARRAY_SIZE(dm365_rtc_resources),
854 .resource = dm365_rtc_resources,
855};
856
809static struct map_desc dm365_io_desc[] = { 857static struct map_desc dm365_io_desc[] = {
810 { 858 {
811 .virtual = IO_VIRT, 859 .virtual = IO_VIRT,
@@ -822,6 +870,28 @@ static struct map_desc dm365_io_desc[] = {
822 }, 870 },
823}; 871};
824 872
873static struct resource dm365_ks_resources[] = {
874 {
875 /* registers */
876 .start = DM365_KEYSCAN_BASE,
877 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
878 .flags = IORESOURCE_MEM,
879 },
880 {
881 /* interrupt */
882 .start = IRQ_DM365_KEYINT,
883 .end = IRQ_DM365_KEYINT,
884 .flags = IORESOURCE_IRQ,
885 },
886};
887
888static struct platform_device dm365_ks_device = {
889 .name = "davinci_keyscan",
890 .id = 0,
891 .num_resources = ARRAY_SIZE(dm365_ks_resources),
892 .resource = dm365_ks_resources,
893};
894
825/* Contents of JTAG ID register used to identify exact cpu type */ 895/* Contents of JTAG ID register used to identify exact cpu type */
826static struct davinci_id dm365_ids[] = { 896static struct davinci_id dm365_ids[] = {
827 { 897 {
@@ -907,6 +977,33 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
907 .sram_len = SZ_32K, 977 .sram_len = SZ_32K,
908}; 978};
909 979
980void __init dm365_init_asp(struct snd_platform_data *pdata)
981{
982 davinci_cfg_reg(DM365_MCBSP0_BDX);
983 davinci_cfg_reg(DM365_MCBSP0_X);
984 davinci_cfg_reg(DM365_MCBSP0_BFSX);
985 davinci_cfg_reg(DM365_MCBSP0_BDR);
986 davinci_cfg_reg(DM365_MCBSP0_R);
987 davinci_cfg_reg(DM365_MCBSP0_BFSR);
988 davinci_cfg_reg(DM365_EVT2_ASP_TX);
989 davinci_cfg_reg(DM365_EVT3_ASP_RX);
990 dm365_asp_device.dev.platform_data = pdata;
991 platform_device_register(&dm365_asp_device);
992}
993
994void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
995{
996 davinci_cfg_reg(DM365_KEYSCAN);
997 dm365_ks_device.dev.platform_data = pdata;
998 platform_device_register(&dm365_ks_device);
999}
1000
1001void __init dm365_init_rtc(void)
1002{
1003 davinci_cfg_reg(DM365_INT_PRTCSS);
1004 platform_device_register(&dm365_rtc_device);
1005}
1006
910void __init dm365_init(void) 1007void __init dm365_init(void)
911{ 1008{
912 davinci_common_init(&davinci_soc_info_dm365); 1009 davinci_common_init(&davinci_soc_info_dm365);
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index d6e0fa5a8d8..2cd008156de 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -8,7 +8,6 @@
8 * is licensed "as is" without any warranty of any kind, whether express 8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 9 * or implied.
10 */ 10 */
11#include <linux/kernel.h>
12#include <linux/init.h> 11#include <linux/init.h>
13#include <linux/clk.h> 12#include <linux/clk.h>
14#include <linux/serial_8250.h> 13#include <linux/serial_8250.h>
@@ -18,7 +17,6 @@
18#include <asm/mach/map.h> 17#include <asm/mach/map.h>
19 18
20#include <mach/dm644x.h> 19#include <mach/dm644x.h>
21#include <mach/clock.h>
22#include <mach/cputype.h> 20#include <mach/cputype.h>
23#include <mach/edma.h> 21#include <mach/edma.h>
24#include <mach/irqs.h> 22#include <mach/irqs.h>
@@ -370,6 +368,11 @@ MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
370MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true) 368MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
371 369
372MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true) 370MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
371MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
372MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
373MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
374MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
375MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
373 376
374MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false) 377MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
375 378
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 0976049c7b3..829a44bcf79 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -8,7 +8,6 @@
8 * is licensed "as is" without any warranty of any kind, whether express 8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 9 * or implied.
10 */ 10 */
11#include <linux/kernel.h>
12#include <linux/init.h> 11#include <linux/init.h>
13#include <linux/clk.h> 12#include <linux/clk.h>
14#include <linux/serial_8250.h> 13#include <linux/serial_8250.h>
@@ -18,7 +17,6 @@
18#include <asm/mach/map.h> 17#include <asm/mach/map.h>
19 18
20#include <mach/dm646x.h> 19#include <mach/dm646x.h>
21#include <mach/clock.h>
22#include <mach/cputype.h> 20#include <mach/cputype.h>
23#include <mach/edma.h> 21#include <mach/edma.h>
24#include <mach/irqs.h> 22#include <mach/irqs.h>
@@ -789,7 +787,14 @@ static struct davinci_id dm646x_ids[] = {
789 .part_no = 0xb770, 787 .part_no = 0xb770,
790 .manufacturer = 0x017, 788 .manufacturer = 0x017,
791 .cpu_id = DAVINCI_CPU_ID_DM6467, 789 .cpu_id = DAVINCI_CPU_ID_DM6467,
792 .name = "dm6467", 790 .name = "dm6467_rev1.x",
791 },
792 {
793 .variant = 0x1,
794 .part_no = 0xb770,
795 .manufacturer = 0x017,
796 .cpu_id = DAVINCI_CPU_ID_DM6467,
797 .name = "dm6467_rev3.x",
793 }, 798 },
794}; 799};
795 800
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index f2e57d27295..648fbb760ae 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -18,22 +18,13 @@
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */ 19 */
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/sched.h>
22#include <linux/init.h> 21#include <linux/init.h>
23#include <linux/module.h> 22#include <linux/module.h>
24#include <linux/interrupt.h> 23#include <linux/interrupt.h>
25#include <linux/platform_device.h> 24#include <linux/platform_device.h>
26#include <linux/spinlock.h>
27#include <linux/compiler.h>
28#include <linux/io.h> 25#include <linux/io.h>
29 26
30#include <mach/cputype.h>
31#include <mach/memory.h>
32#include <mach/hardware.h>
33#include <mach/irqs.h>
34#include <mach/edma.h> 27#include <mach/edma.h>
35#include <mach/mux.h>
36
37 28
38/* Offsets matching "struct edmacc_param" */ 29/* Offsets matching "struct edmacc_param" */
39#define PARM_OPT 0x00 30#define PARM_OPT 0x00
@@ -509,43 +500,59 @@ static irqreturn_t dma_tc1err_handler(int irq, void *data)
509 return IRQ_HANDLED; 500 return IRQ_HANDLED;
510} 501}
511 502
512static int reserve_contiguous_params(int ctlr, unsigned int id, 503static int reserve_contiguous_slots(int ctlr, unsigned int id,
513 unsigned int num_params, 504 unsigned int num_slots,
514 unsigned int start_param) 505 unsigned int start_slot)
515{ 506{
516 int i, j; 507 int i, j;
517 unsigned int count = num_params; 508 unsigned int count = num_slots;
509 int stop_slot = start_slot;
510 DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
518 511
519 for (i = start_param; i < edma_info[ctlr]->num_slots; ++i) { 512 for (i = start_slot; i < edma_info[ctlr]->num_slots; ++i) {
520 j = EDMA_CHAN_SLOT(i); 513 j = EDMA_CHAN_SLOT(i);
521 if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) 514 if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) {
515 /* Record our current beginning slot */
516 if (count == num_slots)
517 stop_slot = i;
518
522 count--; 519 count--;
520 set_bit(j, tmp_inuse);
521
523 if (count == 0) 522 if (count == 0)
524 break; 523 break;
525 else if (id == EDMA_CONT_PARAMS_FIXED_EXACT) 524 } else {
526 break; 525 clear_bit(j, tmp_inuse);
527 else 526
528 count = num_params; 527 if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
528 stop_slot = i;
529 break;
530 } else
531 count = num_slots;
532 }
529 } 533 }
530 534
531 /* 535 /*
532 * We have to clear any bits that we set 536 * We have to clear any bits that we set
533 * if we run out parameter RAMs, i.e we do find a set 537 * if we run out parameter RAM slots, i.e we do find a set
534 * of contiguous parameter RAMs but do not find the exact number 538 * of contiguous parameter RAM slots but do not find the exact number
535 * requested as we may reach the total number of parameter RAMs 539 * requested as we may reach the total number of parameter RAM slots
536 */ 540 */
537 if (count) { 541 if (i == edma_info[ctlr]->num_slots)
538 for (j = i - num_params + count + 1; j <= i ; ++j) 542 stop_slot = i;
543
544 for (j = start_slot; j < stop_slot; j++)
545 if (test_bit(j, tmp_inuse))
539 clear_bit(j, edma_info[ctlr]->edma_inuse); 546 clear_bit(j, edma_info[ctlr]->edma_inuse);
540 547
548 if (count)
541 return -EBUSY; 549 return -EBUSY;
542 }
543 550
544 for (j = i - num_params + 1; j <= i; ++j) 551 for (j = i - num_slots + 1; j <= i; ++j)
545 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j), 552 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
546 &dummy_paramset, PARM_SIZE); 553 &dummy_paramset, PARM_SIZE);
547 554
548 return EDMA_CTLR_CHAN(ctlr, i - num_params + 1); 555 return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
549} 556}
550 557
551/*-----------------------------------------------------------------------*/ 558/*-----------------------------------------------------------------------*/
@@ -743,26 +750,27 @@ EXPORT_SYMBOL(edma_free_slot);
743/** 750/**
744 * edma_alloc_cont_slots- alloc contiguous parameter RAM slots 751 * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
745 * The API will return the starting point of a set of 752 * The API will return the starting point of a set of
746 * contiguous PARAM's that have been requested 753 * contiguous parameter RAM slots that have been requested
747 * 754 *
748 * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT 755 * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
749 * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT 756 * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
750 * @count: number of contiguous Paramter RAM's 757 * @count: number of contiguous Paramter RAM slots
751 * @param - the start value of Parameter RAM that should be passed if id 758 * @slot - the start value of Parameter RAM slot that should be passed if id
752 * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT 759 * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
753 * 760 *
754 * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of 761 * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
755 * contiguous Parameter RAMs from parameter RAM 64 in the case of DaVinci SOCs 762 * contiguous Parameter RAM slots from parameter RAM 64 in the case of
756 * and 32 in the case of Primus 763 * DaVinci SOCs and 32 in the case of DA8xx SOCs.
757 * 764 *
758 * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a 765 * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
759 * set of contiguous parameter RAMs from the "param" that is passed as an 766 * set of contiguous parameter RAM slots from the "slot" that is passed as an
760 * argument to the API. 767 * argument to the API.
761 * 768 *
762 * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries 769 * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
763 * starts looking for a set of contiguous parameter RAMs from the "param" 770 * starts looking for a set of contiguous parameter RAMs from the "slot"
764 * that is passed as an argument to the API. On failure the API will try to 771 * that is passed as an argument to the API. On failure the API will try to
765 * find a set of contiguous Parameter RAMs in the remaining Parameter RAMs 772 * find a set of contiguous Parameter RAM slots from the remaining Parameter
773 * RAM slots
766 */ 774 */
767int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) 775int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
768{ 776{
@@ -771,12 +779,13 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
771 * the number of channels and lesser than the total number 779 * the number of channels and lesser than the total number
772 * of slots 780 * of slots
773 */ 781 */
774 if (slot < edma_info[ctlr]->num_channels || 782 if ((id != EDMA_CONT_PARAMS_ANY) &&
775 slot >= edma_info[ctlr]->num_slots) 783 (slot < edma_info[ctlr]->num_channels ||
784 slot >= edma_info[ctlr]->num_slots))
776 return -EINVAL; 785 return -EINVAL;
777 786
778 /* 787 /*
779 * The number of parameter RAMs requested cannot be less than 1 788 * The number of parameter RAM slots requested cannot be less than 1
780 * and cannot be more than the number of slots minus the number of 789 * and cannot be more than the number of slots minus the number of
781 * channels 790 * channels
782 */ 791 */
@@ -786,11 +795,11 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
786 795
787 switch (id) { 796 switch (id) {
788 case EDMA_CONT_PARAMS_ANY: 797 case EDMA_CONT_PARAMS_ANY:
789 return reserve_contiguous_params(ctlr, id, count, 798 return reserve_contiguous_slots(ctlr, id, count,
790 edma_info[ctlr]->num_channels); 799 edma_info[ctlr]->num_channels);
791 case EDMA_CONT_PARAMS_FIXED_EXACT: 800 case EDMA_CONT_PARAMS_FIXED_EXACT:
792 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: 801 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
793 return reserve_contiguous_params(ctlr, id, count, slot); 802 return reserve_contiguous_slots(ctlr, id, count, slot);
794 default: 803 default:
795 return -EINVAL; 804 return -EINVAL;
796 } 805 }
@@ -799,21 +808,21 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
799EXPORT_SYMBOL(edma_alloc_cont_slots); 808EXPORT_SYMBOL(edma_alloc_cont_slots);
800 809
801/** 810/**
802 * edma_free_cont_slots - deallocate DMA parameter RAMs 811 * edma_free_cont_slots - deallocate DMA parameter RAM slots
803 * @slot: first parameter RAM of a set of parameter RAMs to be freed 812 * @slot: first parameter RAM of a set of parameter RAM slots to be freed
804 * @count: the number of contiguous parameter RAMs to be freed 813 * @count: the number of contiguous parameter RAM slots to be freed
805 * 814 *
806 * This deallocates the parameter RAM slots allocated by 815 * This deallocates the parameter RAM slots allocated by
807 * edma_alloc_cont_slots. 816 * edma_alloc_cont_slots.
808 * Callers/applications need to keep track of sets of contiguous 817 * Callers/applications need to keep track of sets of contiguous
809 * parameter RAMs that have been allocated using the edma_alloc_cont_slots 818 * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
810 * API. 819 * API.
811 * Callers are responsible for ensuring the slots are inactive, and will 820 * Callers are responsible for ensuring the slots are inactive, and will
812 * not be activated. 821 * not be activated.
813 */ 822 */
814int edma_free_cont_slots(unsigned slot, int count) 823int edma_free_cont_slots(unsigned slot, int count)
815{ 824{
816 unsigned ctlr; 825 unsigned ctlr, slot_to_free;
817 int i; 826 int i;
818 827
819 ctlr = EDMA_CTLR(slot); 828 ctlr = EDMA_CTLR(slot);
@@ -826,11 +835,11 @@ int edma_free_cont_slots(unsigned slot, int count)
826 835
827 for (i = slot; i < slot + count; ++i) { 836 for (i = slot; i < slot + count; ++i) {
828 ctlr = EDMA_CTLR(i); 837 ctlr = EDMA_CTLR(i);
829 slot = EDMA_CHAN_SLOT(i); 838 slot_to_free = EDMA_CHAN_SLOT(i);
830 839
831 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), 840 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
832 &dummy_paramset, PARM_SIZE); 841 &dummy_paramset, PARM_SIZE);
833 clear_bit(slot, edma_info[ctlr]->edma_inuse); 842 clear_bit(slot_to_free, edma_info[ctlr]->edma_inuse);
834 } 843 }
835 844
836 return 0; 845 return 0;
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index f6ea9db11f4..744755b5323 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -12,23 +12,14 @@
12 12
13#include <linux/errno.h> 13#include <linux/errno.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/module.h>
17#include <linux/clk.h> 15#include <linux/clk.h>
18#include <linux/err.h> 16#include <linux/err.h>
19#include <linux/io.h> 17#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/bitops.h>
22 18
23#include <mach/cputype.h>
24#include <mach/irqs.h>
25#include <mach/hardware.h>
26#include <mach/common.h>
27#include <mach/gpio.h> 19#include <mach/gpio.h>
28 20
29#include <asm/mach/irq.h> 21#include <asm/mach/irq.h>
30 22
31
32static DEFINE_SPINLOCK(gpio_lock); 23static DEFINE_SPINLOCK(gpio_lock);
33 24
34struct davinci_gpio { 25struct davinci_gpio {
diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h
index e07f70ed7c5..834725f1e81 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -11,6 +11,9 @@
11#define DAVINCI_ASP0_BASE 0x01E02000 11#define DAVINCI_ASP0_BASE 0x01E02000
12#define DAVINCI_ASP1_BASE 0x01E04000 12#define DAVINCI_ASP1_BASE 0x01E04000
13 13
14/* Bases of dm365 register banks */
15#define DAVINCI_DM365_ASP0_BASE 0x01D02000
16
14/* Bases of dm646x register banks */ 17/* Bases of dm646x register banks */
15#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 18#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
16#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 19#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 1fd3917cae4..6ca2c9a0a48 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -20,12 +20,6 @@ extern void davinci_irq_init(void);
20extern void __iomem *davinci_intc_base; 20extern void __iomem *davinci_intc_base;
21extern int davinci_intc_type; 21extern int davinci_intc_type;
22 22
23/* parameters describe VBUS sourcing for host mode */
24extern void setup_usb(unsigned mA, unsigned potpgt_msec);
25
26/* parameters describe VBUS sourcing for host mode */
27extern void setup_usb(unsigned mA, unsigned potpgt_msec);
28
29struct davinci_timer_instance { 23struct davinci_timer_instance {
30 void __iomem *base; 24 void __iomem *base;
31 u32 bottom_irq; 25 u32 bottom_irq;
diff --git a/arch/arm/mach-davinci/include/mach/cpufreq.h b/arch/arm/mach-davinci/include/mach/cpufreq.h
new file mode 100644
index 00000000000..3c089cfb6cd
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cpufreq.h
@@ -0,0 +1,26 @@
1/*
2 * TI DaVinci CPUFreq platform support.
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef _MACH_DAVINCI_CPUFREQ_H
16#define _MACH_DAVINCI_CPUFREQ_H
17
18#include <linux/cpufreq.h>
19
20struct davinci_cpufreq_config {
21 struct cpufreq_frequency_table *freq_table;
22 int (*set_voltage) (unsigned int index);
23 int (*init) (void);
24};
25
26#endif
diff --git a/arch/arm/mach-davinci/include/mach/cpuidle.h b/arch/arm/mach-davinci/include/mach/cpuidle.h
new file mode 100644
index 00000000000..cbfc6a9c81b
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cpuidle.h
@@ -0,0 +1,17 @@
1/*
2 * TI DaVinci cpuidle platform support
3 *
4 * 2009 (C) Texas Instruments, Inc. http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10#ifndef _MACH_DAVINCI_CPUIDLE_H
11#define _MACH_DAVINCI_CPUIDLE_H
12
13struct davinci_cpuidle_config {
14 u32 ddr2_pdown;
15};
16
17#endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index d4095d0572c..90704910d34 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -11,12 +11,17 @@
11#ifndef __ASM_ARCH_DAVINCI_DA8XX_H 11#ifndef __ASM_ARCH_DAVINCI_DA8XX_H
12#define __ASM_ARCH_DAVINCI_DA8XX_H 12#define __ASM_ARCH_DAVINCI_DA8XX_H
13 13
14#include <video/da8xx-fb.h>
15
14#include <mach/serial.h> 16#include <mach/serial.h>
15#include <mach/edma.h> 17#include <mach/edma.h>
16#include <mach/i2c.h> 18#include <mach/i2c.h>
17#include <mach/emac.h> 19#include <mach/emac.h>
18#include <mach/asp.h> 20#include <mach/asp.h>
19#include <mach/mmc.h> 21#include <mach/mmc.h>
22#include <mach/usb.h>
23
24extern void __iomem *da8xx_syscfg_base;
20 25
21/* 26/*
22 * The cp_intc interrupt controller for the da8xx isn't in the same 27 * The cp_intc interrupt controller for the da8xx isn't in the same
@@ -29,11 +34,15 @@
29#define DA8XX_CP_INTC_SIZE SZ_8K 34#define DA8XX_CP_INTC_SIZE SZ_8K
30#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) 35#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
31 36
32#define DA8XX_BOOT_CFG_BASE (IO_PHYS + 0x14000) 37#define DA8XX_SYSCFG_BASE (IO_PHYS + 0x14000)
38#define DA8XX_SYSCFG_VIRT(x) (da8xx_syscfg_base + (x))
39#define DA8XX_JTAG_ID_REG 0x18
40#define DA8XX_CFGCHIP0_REG 0x17c
41#define DA8XX_CFGCHIP2_REG 0x184
42#define DA8XX_CFGCHIP3_REG 0x188
33 43
34#define DA8XX_PSC0_BASE 0x01c10000 44#define DA8XX_PSC0_BASE 0x01c10000
35#define DA8XX_PLL0_BASE 0x01c11000 45#define DA8XX_PLL0_BASE 0x01c11000
36#define DA8XX_JTAG_ID_REG 0x01c14018
37#define DA8XX_TIMER64P0_BASE 0x01c20000 46#define DA8XX_TIMER64P0_BASE 0x01c20000
38#define DA8XX_TIMER64P1_BASE 0x01c21000 47#define DA8XX_TIMER64P1_BASE 0x01c21000
39#define DA8XX_GPIO_BASE 0x01e26000 48#define DA8XX_GPIO_BASE 0x01e26000
@@ -43,6 +52,7 @@
43#define DA8XX_AEMIF_CS2_BASE 0x60000000 52#define DA8XX_AEMIF_CS2_BASE 0x60000000
44#define DA8XX_AEMIF_CS3_BASE 0x62000000 53#define DA8XX_AEMIF_CS3_BASE 0x62000000
45#define DA8XX_AEMIF_CTL_BASE 0x68000000 54#define DA8XX_AEMIF_CTL_BASE 0x68000000
55#define DA8XX_DDR2_CTL_BASE 0xb0000000
46 56
47#define PINMUX0 0x00 57#define PINMUX0 0x00
48#define PINMUX1 0x04 58#define PINMUX1 0x04
@@ -71,13 +81,20 @@ void __init da850_init(void);
71int da8xx_register_edma(void); 81int da8xx_register_edma(void);
72int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); 82int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
73int da8xx_register_watchdog(void); 83int da8xx_register_watchdog(void);
84int da8xx_register_usb20(unsigned mA, unsigned potpgt);
85int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
74int da8xx_register_emac(void); 86int da8xx_register_emac(void);
75int da8xx_register_lcdc(void); 87int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
76int da8xx_register_mmcsd0(struct davinci_mmc_config *config); 88int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
77void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata); 89void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
90int da8xx_register_rtc(void);
91int da850_register_cpufreq(void);
92int da8xx_register_cpuidle(void);
78 93
79extern struct platform_device da8xx_serial_device; 94extern struct platform_device da8xx_serial_device;
80extern struct emac_platform_data da8xx_emac_pdata; 95extern struct emac_platform_data da8xx_emac_pdata;
96extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
97extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
81 98
82extern const short da830_emif25_pins[]; 99extern const short da830_emif25_pins[];
83extern const short da830_spi0_pins[]; 100extern const short da830_spi0_pins[];
@@ -110,6 +127,7 @@ extern const short da850_uart2_pins[];
110extern const short da850_i2c0_pins[]; 127extern const short da850_i2c0_pins[];
111extern const short da850_i2c1_pins[]; 128extern const short da850_i2c1_pins[];
112extern const short da850_cpgmac_pins[]; 129extern const short da850_cpgmac_pins[];
130extern const short da850_rmii_pins[];
113extern const short da850_mcasp_pins[]; 131extern const short da850_mcasp_pins[];
114extern const short da850_lcdcntl_pins[]; 132extern const short da850_lcdcntl_pins[];
115extern const short da850_mmcsd0_pins[]; 133extern const short da850_mmcsd0_pins[];
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index 09db4343bb4..f1710a30e7b 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -16,6 +16,8 @@
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <mach/hardware.h> 17#include <mach/hardware.h>
18#include <mach/emac.h> 18#include <mach/emac.h>
19#include <mach/asp.h>
20#include <mach/keyscan.h>
19 21
20#define DM365_EMAC_BASE (0x01D07000) 22#define DM365_EMAC_BASE (0x01D07000)
21#define DM365_EMAC_CNTRL_OFFSET (0x0000) 23#define DM365_EMAC_CNTRL_OFFSET (0x0000)
@@ -24,6 +26,14 @@
24#define DM365_EMAC_MDIO_OFFSET (0x4000) 26#define DM365_EMAC_MDIO_OFFSET (0x4000)
25#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) 27#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000)
26 28
29/* Base of key scan register bank */
30#define DM365_KEYSCAN_BASE (0x01C69400)
31
32#define DM365_RTC_BASE (0x01C69000)
33
27void __init dm365_init(void); 34void __init dm365_init(void);
35void __init dm365_init_asp(struct snd_platform_data *pdata);
36void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
37void __init dm365_init_rtc(void);
28 38
29#endif /* __ASM_ARCH_DM365_H */ 39#endif /* __ASM_ARCH_DM365_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 0efb73852c2..44e8f0fae9e 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -22,7 +22,6 @@
22#ifndef __ASM_ARCH_DM644X_H 22#ifndef __ASM_ARCH_DM644X_H
23#define __ASM_ARCH_DM644X_H 23#define __ASM_ARCH_DM644X_H
24 24
25#include <linux/platform_device.h>
26#include <mach/hardware.h> 25#include <mach/hardware.h>
27#include <mach/emac.h> 26#include <mach/emac.h>
28#include <mach/asp.h> 27#include <mach/asp.h>
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 3c918a77261..354af71798d 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -217,6 +217,7 @@
217#define IRQ_DM365_SDIOINT0 23 217#define IRQ_DM365_SDIOINT0 23
218#define IRQ_DM365_MMCINT1 27 218#define IRQ_DM365_MMCINT1 27
219#define IRQ_DM365_PWMINT3 28 219#define IRQ_DM365_PWMINT3 28
220#define IRQ_DM365_RTCINT 29
220#define IRQ_DM365_SDIOINT1 31 221#define IRQ_DM365_SDIOINT1 31
221#define IRQ_DM365_SPIINT0_0 42 222#define IRQ_DM365_SPIINT0_0 42
222#define IRQ_DM365_SPIINT3_0 43 223#define IRQ_DM365_SPIINT3_0 43
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index bb84893a4e8..b60c693985f 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -40,6 +40,11 @@ enum davinci_dm644x_index {
40 40
41 /* AEAW functions */ 41 /* AEAW functions */
42 DM644X_AEAW, 42 DM644X_AEAW,
43 DM644X_AEAW0,
44 DM644X_AEAW1,
45 DM644X_AEAW2,
46 DM644X_AEAW3,
47 DM644X_AEAW4,
43 48
44 /* Memory Stick */ 49 /* Memory Stick */
45 DM644X_MSTK, 50 DM644X_MSTK,
@@ -237,8 +242,8 @@ enum davinci_dm365_index {
237 DM365_EMAC_MDIO, 242 DM365_EMAC_MDIO,
238 DM365_EMAC_MDCLK, 243 DM365_EMAC_MDCLK,
239 244
240 /* Keypad */ 245 /* Key Scan */
241 DM365_KEYPAD, 246 DM365_KEYSCAN,
242 247
243 /* PWM */ 248 /* PWM */
244 DM365_PWM0, 249 DM365_PWM0,
@@ -774,6 +779,14 @@ enum davinci_da850_index {
774 DA850_MII_RXD_0, 779 DA850_MII_RXD_0,
775 DA850_MDIO_CLK, 780 DA850_MDIO_CLK,
776 DA850_MDIO_D, 781 DA850_MDIO_D,
782 DA850_RMII_TXD_0,
783 DA850_RMII_TXD_1,
784 DA850_RMII_TXEN,
785 DA850_RMII_CRS_DV,
786 DA850_RMII_RXD_0,
787 DA850_RMII_RXD_1,
788 DA850_RMII_RXER,
789 DA850_RMII_MHZ_50_CLK,
777 790
778 /* McASP function */ 791 /* McASP function */
779 DA850_ACLKR, 792 DA850_ACLKR,
@@ -881,8 +894,9 @@ enum davinci_da850_index {
881 DA850_NEMA_CS_2, 894 DA850_NEMA_CS_2,
882 895
883 /* GPIO function */ 896 /* GPIO function */
897 DA850_GPIO2_6,
898 DA850_GPIO2_8,
884 DA850_GPIO2_15, 899 DA850_GPIO2_15,
885 DA850_GPIO8_10,
886 DA850_GPIO4_0, 900 DA850_GPIO4_0,
887 DA850_GPIO4_1, 901 DA850_GPIO4_1,
888}; 902};
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
index 8e4f10fe126..5a7d7581b8c 100644
--- a/arch/arm/mach-davinci/include/mach/system.h
+++ b/arch/arm/mach-davinci/include/mach/system.h
@@ -11,9 +11,6 @@
11#ifndef __ASM_ARCH_SYSTEM_H 11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H 12#define __ASM_ARCH_SYSTEM_H
13 13
14#include <linux/io.h>
15#include <mach/hardware.h>
16
17extern void davinci_watchdog_reset(void); 14extern void davinci_watchdog_reset(void);
18 15
19static inline void arch_idle(void) 16static inline void arch_idle(void)
diff --git a/arch/arm/mach-davinci/include/mach/usb.h b/arch/arm/mach-davinci/include/mach/usb.h
new file mode 100644
index 00000000000..e0bc4abe69c
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/usb.h
@@ -0,0 +1,59 @@
1/*
2 * USB related definitions
3 *
4 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_USB_H
12#define __ASM_ARCH_USB_H
13
14/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
15#define CFGCHIP2_PHYCLKGD (1 << 17)
16#define CFGCHIP2_VBUSSENSE (1 << 16)
17#define CFGCHIP2_RESET (1 << 15)
18#define CFGCHIP2_OTGMODE (3 << 13)
19#define CFGCHIP2_NO_OVERRIDE (0 << 13)
20#define CFGCHIP2_FORCE_HOST (1 << 13)
21#define CFGCHIP2_FORCE_DEVICE (2 << 13)
22#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
23#define CFGCHIP2_USB1PHYCLKMUX (1 << 12)
24#define CFGCHIP2_USB2PHYCLKMUX (1 << 11)
25#define CFGCHIP2_PHYPWRDN (1 << 10)
26#define CFGCHIP2_OTGPWRDN (1 << 9)
27#define CFGCHIP2_DATPOL (1 << 8)
28#define CFGCHIP2_USB1SUSPENDM (1 << 7)
29#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */
30#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */
31#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */
32#define CFGCHIP2_REFFREQ (0xf << 0)
33#define CFGCHIP2_REFFREQ_12MHZ (1 << 0)
34#define CFGCHIP2_REFFREQ_24MHZ (2 << 0)
35#define CFGCHIP2_REFFREQ_48MHZ (3 << 0)
36
37struct da8xx_ohci_root_hub;
38
39typedef void (*da8xx_ocic_handler_t)(struct da8xx_ohci_root_hub *hub,
40 unsigned port);
41
42/* Passed as the platform data to the OHCI driver */
43struct da8xx_ohci_root_hub {
44 /* Switch the port power on/off */
45 int (*set_power)(unsigned port, int on);
46 /* Read the port power status */
47 int (*get_power)(unsigned port);
48 /* Read the port over-current indicator */
49 int (*get_oci)(unsigned port);
50 /* Over-current indicator change notification (pass NULL to disable) */
51 int (*ocic_notify)(da8xx_ocic_handler_t handler);
52
53 /* Time from power on to power good (in 2 ms units) */
54 u8 potpgt;
55};
56
57void davinci_setup_usb(unsigned mA, unsigned potpgt_ms);
58
59#endif /* ifndef __ASM_ARCH_USB_H */
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index 898905e4894..f757e83415f 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -19,7 +19,6 @@
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/spinlock.h> 20#include <linux/spinlock.h>
21 21
22#include <mach/hardware.h>
23#include <mach/mux.h> 22#include <mach/mux.h>
24#include <mach/common.h> 23#include <mach/common.h>
25 24
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index a78b657e916..04a3cb72c5a 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -19,14 +19,11 @@
19 * 19 *
20 */ 20 */
21#include <linux/kernel.h> 21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/init.h> 22#include <linux/init.h>
24#include <linux/io.h> 23#include <linux/io.h>
25 24
26#include <mach/cputype.h> 25#include <mach/cputype.h>
27#include <mach/hardware.h>
28#include <mach/psc.h> 26#include <mach/psc.h>
29#include <mach/mux.h>
30 27
31/* PSC register offsets */ 28/* PSC register offsets */
32#define EPCPR 0x070 29#define EPCPR 0x070
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index c530c7333d0..7ce5ba08657 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -28,14 +28,8 @@
28#include <linux/clk.h> 28#include <linux/clk.h>
29#include <linux/io.h> 29#include <linux/io.h>
30 30
31#include <asm/irq.h>
32#include <mach/hardware.h>
33#include <mach/serial.h> 31#include <mach/serial.h>
34#include <mach/irqs.h>
35#include <mach/cputype.h> 32#include <mach/cputype.h>
36#include <mach/common.h>
37
38#include "clock.h"
39 33
40static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, 34static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
41 int offset) 35 int offset)
diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c
index 4f1fc9b318b..db0f7787faf 100644
--- a/arch/arm/mach-davinci/sram.c
+++ b/arch/arm/mach-davinci/sram.c
@@ -9,15 +9,12 @@
9 * (at your option) any later version. 9 * (at your option) any later version.
10 */ 10 */
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h> 12#include <linux/init.h>
14#include <linux/genalloc.h> 13#include <linux/genalloc.h>
15 14
16#include <mach/common.h> 15#include <mach/common.h>
17#include <mach/memory.h>
18#include <mach/sram.h> 16#include <mach/sram.h>
19 17
20
21static struct gen_pool *sram_pool; 18static struct gen_pool *sram_pool;
22 19
23void *sram_alloc(size_t len, dma_addr_t *dma) 20void *sram_alloc(size_t len, dma_addr_t *dma)
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 0d1b6d407b4..42d985beece 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -14,20 +14,14 @@
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/clocksource.h> 15#include <linux/clocksource.h>
16#include <linux/clockchips.h> 16#include <linux/clockchips.h>
17#include <linux/spinlock.h>
18#include <linux/io.h> 17#include <linux/io.h>
19#include <linux/clk.h> 18#include <linux/clk.h>
20#include <linux/err.h> 19#include <linux/err.h>
21#include <linux/device.h>
22#include <linux/platform_device.h> 20#include <linux/platform_device.h>
23 21
24#include <mach/hardware.h> 22#include <mach/hardware.h>
25#include <asm/system.h>
26#include <asm/irq.h>
27#include <asm/mach/irq.h> 23#include <asm/mach/irq.h>
28#include <asm/mach/time.h> 24#include <asm/mach/time.h>
29#include <asm/errno.h>
30#include <mach/io.h>
31#include <mach/cputype.h> 25#include <mach/cputype.h>
32#include <mach/time.h> 26#include <mach/time.h>
33#include "clock.h" 27#include "clock.h"
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index 06f55931620..31f0cbea0ca 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -1,21 +1,21 @@
1/* 1/*
2 * USB 2 * USB
3 */ 3 */
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/init.h> 4#include <linux/init.h>
7#include <linux/platform_device.h> 5#include <linux/platform_device.h>
8#include <linux/dma-mapping.h> 6#include <linux/dma-mapping.h>
9 7
10#include <linux/usb/musb.h> 8#include <linux/usb/musb.h>
11#include <linux/usb/otg.h>
12 9
13#include <mach/common.h> 10#include <mach/common.h>
14#include <mach/hardware.h>
15#include <mach/irqs.h> 11#include <mach/irqs.h>
16#include <mach/cputype.h> 12#include <mach/cputype.h>
13#include <mach/usb.h>
17 14
18#define DAVINCI_USB_OTG_BASE 0x01C64000 15#define DAVINCI_USB_OTG_BASE 0x01c64000
16
17#define DA8XX_USB0_BASE 0x01e00000
18#define DA8XX_USB1_BASE 0x01e25000
19 19
20#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) 20#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
21static struct musb_hdrc_eps_bits musb_eps[] = { 21static struct musb_hdrc_eps_bits musb_eps[] = {
@@ -85,10 +85,10 @@ static struct platform_device usb_dev = {
85 .num_resources = ARRAY_SIZE(usb_resources), 85 .num_resources = ARRAY_SIZE(usb_resources),
86}; 86};
87 87
88void __init setup_usb(unsigned mA, unsigned potpgt_msec) 88void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms)
89{ 89{
90 usb_data.power = mA / 2; 90 usb_data.power = mA > 510 ? 255 : mA / 2;
91 usb_data.potpgt = potpgt_msec / 2; 91 usb_data.potpgt = (potpgt_ms + 1) / 2;
92 92
93 if (cpu_is_davinci_dm646x()) { 93 if (cpu_is_davinci_dm646x()) {
94 /* Override the defaults as DM6467 uses different IRQs. */ 94 /* Override the defaults as DM6467 uses different IRQs. */
@@ -100,11 +100,77 @@ void __init setup_usb(unsigned mA, unsigned potpgt_msec)
100 platform_device_register(&usb_dev); 100 platform_device_register(&usb_dev);
101} 101}
102 102
103#ifdef CONFIG_ARCH_DAVINCI_DA8XX
104static struct resource da8xx_usb20_resources[] = {
105 {
106 .start = DA8XX_USB0_BASE,
107 .end = DA8XX_USB0_BASE + SZ_64K - 1,
108 .flags = IORESOURCE_MEM,
109 },
110 {
111 .start = IRQ_DA8XX_USB_INT,
112 .flags = IORESOURCE_IRQ,
113 },
114};
115
116int __init da8xx_register_usb20(unsigned mA, unsigned potpgt)
117{
118 usb_data.clock = "usb20";
119 usb_data.power = mA > 510 ? 255 : mA / 2;
120 usb_data.potpgt = (potpgt + 1) / 2;
121
122 usb_dev.resource = da8xx_usb20_resources;
123 usb_dev.num_resources = ARRAY_SIZE(da8xx_usb20_resources);
124
125 return platform_device_register(&usb_dev);
126}
127#endif /* CONFIG_DAVINCI_DA8XX */
128
103#else 129#else
104 130
105void __init setup_usb(unsigned mA, unsigned potpgt_msec) 131void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms)
106{ 132{
107} 133}
108 134
135#ifdef CONFIG_ARCH_DAVINCI_DA8XX
136int __init da8xx_register_usb20(unsigned mA, unsigned potpgt)
137{
138 return 0;
139}
140#endif
141
109#endif /* CONFIG_USB_MUSB_HDRC */ 142#endif /* CONFIG_USB_MUSB_HDRC */
110 143
144#ifdef CONFIG_ARCH_DAVINCI_DA8XX
145static struct resource da8xx_usb11_resources[] = {
146 [0] = {
147 .start = DA8XX_USB1_BASE,
148 .end = DA8XX_USB1_BASE + SZ_4K - 1,
149 .flags = IORESOURCE_MEM,
150 },
151 [1] = {
152 .start = IRQ_DA8XX_IRQN,
153 .end = IRQ_DA8XX_IRQN,
154 .flags = IORESOURCE_IRQ,
155 },
156};
157
158static u64 da8xx_usb11_dma_mask = DMA_BIT_MASK(32);
159
160static struct platform_device da8xx_usb11_device = {
161 .name = "ohci",
162 .id = 0,
163 .dev = {
164 .dma_mask = &da8xx_usb11_dma_mask,
165 .coherent_dma_mask = DMA_BIT_MASK(32),
166 },
167 .num_resources = ARRAY_SIZE(da8xx_usb11_resources),
168 .resource = da8xx_usb11_resources,
169};
170
171int __init da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata)
172{
173 da8xx_usb11_device.dev.platform_data = pdata;
174 return platform_device_register(&da8xx_usb11_device);
175}
176#endif /* CONFIG_DAVINCI_DA8XX */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 05:26:59 -0500