From fb533d0c5a9783ecafa9a177bace6384c47282a9 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 14 Sep 2007 14:22:36 -0500 Subject: [POWERPC] 8xx: Infrastructure code cleanup. 1. Keep a global mpc8xx_immr mapping, rather than constantly creating temporary mappings. 2. Look for new fsl,cpm1 and fsl,cpm1-pic names. 3. Always reset the CPM when not using the udbg console; this is required in case the firmware initialized a device that is incompatible with one that the kernel is about to use. 4. Remove some superfluous casts and header includes. 5. Change a usage of IMAP_ADDR to get_immrbase(). 6. Use phys_addr_t, not uint, for dpram_pbase. 7. Various sparse-related fixes, such as __iomem annotations. 8. Remove mpc8xx_show_cpuinfo, which doesn't provide anything useful beyond the generic cpuinfo handler. 9. Move prototypes for 8xx support functions from board files to sysdev/commproc.h. Signed-off-by: Scott Wood Signed-off-by: Kumar Gala --- arch/powerpc/platforms/8xx/m8xx_setup.c | 90 ++++++++------------------------- 1 file changed, 20 insertions(+), 70 deletions(-) (limited to 'arch/powerpc/platforms/8xx/m8xx_setup.c') diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c index b2b98dd8be6a..d35eda80e9e6 100644 --- a/arch/powerpc/platforms/8xx/m8xx_setup.c +++ b/arch/powerpc/platforms/8xx/m8xx_setup.c @@ -10,57 +10,33 @@ * bootup setup stuff.. */ -#include -#include #include -#include -#include -#include -#include #include -#include -#include -#include -#include #include -#include #include -#include -#include -#include -#include -#include #include #include -#include -#include -#include #include -#include #include #include -#include -#include #include #include #include -#include "sysdev/mpc8xx_pic.h" +#include +#include #ifdef CONFIG_PCMCIA_M8XX struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops; #endif void m8xx_calibrate_decr(void); -#ifdef CONFIG_8xx_WDT -extern void m8xx_wdt_handler_install(bd_t *bp); -#endif extern int cpm_pic_init(void); extern int cpm_get_irq(void); /* A place holder for time base interrupts, if they are ever enabled. */ -irqreturn_t timebase_interrupt(int irq, void * dev) +static irqreturn_t timebase_interrupt(int irq, void *dev) { printk ("timebase_interrupt()\n"); @@ -77,7 +53,7 @@ static struct irqaction tbint_irqaction = { void __init __attribute__ ((weak)) init_internal_rtc(void) { - sit8xx_t *sys_tmr = (sit8xx_t *) immr_map(im_sit); + sit8xx_t __iomem *sys_tmr = immr_map(im_sit); /* Disable the RTC one second and alarm interrupts. */ clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE)); @@ -116,13 +92,13 @@ static int __init get_freq(char *name, unsigned long *val) void __init mpc8xx_calibrate_decr(void) { struct device_node *cpu; - cark8xx_t *clk_r1; - car8xx_t *clk_r2; - sitk8xx_t *sys_tmr1; - sit8xx_t *sys_tmr2; + cark8xx_t __iomem *clk_r1; + car8xx_t __iomem *clk_r2; + sitk8xx_t __iomem *sys_tmr1; + sit8xx_t __iomem *sys_tmr2; int irq, virq; - clk_r1 = (cark8xx_t *) immr_map(im_clkrstk); + clk_r1 = immr_map(im_clkrstk); /* Unlock the SCCR. */ out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY); @@ -130,7 +106,7 @@ void __init mpc8xx_calibrate_decr(void) immr_unmap(clk_r1); /* Force all 8xx processors to use divide by 16 processor clock. */ - clk_r2 = (car8xx_t *) immr_map(im_clkrst); + clk_r2 = immr_map(im_clkrst); setbits32(&clk_r2->car_sccr, 0x02000000); immr_unmap(clk_r2); @@ -164,7 +140,7 @@ void __init mpc8xx_calibrate_decr(void) * we guarantee the registers are locked, then we unlock them * for our use. */ - sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk); + sys_tmr1 = immr_map(im_sitk); out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY); out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY); out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY); @@ -184,20 +160,13 @@ void __init mpc8xx_calibrate_decr(void) virq= irq_of_parse_and_map(cpu, 0); irq = irq_map[virq].hwirq; - sys_tmr2 = (sit8xx_t *) immr_map(im_sit); + sys_tmr2 = immr_map(im_sit); out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) | (TBSCR_TBF | TBSCR_TBE)); immr_unmap(sys_tmr2); if (setup_irq(virq, &tbint_irqaction)) panic("Could not allocate timer IRQ!"); - -#ifdef CONFIG_8xx_WDT - /* Install watchdog timer handler early because it might be - * already enabled by the bootloader - */ - m8xx_wdt_handler_install(binfo); -#endif } /* The RTC on the MPC8xx is an internal register. @@ -207,12 +176,12 @@ void __init mpc8xx_calibrate_decr(void) int mpc8xx_set_rtc_time(struct rtc_time *tm) { - sitk8xx_t *sys_tmr1; - sit8xx_t *sys_tmr2; + sitk8xx_t __iomem *sys_tmr1; + sit8xx_t __iomem *sys_tmr2; int time; - sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk); - sys_tmr2 = (sit8xx_t *) immr_map(im_sit); + sys_tmr1 = immr_map(im_sitk); + sys_tmr2 = immr_map(im_sit); time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec); @@ -228,7 +197,7 @@ int mpc8xx_set_rtc_time(struct rtc_time *tm) void mpc8xx_get_rtc_time(struct rtc_time *tm) { unsigned long data; - sit8xx_t *sys_tmr = (sit8xx_t *) immr_map(im_sit); + sit8xx_t __iomem *sys_tmr = immr_map(im_sit); /* Get time from the RTC. */ data = in_be32(&sys_tmr->sit_rtc); @@ -241,8 +210,7 @@ void mpc8xx_get_rtc_time(struct rtc_time *tm) void mpc8xx_restart(char *cmd) { - __volatile__ unsigned char dummy; - car8xx_t * clk_r = (car8xx_t *) immr_map(im_clkrst); + car8xx_t __iomem *clk_r = immr_map(im_clkrst); local_irq_disable(); @@ -252,26 +220,8 @@ void mpc8xx_restart(char *cmd) */ mtmsr(mfmsr() & ~0x1000); - dummy = in_8(&clk_r->res[0]); - printk("Restart failed\n"); - while(1); -} - -void mpc8xx_show_cpuinfo(struct seq_file *m) -{ - struct device_node *root; - uint memsize = total_memory; - const char *model = ""; - - seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n"); - - root = of_find_node_by_path("/"); - if (root) - model = of_get_property(root, "model", NULL); - seq_printf(m, "Machine\t\t: %s\n", model); - of_node_put(root); - - seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024)); + in_8(&clk_r->res[0]); + panic("Restart failed\n"); } static void cpm_cascade(unsigned int irq, struct irq_desc *desc) -- cgit v1.2.2