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* ENGR00318773-1 mxc: asrc: Don't use the extra work thread to handle the last ↵Nicolin Chen2014-06-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | period data The original design: -> Input DMA task -> complete() | -> Output DMA task -> complete() | | | -> Last period polling work thread -> complete() | Main thread --------------> wait_for_completion() of Input and last period It's too complicated and worthless to use an extra work thread for last period data. So this patch just switches the flow into a simpler approach: -> Input DMA task -> complete() | -> Output DMA task -> complete() | Main thread --------------> wait_for_completion() of In/Output -> Last period polling Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* net: Add a software TSO helper APIEzequiel Garcia2014-06-13
| | | | | | | | Although the implementation probably needs a lot of work, this initial API allows to implement software TSO in mvneta and mv643xx_eth drivers in a not so intrusive way. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
* ENGR00313685-7 of/irq: Create of_irq_parse_and_map_pci() to consolidate arch ↵Grant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | code. commit 16b84e5a505c790538e534ad8dfda9c288691e40 upstream. Several architectures open code effectively the same code block for finding and mapping PCI irqs. This patch consolidates it down to a single function. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/mach-integrator/pci_v3.c arch/mips/pci/pci-rt3883.c
* ENGR00313685-5 of: Add helper for printing an of_phandle_args structureGrant Likely2014-05-16
| | | | | | | | | | | | | commit 624cfca534f9b1ffb1326617b4e973a3d5ecff4a upstream. It is sometimes useful for debug to get the contents of an of_phandle_args structure out into the kernel log. Signed-off-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: drivers/of/base.c
* ENGR00313685-4 of/irq: Refactor interrupt-map parsingGrant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 2361613206e66ce59cc0e08efa8d98ec15b84ed1 upstream. All the users of of_irq_parse_raw pass in a raw interrupt specifier from the device tree and expect it to be returned (possibly modified) in an of_phandle_args structure. However, the primary function of of_irq_parse_raw() is to check for translations due to the presence of one or more interrupt-map properties. The actual placing of the data into an of_phandle_args structure is trivial. If it is refactored to accept an of_phandle_args structure directly, then it becomes possible to consume of_phandle_args from other sources. This is important for an upcoming patch that allows a device to be connected to more than one interrupt parent. It also simplifies the code a bit. The biggest complication with this patch is that the old version works on the interrupt specifiers in __be32 form, but the of_phandle_args structure is intended to carry it in the cpu-native version. A bit of churn was required to make this work. In the end it results in tighter code, so the churn is worth it. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: drivers/of/irq.c
* ENGR00313685-3 of/irq: simplify args to irq_create_of_mappingGrant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | | | commit e6d30ab1e7d1281784672c0fc2ffa385cfb7279e upstream. All the callers of irq_create_of_mapping() pass the contents of a struct of_phandle_args structure to the function. Since all the callers already have an of_phandle_args pointer, why not pass it directly to irq_create_of_mapping()? Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/mach-integrator/pci_v3.c arch/mips/pci/pci-rt3883.c kernel/irq/irqdomain.c
* ENGR00313685-2 of/irq: Replace of_irq with of_phandle_argsGrant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | commit 530210c7814e83564c7ca7bca8192515042c0b63 upstream. struct of_irq and struct of_phandle_args are exactly the same structure. This patch makes the kernel use of_phandle_args everywhere. This in itself isn't a big deal, but it makes some follow-on patches simpler. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/mach-integrator/pci_v3.c arch/mips/pci/pci-rt3883.c include/linux/of_irq.h
* ENGR00313685-1 of/irq: Rename of_irq_map_* functions to of_irq_parse_*Grant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 0c02c8007ea5554d028f99fd3e29fc201fdeeab3 upstream. The OF irq handling code has been overloading the term 'map' to refer to both parsing the data in the device tree and mapping it to the internal linux irq system. This is probably because the device tree does have the concept of an 'interrupt-map' function for translating interrupt references from one node to another, but 'map' is still confusing when the primary purpose of some of the functions are to parse the DT data. This patch renames all the of_irq_map_* functions to of_irq_parse_* which makes it clear that there is a difference between the parsing phase and the mapping phase. Kernel code can make use of just the parsing or just the mapping support as needed by the subsystem. The patch was generated mechanically with a handful of sed commands. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/mach-integrator/pci_v3.c arch/mips/pci/pci-rt3883.c drivers/of/irq.c
* ENGR00313508-01 ARM: imx6sx: add enet sleep mode supportFugang Duan2014-05-15
| | | | | | Add enet sleep mode support for imx6sx arm2 platforms. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ASoC: core: Add SOC_DOUBLE_R_S_TLVMarkus Pargmann2014-05-13
| | | | | | | | Add a macro for signed mixer with two registers and tlv array. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit cd21b123346c6a2f033d8c3bd2bf240198b5712a)
* ASoC: core: Add signed register volume control logicMarkus Pargmann2014-05-13
| | | | | | | | | | | | | | | | Some codecs use signed volume control representation with non standard register sizes, e.g. 6 or 7 bit signed integers. This patch adds generic signed register volume control logic to soc-core. Instead of a fixed width signed register control, this implementation uses a 'min' value and the signed bit location to translate it to an absolute volume. Using the 'sign_bit' we can calculate a correct mask for the register values and translate it back into signed integers of standard size. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit f227b88f0fce5f9b82aa934f8829a741c2e06d82)
* serial: imx: Remove init() and exit() platform callbacksAlexander Shiyan2014-04-29
| | | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00310878-1 Asoc: fsl: refine clock tree for ESAIShengjiu Wang2014-04-29
| | | | | | | There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Make the clock for ESAI more clear. Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* tty_ldisc: add more limits to the @write_wakeupHuang Shijie2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the uart_handle_cts_change(), uart_write_wakeup() is called after we call @uart_port->ops->start_tx(). The Documentation/serial/driver tells us: ----------------------------------------------- start_tx(port) Start transmitting characters. Locking: port->lock taken. Interrupts: locally disabled. ----------------------------------------------- So when the uart_write_wakeup() is called, the port->lock is taken by the upper. See the following callstack: |_ uart_write_wakeup |_ tty_wakeup |_ ld->ops->write_wakeup With the port->lock held, we call the @write_wakeup. Some implemetation of the @write_wakeup does not notice that the port->lock is held, and it still tries to send data with uart_write() which will try to grab the prot->lock. A dead lock occurs, see the following log caught in the Bluetooth by uart: -------------------------------------------------------------------- BUG: spinlock lockup suspected on CPU#0, swapper/0/0 lock: 0xdc3f4410, .magic: dead4ead, .owner: swapper/0/0, .owner_cpu: 0 CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.10.17-16839-ge4a1bef #1320 [<80014cbc>] (unwind_backtrace+0x0/0x138) from [<8001251c>] (show_stack+0x10/0x14) [<8001251c>] (show_stack+0x10/0x14) from [<802816ac>] (do_raw_spin_lock+0x108/0x184) [<802816ac>] (do_raw_spin_lock+0x108/0x184) from [<806a22b0>] (_raw_spin_lock_irqsave+0x54/0x60) [<806a22b0>] (_raw_spin_lock_irqsave+0x54/0x60) from [<802f5754>] (uart_write+0x38/0xe0) [<802f5754>] (uart_write+0x38/0xe0) from [<80455270>] (hci_uart_tx_wakeup+0xa4/0x168) [<80455270>] (hci_uart_tx_wakeup+0xa4/0x168) from [<802dab18>] (tty_wakeup+0x50/0x5c) [<802dab18>] (tty_wakeup+0x50/0x5c) from [<802f81a4>] (imx_rtsint+0x50/0x80) [<802f81a4>] (imx_rtsint+0x50/0x80) from [<802f88f4>] (imx_int+0x158/0x17c) [<802f88f4>] (imx_int+0x158/0x17c) from [<8007abe0>] (handle_irq_event_percpu+0x50/0x194) [<8007abe0>] (handle_irq_event_percpu+0x50/0x194) from [<8007ad60>] (handle_irq_event+0x3c/0x5c) -------------------------------------------------------------------- This patch adds more limits to the @write_wakeup, the one who wants to implemet the @write_wakeup should follow the limits which avoid the deadlock. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ENGR00309977-3 ARM: imx6sx: Drop useless IMX6SX_CLK_AUDIO_GATENicolin Chen2014-04-23
| | | | | | | | Since we've fixed the clock's shared-gate issue, we no longer need this gate clock. Thus drop it. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* futex: Allow architectures to skip futex_atomic_cmpxchg_inatomic() testHeiko Carstens2014-04-17
| | | | | | | | | | | | | | If an architecture has futex_atomic_cmpxchg_inatomic() implemented and there is no runtime check necessary, allow to skip the test within futex_init(). This allows to get rid of some code which would always give the same result, and also allows the compiler to optimize a couple of if statements away. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Finn Thain <fthain@telegraphics.com.au> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Link: http://lkml.kernel.org/r/20140302120947.GA3641@osiris Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* ENGR00308770-1 sdma: update platform data for new sdma scriptRobin Gong2014-04-17
| | | | | | update the struct of sdma script platform data. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00307014-05 Add imx6sx vadc gpr register defineSandor Yu2014-04-17
| | | | | | Add imx6sx vadc gpr register define. Signed-off-by: Sandor Yu <R01008@freescale.com>
* usb: phy: move OTG FSM headerAnton Tikhomirov2014-04-16
| | | | | | | | | Other USB drivers may want to use OTG final state machine implementation, so make this header available for them. Signed-off-by: Anton Tikhomirov <av.tikhomirov@samsung.com> Signed-off-by: Felipe Balbi <balbi@ti.com> (cherry-picked from commit 5653668c9585441926dd2575791f6b5bb84bb254)
* ENGR00308060-3 mcc: add sema4 driver required by mccRichard Zhu2014-04-16
| | | | | | | | - add linux sema4 driver, that mandatory required by mcc. - use volatile types in sema4 structure - align the port definiton a9 is 1, m4 is 2. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00308060-2 mcc: implementation mcc on imx6sxRichard Zhu2014-04-16
| | | | | | | | | | | | | | | | | | | - inherited mcc ver 001.002 from vibryd mqx release. - use mu general int4 as the cpu2cpu int (num is 122 at a9 side). - add linux wait_event/wake_up mechanism on the buffer management of share memory - replace wait_event_interruptible### by wait_event###, so the sleep task wouldn't be waken up by reboot or CTRL+C signals. - use the offset address to do the MQX_TO_VIRT and VIRT_TO_MQX exchanges. - regmap_bits_updat can't write 1 to clear the bit-set asr, use regmap_read/write - fix mu irq clear hang issue only do the regmap once in the isr register func, and replace the multi-regmap operations in the kinds of mx6sx mcc related apis by one global imx_mu_reg. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00308060-1 mcc: implementation mcc common on imx6sxRichard Zhu2014-04-16
| | | | | | | | | | | | | - inherited mcc ver 001.002 from vibryd mqx release. - let lwevent related codes mqx specified. - use the offset address to do the MQX_TO_VIRT and VIRT_TO_MQX exchanges. - add some modification in mcc common codes, since all the shm access should be protected by sema4. - double check the list head, and make the recv more robust. Acked-by: Shawn Guo Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00307835-2 ASoC: dmaengine: Add two function for dmaengine_pcmShengjiu Wang2014-04-16
| | | | | | Add check_xrun and device_reset for dmaengine_pcm Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* pwm-backlight: Add optional enable GPIOThierry Reding2014-04-16
| | | | | | | | | | | | | | | To support a wider variety of backlight setups, introduce an optional enable GPIO. Legacy users of the platform data already have a means of supporting GPIOs by using the .init(), .exit() and .notify() hooks. DT users however cannot use those, so an alternative method is required. In order to ease the introduction of the optional enable GPIO, make it available in the platform data first, so that existing users can be converted. Once that has happened a second patch will add code to make use of it in the driver. Signed-off-by: Thierry Reding <treding@nvidia.com> (cherry picked from commit 2b9b1620349e325f184c68cddf3b484499c163c0)
* Input: tsc2007 - add device tree support.Denis Carikli2014-04-16
| | | | | Signed-off-by: Denis Carikli <denis@eukrea.com> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
* ENGR00306442-1 ARM: imx6sx: Merge SPDIF and AUDIO clocks into one gate clockNicolin Chen2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Solo X, SPDIF and AUDIO clocks shares one single gate to switch two entirely different clock routes: SPDIF <-- <---- SPDIF_PODF ----.... \ / gate1 / \ AUDIO <-- <---- AUDIO_PODF ----.... The two audio modules would easily cause conflict during clock operations if running in the same time: SPDIF <-- gate1 <---- SPDIF_PODF ----.... AUDIO <-- gate1 <---- AUDIO_PODF ----.... To keep them safe, we here have to merge them into one gate clock and limit their rates and parent identical: <---- SPDIF_PODF ----.... / SPDIF, AUDIO <-- gate1 \ <---- AUDIO_PODF ----.... [ The only disadvantage of this modification is that we can not separately set a different clock rates and clock sources to SPDIF and AUDIO clock. ] Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00305648-8 dma: imx-sdma: Add SAI script supportNicolin Chen2014-04-16
| | | | | | | This patch adds SAI script support to imx-sdma. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00305648-2 ARM: imx6sx: Add SAI ipg clock to the clock treeNicolin Chen2014-04-16
| | | | | | | There's one clock for SAI memory access missing in the clock tree. Thus add it. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* mtd: nand: fix GET/SET_FEATURES address on 16-bit devicesDavid Mosberger2014-04-16
| | | | | | | | GET_FEATURES and SET_FEATURES also need byte-addressing on 16-bit devices. Signed-off-by: David Mosberger <davidm@egauge.net> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* usb: chipidea: udc: add maximum-speed = full-speed optionMichael Grzeschik2014-04-16
| | | | | | | | | | This patch makes it possible to set the chipidea udc into full-speed only mode. It is set by the oftree property "maximum-speed = full-speed". Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* usb: common: introduce of_usb_get_maximum_speed()Felipe Balbi2014-04-16
| | | | | | | | | | | | this helper will be used for controllers which want to work at a lower speed even though they support higher USB transfer rates. One such case is Texas Instruments' AM437x SoC where it uses a USB3 controller without a USB3 PHY, rendering the controller USB2-only. Signed-off-by: Felipe Balbi <balbi@ti.com>
* ENGR00302472-2 ARM: imx6q: Add imx6sx LDB mux ctrl bit definitionsLiu Ying2014-04-16
| | | | | | | This patch adds LDB mux ctrl bit definitions for imx6sx. The bit DISP_MUX_LDB_MUX_CTRL is defined in the register IOMUXC_GPR5. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-1 ARM: imx6q: Add imx6dl LVDS mux ctrl bit definitionsLiu Ying2014-04-16
| | | | | | | This patch adds LVDS mux ctrl bit definitions for imx6dl. The bits LVDS0/1_MUX_CTL are defined in the register IOMUXC_GPR3. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* regulator: pfuze100: add pfuze200 supportRobin Gong2014-04-16
| | | | | | | | | | | | support pfuze200 chip which remove SW1C and SW4 based on pfuze100. Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit f2518480c7b744296a5587990a54e3a284d932b8) Conflicts: drivers/regulator/pfuze100-regulator.c
* ENGR00303122-3 ARM: imx6sx: fix ASRC related clocks in the clock treeNicolin Chen2014-04-16
| | | | | | | | | | | | | | | | | | According to imx6sx RM, there are three clock providers for ASRC: Module clock Clock root Gate asrck_clock_d spdif0_clk_root N/A ipg_clk ahb_clk_root asrc_clk_enable mem_clk ahb_clk_root asrc_clk_enable while the current clock tree describes a clock named 'ASRC' that only describes the asrc_clk_enable function. Thus this patch first adds the other missing clocks to ASRC. [ Since we don't have the gate for asrck_clock_d, we can pass spdif0_clk to ASRC in the devicetree directly. ] Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00303122-1 mxc: asrc: Fix asrc clocks managementNicolin Chen2014-04-16
| | | | | | | | | | | | | ASRC needs three clocks from SoC, they are: mem_clk: Peripheral access clock ipg_clk: Peripheral clock asrck_clk: ASRC module clock while the current driver only maintains two of them and has confusing clock names. Thus fix it. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00302235-2 arm: enable pcie on imx6sxRichard Zhu2014-04-16
| | | | | | | | | - add mandatory pcie related clks in imx6sx clks tree - add pcie dts in imx6sx dts - add pcie kconfig option in imx6sx soc config - add pcie regulate into dts Signed-off-by: Richard Zhu <r65037@freescale.com>
* mtd: nand: add "page" argument for read_subpage hookHuang Shijie2014-04-16
| | | | | | | | | Add the "page" argument for the read_subpage hook. With this argument, the implementation of this hook could prints out more accurate information for debugging. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* sched: replace INIT_COMPLETION with reinit_completionWolfram Sang2014-04-16
| | | | | | | | | | | | | | | | | | For the casual device driver writer, it is hard to remember when to use init_completion (to init a completion structure) or INIT_COMPLETION (to *reinit* a completion structure). Furthermore, while all other completion functions exepct a pointer as a parameter, INIT_COMPLETION does not. To make it easier to remember which function to use and to make code more readable, introduce a new inline function with the proper name and consistent argument type. Update the kernel-doc for init_completion while we are here. Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> (personally at LCE13) Cc: Ingo Molnar <mingo@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Luwei Zhou <b45643@freescale.com>
* iio: core: implement devm_iio_device_alloc/devm_iio_device_freeGrygorii Strashko2014-04-16
| | | | | | | | | | | | | | | | | | Add a resource managed devm_iio_device_alloc()/devm_iio_device_free() to automatically clean up any allocations made by IIO drivers, thus leading to simplified IIO drivers code. In addition, this will allow IIO drivers to use other devm_*() API (like devm_request_irq) and don't care about the race between iio_device_free() and the release of resources by Device core during driver removing. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Oleksandr Kravchenko <o.v.kravchenko@globallogic.com> Tested-by: Oleksandr Kravchenko <o.v.kravchenko@globallogic.com> Reviewed-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org> Signed-off-by: Luwei Zhou <b45643@freescale.com>
* of_mtd: Add helpers to get ECC strength and ECC step sizeEzequiel Garcia2014-04-16
| | | | | | | | | | | This commit adds simple helpers to obtain the devicetree properties that specify the ECC strength and ECC step size to use on a given NAND controller. Acked-by: Boris BREZILLON <b.brezillon.dev@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: Add a retlen parameter to _get_{fact,user}_prot_infoChristian Riesch2014-04-16
| | | | | | | Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* of_mtd: fix header file include guardPhilipp Rosenberger2014-04-16
| | | | | | | | It seems the include guard was copied from of_net.h. Signed-off-by: Philipp Rosenberger <philipp.rosenberger@xse.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* of_mtd: Add no-op stubs to support CONFIG_OF=nEzequiel Garcia2014-04-16
| | | | | | | | | | | | | Just like the rest of the subsystems, let's add the required no-op functions to implement stubs when CONFIG_OF=n. This prevents MTD drivers from having ugly ifdefs in their code, and instead hide the ifdef monster in the header closet (far away from people's sight). Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00301552-1 ARM: imx6sx: Correct audio_clk in the clock treeNicolin Chen2014-04-16
| | | | | | | | | | | | | We currently has asrc_* clocks in the imx6sx clock tree while actually, according to the Reference Manual, all of them should be named after the audio_clk that controls the external MCLK output from MCLK pad of AUDMUX. Thus fix it along with its gate clock missing in the current clock tree. Meanwhile, this patch also configures a default clock rate for it -- 24MHz. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00300430-5 mtd: spi-nor: add a helper to find the spi_device_idHuang Shijie2014-04-16
| | | | | | | Add the spi_nor_match_id() to find the proper spi_device_id with the NOR flash's name in the spi_nor_ids table. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-3 mtd: spi-nor: add the framework for SPI NORHuang Shijie2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cloned most of the m25p80.c. In theory, it adds a new spi-nor layer. Before this patch, the layer is like: MTD ------------------------ m25p80 ------------------------ spi bus driver ------------------------ SPI NOR chip After this patch, the layer is like: MTD ------------------------ spi-nor ------------------------ m25p80 ------------------------ spi bus driver ------------------------ SPI NOR chip With the spi-nor controller driver(Freescale Quadspi), it looks like: MTD ------------------------ spi-nor ------------------------ fsl-quadspi ------------------------ SPI NOR chip New APIs: spi_nor_scan: used to scan a spi-nor flash. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-2 mtd: spi-nor: add the basic data structuresHuang Shijie2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The spi_nor{} is cloned from the m25p{}. The spi_nor{} can be used by both the m25p80 and spi-nor controller. We also add the spi_nor_xfer_cfg{} which can be used by the two fundamental primitives: read_xfer/write_xfer. 1) the hooks for spi_nor{}: @prepare/unpreare: used to do some work before or after the read/write/erase/lock/unlock. @read_xfer/write_xfer: We can use these two hooks to code all the following hooks if the driver tries to implement them by itself. @read_reg: used to read the registers, such as read status register, read configure register. @write_reg: used to write the registers, such as write enable, erase sector. @read_id: read out the ID info. @wait_till_ready: wait till the NOR becomes ready. @read: read out the data from the NOR. @write: write data to the NOR. @erase: erase a sector of the NOR. 2) Add a new field sst_write_second for the SST NOR write. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-1 mtd: spi-nor: copy the SPI NOR commands to a new header fileHuang Shijie2014-04-16
| | | | | | | | | | This patch adds a new header :spi-nor.h, and copies all the SPI NOR commands and relative macros into this new header. This hearder can be used by the m25p80.c and other spi-nor controller, such as Freescale's Quadspi. Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: mux: Add support for read-only muxes.Tomasz Figa2014-04-16
| | | | | | | | | | | Some platforms have read-only clock muxes that are preconfigured at reset and cannot be changed at runtime. This patch extends mux clock driver to allow handling such read-only muxes by adding new CLK_MUX_READ_ONLY mux flag. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-07 05:41:10 -0400