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* clk: mux: add CLK_MUX_HIWORD_MASKHaojian Zhuang2014-04-16
| | | | | | | | | | | | | | | | In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as switching mux, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds mux flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: divider: add CLK_DIVIDER_HIWORD_MASK flagHaojian Zhuang2014-04-16
| | | | | | | | | | | | | | | | In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as setting divider, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds divider flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: clk-mux: implement remuxing on set_rateJames Hogan2014-04-16
| | | | | | | | | | | | | | | | | Implement clk-mux remuxing if the CLK_SET_RATE_NO_REPARENT flag isn't set. This implements determine_rate for clk-mux to propagate to each parent and to choose the best one (like clk-divider this chooses the parent which provides the fastest rate <= the requested rate). The determine_rate op is implemented as a core helper function so that it can be easily used by more complex clocks which incorporate muxes. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes being reparented during clk_set_rate. To avoid breaking existing platforms, all callers of clk_register_mux() are adjusted to pass the new flag. Platform maintainers are encouraged to remove the flag if they wish to allow mux reparenting on set_rate. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Chao Xie <xiechao.mail@gmail.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Andrew Chew <achew@nvidia.com> Cc: Doug Anderson <dianders@chromium.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Tomasz Figa <t.figa@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: spear-devel@list.st.com Cc: linux-tegra@vger.kernel.org Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> [tegra] Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi] Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq] Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: add support for clock reparent on set_rateJames Hogan2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add core support to allow clock implementations to select the best parent clock when rounding a rate, e.g. the one which can provide the closest clock rate to that requested. This is by way of adding a new clock op, determine_rate(), which is like round_rate() but has an extra parameter to allow the clock implementation to optionally select a different parent clock. The core then takes care of reparenting the clock when setting the rate. The parent change takes place with the help of some new private data members. struct clk::new_parent specifies a clock's new parent (NULL indicates no change), and struct clk::new_child specifies a clock's new child (whose new_parent member points back to it). The purpose of these are to allow correct walking of the future tree for notifications prior to actually reparenting any clocks, specifically to skip child clocks who are being reparented to another clock (they will be notified via the new parent), and to include any new child clock. These pointers are set by clk_calc_subtree(), and the new_child pointer gets cleared when a child is actually reparented to avoid duplicate POST_RATE_CHANGE notifications. Each place where round_rate() is called, determine_rate() is checked first and called in preference. This restructures a few of the call sites to simplify the logic into if/else blocks. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: abstract parent cacheJames Hogan2014-04-16
| | | | | | | | | | | | | Abstract access to the clock parent cache by defining clk_get_parent_by_index(clk, index). This allows access to parent clocks from clock drivers. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: parse out the JEDEC compliant NANDHuang Shijie2014-04-16
| | | | | | | | | | This patch adds the parsing code for the JEDEC compliant NAND. Since we need the 0x40 as the column address, this patch also makes the NAND_CMD_PARAM to use the 8-bit address only. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: add a helper to get the supported features for JEDECHuang Shijie2014-04-16
| | | | | | | | Add a helper to get the supported features for JEDEC compliant NAND. Also add a macro JEDEC_FEATURE_16_BIT_BUS. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: add fields for JEDEC in nand_chipHuang Shijie2014-04-16
| | | | | | | | Add the jedec_version field, and add an anonymous union which contains the nand_onfi_params and nand_jedec_params. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: add the data structures for JEDEC parameter pageHuang Shijie2014-04-16
| | | | | | | | Create the nand_jedec_params{} and jedec_ecc_info{} according to the JESD230A (Revision of JESD230, October 2012). Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* ASoC: dai: Provide interface for setting DMA data at probe timeMark Brown2014-04-16
| | | | | | | | | | Allow DMA data to be set at probe time for devices that can do that, avoiding the need to do it every time we start a stream and supporting non-DT dmaengine users using the helpers. Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit ecfc0c04f236f1e2a95094792ec10cf27be39f7c) Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ASoC: Add resource managed snd_dmaengine_pcm_register()Lars-Peter Clausen2014-04-16
| | | | | | | | | | | | | For many drivers using the generic dmaengine PCM driver one of the few (or the only) things left to do in the drivers remove function is to unregister the PCM device. This patch adds a resource managed version of snd_dmaengine_pcm_register() which makes it possible to simplify the remove function as well as the error path in the probe function for those drivers. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 21585ee848078b12d0d1a513e93936bf96b444a0) Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ASoC: core: Add devm_snd_soc_register_card()Mark Brown2014-04-16
| | | | | | | | | | Simplify error handling and remove repetitive (and rarely executed) code for unregistration by providing a devm_snd_soc_register() card. Signed-off-by: Mark Brown <broonie@linaro.org> Acked-by: Liam Girdwood <liam.r.girdwood@linux.intel.com> (cherry picked from commit 0e4ff5c806263bf40ee5409ac283b776f0c11e41) Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ASoC: core: Implement devm_snd_soc_register_component()Mark Brown2014-04-16
| | | | | | | | | | Since with the wider use of devres many drivers are now only calling snd_soc_unregister_component() in their remove functions providing a managed version will save a reasonable amount of code. Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit a0b03a616b08cf9d709812ff5cf7e9c0958d6807) Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00299323-13 ARM:imx:imx6sx: add enet init for imx6sx platformFugang Duan2014-04-16
| | | | | | | | | - Init GPR1 register to select enet1 and enet2 refrence clock from internal PLL. - Add enet MAC address checking from fuse. - Add some phy fixup, set RGMII IO voltage to 1.8V. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00299323-11 ARM: imx: Add i.mx6sx enet clk supportFugang Duan2014-04-16
| | | | | | | | | Add i.mx6sx enet clk support: - Add enet2 refrence clock. - Add PTP clock. - Set enet system AHB clock to 200Mh. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00298524-2 ARM: imx: Add MSL support for i.mx6sxAnson Huang2014-04-16
| | | | | | | | | | | | | | It adds initial MSL support for i.mx6sx, including below features: 1. add cpu type check; 2. add system timer support; 3. add clock tree support; 4. add machine layer init support; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> Acked-by: Jason Liu
* mtd: nand: fix misspelling in ONFI parameter field nameBrian Norris2014-04-16
| | | | | | | | | s/strenght/strength/ This field isn't used anywhere, so this rename is safe. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: force NAND_CMD_READID onto 8-bit busBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | | | The NAND command helpers tend to automatically shift the column address for x16 bus devices, since most commands expect a word address, not a byte address. The Read ID command, however, expects an 8-bit address (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or 0x20). This fixes the column address for a few drivers which imitate the nand_base defaults. Note that I don't touch sh_flctl.c, since it already handles this problem slightly differently (note its comment "READID is always performed using an 8-bit bus"). I have not tested this patch, as I only have x8 parts up for testing at this point. Hopefully that can change soon... Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-By: Pekon Gupta <pekon@ti.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: remove the NAND_MAX_PAGESIZE/NAND_MAX_OOBSIZEHuang Shijie2014-04-16
| | | | | | | | | There is no reference to these two macros now. Just remove them. Signed-off-by: Huang Shijie <shijie8@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: kill the the NAND_MAX_PAGESIZE/NAND_MAX_OOBSIZE for nand_buffers{}Huang Shijie2014-04-16
| | | | | | | | | | | | | | | | | The patch converts the arrays to buffer pointers for nand_buffers{}. The cafe_nand.c is the only NAND_OWN_BUFFERS user which allocates nand_buffers{} itself. This patch disables the DMA for nand_scan_ident, and restores the DMA status after we finish the nand_scan_ident. This way, we can get page size and OOB size and use them to allocate cafe->dmabuf. Since the cafe_nand.c uses the NAND_ECC_HW_SYNDROME ECC mode, we do not allocate the buffers for @ecccalc and @ecccode. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: add Intel manufacturer IDHuang Shijie2014-04-16
| | | | | | | | | Add the Intel manufacturer Id. Tested with Intel JS29F32G08ACMD1(4096 + 224) which is ONFI 2.0 compliant nand. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: add SanDisk manufacturer IDHuang Shijie2014-04-16
| | | | | | | | Add the manufactor ID for SanDisk. Make preparation for SanDisk SDTNRGAMA-008G. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: don't use {read,write}_buf for 8-bit transfersUwe Kleine-König2014-04-16
| | | | | | | | | | | | | | | | | | | According to the Open NAND Flash Interface Specification (ONFI) Revision 3.1 "Parameters are always transferred on the lower 8-bits of the data bus." for the Get Features and Set Features commands. So using read_buf and write_buf is wrong for 16-bit wide nand chips as they use I/O[15:0]. The Get Features command is easily fixed using 4 times the read_byte callback. For Set Features implement a new overwritable callback "write_byte". Still I expect the default to work just fine for all controllers and making it overwriteable was just done for symmetry. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> [Brian: fixed warning] Tested-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: use __packed shorthandBrian Norris2014-04-16
| | | | | | | | | To be consistent with the rest of include/linux/mtd/nand.h, we should use the __packed shorthand instead of __attribute__((packed)). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: support Micron READ RETRYBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Micron provides READ RETRY support via the ONFI vendor-specific parameter block (to indicate how many read-retry modes are available) and the ONFI {GET,SET}_FEATURES commands with a vendor-specific feature address (to support reading/switching the current read-retry mode). The recommended sequence is as follows: 1. Perform PAGE_READ operation 2. If no ECC error, we are done 3. Run SET_FEATURES with feature address 89h, mode 1 4. Retry PAGE_READ operation 5. If ECC error and there are remaining supported modes, increment the mode and return to step 3. Otherwise, this is a true ECC error. 6. Run SET_FEATURES with feature address 89h, mode 0, to return to the default state. This patch implements the chip->setup_read_retry() callback for Micron and fills in the chip->read_retries. Tested on Micron MT29F32G08CBADA, which supports 8 read-retry modes. The Micron vendor-specific table was checked against the datasheets for the following Micron NAND: Needs retry Cell-type Part number Vendor revision Byte 180 ----------- --------- ---------------- --------------- ------------ No SLC MT29F16G08ABABA 1 Reserved (0) No MLC MT29F32G08CBABA 1 Reserved (0) No SLC MT29F1G08AACWP 1 0 Yes MLC MT29F32G08CBADA 1 08h Yes MLC MT29F64G08CBABA 2 08h Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: add generic READ RETRY supportBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modern MLC (and even SLC?) NAND can experience a large number of bitflips (beyond the recommended correctability capacity) due to drifts in the voltage threshold (Vt). These bitflips can cause ECC errors to occur well within the expected lifetime of the flash. To account for this, some manufacturers provide a mechanism for shifting the Vt threshold after a corrupted read. The generic pattern seems to be that a particular flash has N read retry modes (where N = 0, traditionally), and after an ECC failure, the host should reconfigure the flash to use the next available mode, then retry the read operation. This process repeats until all bitfips can be corrected or until the host has tried all available retry modes. This patch adds the infrastructure support for a vendor-specific/flash-specific callback, used for setting the read-retry mode (i.e., voltage threshold). For now, this patch always returns the flash to mode 0 (the default mode) after a successful read-retry, according to the flowchart found in Micron's datasheets. This may need to change in the future if it is determined that eventually, mode 0 is insufficient for the majority of the flash cells (and so for performance reasons, we should leave the flash in mode 1, 2, etc.). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: add ONFI vendor block for MicronBrian Norris2014-04-16
| | | | | | Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* ASoC: soc-pcm: add symmetry for channels and sample bitsNicolin Chen2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SoCs can only work in mono or stereo mode at one time. So if we let them capture a mono stream while playing a stereo stream, there might be a problem occur to one of these two streams: double paced or slowed down. In soc-pcm.c, we have soc_pcm_apply_symmetry() to apply the rate symmetry. But we don't have one for channels. Likewise, we can treat symmetric_rate as a solution for those SoCs or CODECs which can not handle asymmetrical LRCLK. But it's also impossible for them to handle asymmetrical BCLK. And accodring to BCLK = LRCLK * channel number * slot size(fixed or sample bits), sample bits might also be a problem if they are not using a fixed slot size. Thus, this patch applys symmetry for channels and sample bits. Meanwhile, there might be a race between two substreams if starting simultaneously. Previously, we only added warning to compalin but still using conservative way to let it carry on. However, this patch rejects the second stream with any unmatched parameter to make sure the first existing stream won't be broken. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 3635bf09a89cf92b80ac44198c5c8f0989624ea6)
* ENGR00292408-1 usb: chipidea: add query_available_role interfacePeter Chen2014-04-16
| | | | | | | The glue layer may need to know current available role, add ci_hdrc_query_available_role for that. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00291282-4 usb: chipidea: imx: add HSIC supportPeter Chen2014-04-16
| | | | | | Add imx6 HSIC support Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00293323 PXP: add WC and cacheable dma buffer support for PXP deviceFancy Fang2014-04-16
| | | | | | | | | This change add support for new dma buffer type(writecombine and cacheable) which allows user application has more choices for the buffer type. And if the dma buffer is cacheable, then add flush interfaces to make it cache coherent when necessary. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00293234 PXP: let irq_pending variable to be atomicFancy Fang2014-04-16
| | | | | | | Change irq_pending field in struct pxp_irq_info to a atomic type. So the spin lock in pxp_irq_info is unnecessary. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00293211 PXP: bind allocated DMA channels to opened device file descriptorFancy Fang2014-04-16
| | | | | | | | | | | The allocated DMA channels via some opened file descriptor is better to be bound to this descriptor. Since this can avoid some application to fake a channel id which may be requested by other applications to request PXP service. And also, this make it easier to release the dma channel when application exists abnormally or forgets to release it explicitly. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00293170 PXP: remove cpu_addr field from struct pxp_mem_descFancy Fang2014-04-16
| | | | | | | | | | The cpu_addr field in struct pxp_mem_desc cannot be used by user application, so it is not necessary to pass this field data to user. Now the similar field 'virtual' in struct pxp_buf_obj is used to store the kernel space virtual addr for allocated dma buffer. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00293119 PXP: change the dma buffer lists management for PXP deviceFancy Fang2014-04-16
| | | | | | | | | Create pxp_info struct data for each opened device file descriptor. And bind all the allocated dma buffers to this struct for each opened file. This makes the dma buffer lists management safer, more effective and more flexible. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00292816 PXP: move two struct definitions to pxp_device.hFancy Fang2014-04-16
| | | | | | | | Move two struct definitions defined in pxp_device.c to pxp_device.h. Now the pxp_device.h has been created for PXP device driver. So all the type definition should stay in header file not c source file. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00292775 mipi csi2: Refine register accessLiu Ying2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | The original mipi csi2 driver uses readl()/writel() to access the 32 bit mipi csi2 registers in the following way where info->mipi_csi2_base is a pointer which points to a 32 bit I/O memory cell of the mipi csi2's base address: writel(value, info->mipi_csi2_base + offset); readl(info->mipi_csi2_base + offset); This makes the register offset values shrink 4 times, comparing to the offset values documented in the reference manual. For example, we need to change the offset value from 0x004 to 0x001 so that we may access the register MIPI_CSI2_N_LANES correctly. This patch redefines the type of info->mipi_csi2_base to 'void __iomem *', then the offset values can be the same to what they are documented. Also, the macro names for the registers are aligned to the documentation. Acked-by: Robby Cai <R63905@freescale.com> Cc: Oliver Brown <oliver.brown@freescale.com> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00292562 PXP: move the definitions used only by PXP device to a new ↵Fancy Fang2014-04-16
| | | | | | | | | | header file Some definitions used only by PXP device driver should not stay in pxp_dma.h which is shared by PXP, EPDC and V4L2. So the patch creates a new header file pxp_device.h to hold these definitions. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00292121 PXP: remove __u32 definition in pxp_dma.hFancy Fang2014-04-16
| | | | | | | | Remove the __u32 macro definition in pxp_dma.h. But include <linux/types.h> in pxp_dma.h to make sure user application which include pxp_dma.h to be compiled with no error. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00291731 PXP: move pxp_irq_info definition from PXP dma to PXP deviceFancy Fang2014-04-16
| | | | | | | | struct pxp_irq_info is only used by PXP device driver, so it is unreasonable to define it in pxp_dma.h which will be included by EPDC, V4L2 PXP and PXP device driver. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00291729 PXP: remove a mutex lock from pxp channelFancy Fang2014-04-16
| | | | | | | | | This mutex lock is no longer necessary in PXP dma driver. After the commit "ENGR00291400 PXP: Organize PXP task queue to be FIFO", protection fields can be protected by the spin lock in PXP channel now. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00291658 PXP: allow PXP device users to submit multiple tasks before ↵Fancy Fang2014-04-16
| | | | | | | | | | | | start PXP After the commit "ffcad666548417ef21937e0a755d85ab922313a9" pushed, adding this support in PXP device driver is also necessary. This change allows users to submit more than one PXP tasks followd by only one wait for finished ioctl. It means that users can wait for more than one tasks done by calling one PXP_IOC_WAIT4CMPLT ioctl. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00291400 PXP: Organize PXP task queue to be FIFOFancy Fang2014-04-16
| | | | | | | | | | | | The requested PXP tasks were handled based on channel unit. All the tasks in one channel were handled one by one, and the tasks in another channel only can get chance after all the tasks in previous channel were finished. So this may allow some channel occupies PXP hardware exclusively all the time, and other channels may never get PXP services. So this change makes the PXP task queue to be a FIFO to avoid this kind of unfair usage for PXP. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00290664 PXP: allocate DMA TX descriptors on demand instead of in PXP ↵Fancy Fang2014-04-16
| | | | | | | | | | | | | initialization In previous PXP driver, the number of tx descriptors allocated for each channel is a constant 16 and they can only be allocated during PXP initialization. But since the driver allows users to queue more than one PXP tasks for each channel before issuing pending tasks, so in this case the descriptors may be not enough for some cases. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00290361-1 IPUv3 IC:Add check for a IDMAC errataLiu Ying2014-04-16
| | | | | | | | | | | The IPUv3 IDMAC has a bug to read 32bpp pixels from a graphics plane whose alpha component is at the most significant 8 bits. The bug only impacts on cases in which the relevant separate alpha channel is enabled. This patch adds check for the errata so that the bad cases won't be triggered. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00289643-1 arm: imx6sl: add missing spba clock to clock treeNicolin Chen2014-04-16
| | | | | | | | We are missing spba clock in imx6sl's clock tree, thus add it. Acked-by: Wang Shengjiu <b02247@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00289406-1 mmc: sdhci: add quirk for get max timeout counterDong Aisheng2014-04-16
| | | | | | | | | The max timeout counter of some SoCs like i.MX6 uSDHC may not be standard, add SDHCI_QUIRK2_NOSTD_TIMEOUT_COUNTER quirk to get the correct max timeout counter from platform specific code. Then we can calculate the correct max_discard_to value. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00284411-1 PXP: Enhance YUV, alpha blend and rotationFancy Fang2014-04-16
| | | | | | | | Support YUV formats like: I420, NV12, NV21, UYVY, YUYV, VYUY, YVYU, NV16, NV61 and YV12. Support rotation in both stages before and after alpha blending. Signed-off-by: Fancy Fang <B47543@freescale.com>
* of: pci: add registry of MSI chipsThomas Petazzoni2014-04-16
| | | | | | | | | | | This commit adds a very basic registry of msi_chip structures, so that an IRQ controller driver can register an msi_chip, and a PCIe host controller can find it, based on a 'struct device_node'. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-07 07:04:48 -0400