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* PCI: use weak functions for MSI arch-specific functionsThomas Petazzoni2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, the MSI architecture-specific functions could be overloaded using a fairly complex set of #define and compile-time conditionals. In order to prepare for the introduction of the msi_chip infrastructure, it is desirable to switch all those functions to use the 'weak' mechanism. This commit converts all the architectures that were overidding those MSI functions to use the new strategy. Note that we keep two separate, non-weak, functions default_teardown_msi_irqs() and default_restore_msi_irqs() for the default behavior of the arch_teardown_msi_irqs() and arch_restore_msi_irqs(), as the default behavior is needed by x86 PCI code. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Tested-by: Daniel Price <daniel.price@gmail.com> Tested-by: Thierry Reding <thierry.reding@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: linuxppc-dev@lists.ozlabs.org Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: linux390@de.ibm.com Cc: linux-s390@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: x86@kernel.org Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Luck <tony.luck@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: linux-ia64@vger.kernel.org Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: David S. Miller <davem@davemloft.net> Cc: sparclinux@vger.kernel.org Cc: Chris Metcalf <cmetcalf@tilera.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* PCI: Allocate only as many MSI vectors as requested by driverAlexander Gordeev2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Because of the encoding of the "Multiple Message Capable" and "Multiple Message Enable" fields, a device can only advertise that it's capable of a power-of-two number of vectors, and the OS can only enable a power-of-two number. For example, a device that's limited internally to using 18 vectors would have to advertise that it's capable of 32. The 14 extra vectors consume vector numbers and IRQ descriptors even though the device can't actually use them. This fix introduces a 'msi_desc::nvec_used' field to address this issue. When non-zero, it is the actual number of MSIs the device will send, as requested by the device driver. This value should be used by architectures to set up and tear down only as many interrupt resources as the device will actually use. Note, although the existing 'msi_desc::multiple' field might seem redundant, in fact it is not. The number of MSIs advertised need not be the smallest power-of-two larger than the number of MSIs the device will send. Thus, it is not always possible to derive the former from the latter, so we need to keep them both to handle this case. [bhelgaas: changelog, rename to "nvec_used"] Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* ARM: imx6q: Add PCIe bits to GPR syscon definitionSean Cross2014-04-16
| | | | | | | | | PCIe requires additional bits be defined for GPR8 and GPR12. Signed-off-by: Sean Cross <xobs@kosagi.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> (cherry picked from commit 8d6a35fb13406f87d926fffeee0d70360ce3077d)
* ENGR00288567 Revert "ENGR00275213-2 ARM: imx6q: update the pcie bits ↵Richard Zhu2014-04-16
| | | | | | | | | | definitions of gpr" switch to community upstreamed pcie driver. Revert "ENGR00275213-2 ARM: imx6q: update the pcie bits definitions of gpr" This reverts commit 0ddad708c7484a8b5d2016d31fda2bd8b9b8f275. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00287992-4 usb: chipidea: Add usb charger detect notifyPeter Chen2014-04-16
| | | | | | | | | | | | | - Change .notify's return value from void to int. - Add CI_HDRC_CONTROLLER_CHARGER_EVENT and CI_HDRC_CONTROLLER_CHARGER_POST_EVENT to finish the USB charger detection flow. - Add usb_gadget_vbus_connect for only notify udc when vbus is on, the main reason we add it is we don't want the first notification when the vbus is off, it causes the dev->power.usage_count equals -1 when do charger detection. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00287992-1 power: imx6: add imx6 USB charger detectionPeter Chen2014-04-16
| | | | | | | | | | | | | | | | | | Add imx6 USB charger detection, the vbus supplier will create and remove struct usb_charger, and notify vbus connect and disconnect event. The detail USB charger detection flow is at: "i.MX6 RM, Chapter Universal Serial Bus 2.0 Integrated PHY (USB-PHY), Charger detection, Charger detection software flow". Since imx6 only has charger detection function, and no charging current function is existed. It the user wants the detection abilities from SoC, it can use this detection method (add imx6-usb-charger-detection at dts). If the charger IC already has USB charger detection function, and the user wants to use the detection method from charger IC, please do not add imx6-usb-charger-detection property at dts. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00287256 mxc: mlb: Fix the SYNC mode hang issue when connected with MITBLuwei Zhou2014-04-16
| | | | | | | | | | | This patch fixes the hang and crash issue of MLB SYNC mode in the driver. The MITB will casue Sabreauto to hang and crash when testing the SYNC mode. It is because MITB will cause something error on MLB bus when stopping the SYNC test. The Sabreauto will keep entering error ISR and hang. Since we don't know the details about MITB, we make drivers provide IO_CTRL interface to disable the interrupt in SYNC mode. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* mmc: sdhci: fix caps2 for HS200Giuseppe CAVALLARO2014-04-16
| | | | | | | | | | | | | | Although the HC supports HS200 (eMMC) the caps2 are always zero; this means there's no way to use the super speed mode (when init the card). If the HC support SDR104, for SD3.0, so it also supports HS200 for eMMC and this patch just sets the MMC_CAP2_HS200 in the host caps2 field. Reported-by: Youssef Triki <youssef.triki@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Reviewed-by: Philip Rakity <prakity@nvidia.com> Signed-off-by: Chris Ball <cjb@laptop.org> (cherry picked from commit 156e14b126ffb6f040bc6f1aff3c51077e42a744)
* mmc: sdhci: add ability to stay runtime-resumed if the card is powered upAdrian Hunter2014-04-16
| | | | | | | | | | | If card power is dependent on SD bus power then the host controller must not be runtime suspended while the card is powered up. Add the ability to stay runtime-resumed in that case and enable it with a new quirk SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Chris Ball <cjb@laptop.org> (cherry picked from commit f0710a557cb17746b09234f01073a2cdafe4f4a5)
* ENGR00286971-4 Revert "ENGR00278504-1 mmc: sdhci: add quirk for broken acmd23"Dong Aisheng2014-04-16
| | | | | | | | | The ACMD23 unwork issue is fixed now. so the former quirk to disable ACMD23 can be removed. This reverts commit fd27fce042bfd289eab6dbb7c98ab3adb48ca25b. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00286426-21 usb: chipidea: host: add ehci quirk for imx controllerPeter Chen2014-04-16
| | | | | | | | When the port goes to suspend or finishes resme, it needs to notify PHY, it is not a standard EHCI operation, so we add a quirk for it. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00286426-13 usb: chipidea: Add power management supportPeter Chen2014-04-16
| | | | | | | | This commit adds runtime and system power management support for chipidea core. The runtime pm support is controlled by glue layer, it can be enabled by flag CI_HDRC_SUPPORTS_RUNTIME_PM. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00286426-10 usb: phy: Add set_wakeup APIPeter Chen2014-04-16
| | | | | | | | This API is used to set wakeup enable at PHY registers, in that case, the PHY can be waken up from suspend due to external events, like vbus change, dp/dm change and id change. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00286426-7 usb: phy: add notify suspend and resume callbackPeter Chen2014-04-16
| | | | | | | They are used to notify PHY that the controller enters suspend or finishes resume. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00286159-1 usb: chipidea: add freescale imx28 special write register methodPeter Chen2014-04-16
| | | | | | | | | | | | According to Freescale imx28 Errata, "ENGR119653 USB: ARM to USB register error issue", All USB register write operations must use the ARM SWP instruction. So, we implement special hw_write and hw_test_and_clear for imx28. Discussion for it at below: http://marc.info/?l=linux-usb&m=137996395529294&w=2 Signed-off-by: Peter Chen <peter.chen@freescale.com>
* lib/genalloc: add a helper function for DMA buffer allocationNicolin Chen2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | When using pool space for DMA buffer, there might be duplicated calling of gen_pool_alloc() and gen_pool_virt_to_phys() in each implementation. Thus it's better to add a simple helper function, a compatible one to the common dma_alloc_coherent(), to save some code. Signed-off-by: Nicolin Chen <b42378@freescale.com> Cc: "Hans J. Koch" <hjk@hansjkoch.de> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Eric Miao <eric.y.miao@gmail.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Haojian Zhuang <haojian.zhuang@gmail.com> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Liam Girdwood <lgirdwood@gmail.com> Cc: Mark Brown <broonie@kernel.org> Cc: Mauro Carvalho Chehab <m.chehab@samsung.com> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Takashi Iwai <tiwai@suse.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
* ENGR00286149-5: Revert "ENGR00277805-6"Peter Chen2014-04-16
| | | | | | This reverts commit 4e9bcf000f717cd17faef109eb6874f3d6323cea. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* mtd: nand_bbt: kill NAND_BBT_SCANALLPAGESBrian Norris2014-04-16
| | | | | | | | | | Now that the last user of NAND_BBT_SCANALLPAGES has been removed, let's kill this peculiar BBT feature flag. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: add a helper to detect the nand typeHuang Shijie2014-04-16
| | | | | | | | | | | This helper detects that whether the mtd's type is nand type. Now, it's clear that the MTD_NANDFLASH stands for SLC nand only. So use the mtd_type_is_nand() to replace the old check method to do the nand type (include the SLC and MLC) check. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: add data structures for Extended Parameter PageHuang Shijie2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | Since the ONFI 2.1, the onfi spec adds the Extended Parameter Page to store the ECC info. The onfi spec tells us that if the nand chip's recommended ECC codeword size is not 512 bytes, then the @ecc_bits is 0xff. The host _SHOULD_ then read the Extended ECC information that is part of the extended parameter page to retrieve the ECC requirements for this device. This patch adds [1] the neccessary fields for nand_onfi_params{}, [2] and adds the onfi_ext_ecc_info{} for Extended ECC information, [3] adds onfi_ext_section{} for extended sections, [4] and adds onfi_ext_param_page{} for the Extended Parameter Page. Acked-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Huang Shijie <b32955@freescale.com> Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com> [Brian: amended for checkpatch.pl] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: add a new ecc_step_size field to mtd_info{}Huang Shijie2014-04-16
| | | | | | | | | | | | | | | | | | | In order to implement the NAND boot for some Freescale's chips, such as imx23/imx28/imx50/imx6, we use a tool (called kobs-ng) to burn the uboot and some metadata to nand chip. And the ROM code will use the metadata to configrate the BCH, and to find the uboot. The ECC information(ecc step size, ecc strength) which is used to configrure the BCH is part of the metadata. The kobs-ng can get the ecc strength from the sys node /sys/*/ecc_strength now. But it can not get the ecc step size. This patch adds a new field to store the ecc step size in mtd_info{}, and it makes preparation for the next patches. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: rename the cellinfo to bits_per_cellHuang Shijie2014-04-16
| | | | | | | | | | | | | | | | | | | The @cellinfo fields contains unused information, such as write caching, internal chip numbering, etc. But we only use it to check the SLC or MLC. This patch tries to make it more clear and simple, renames the @cellinfo to @bits_per_cell. In order to avoiding the bisect issue, this patch also does the following changes: (0) add a macro NAND_CI_CELLTYPE_SHIFT to avoid the hardcode. (1) add a helper to parse out the cell type : nand_get_bits_per_cell() (2) parse out the cell type for extended-ID chips and the full-id nand chips. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: remove obsolete 'ecclayout' fieldBrian Norris2014-04-16
| | | | | | | This field is never used, except to print it out. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: add ECC info for nand_flash_dev{}Huang Shijie2014-04-16
| | | | | | | | | | | | | | | Add an instance of an anonymous struct to store the ECC info for full id nand chips. @ecc.strength_ds: ECC correctability from the datasheet. @ecc.step_ds: ECC size required by the @ecc.strength_ds, These two fields are all from the datasheet. Also add the necessary macros to make the code simple and clean. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: add a helper to get the supported features for ONFI nandHuang Shijie2014-04-16
| | | | | | | | | | add a helper to get the supported features for ONFI nand. Also add the neccessary macros. Signed-off-by: Huang Shijie <b32955@freescale.com> Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: add datasheet's ECC information to nand_chip{}Huang Shijie2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1.) Why add the ECC information to the nand_chip{} ? Each nand chip has its requirement for the ECC correctability, such as "4bit ECC for each 512Byte" or "40bit ECC for each 1024Byte". This ECC info is very important to the nand controller, such as gpmi. Take the Micron MT29F64G08CBABA for example, its geometry is 8KiB page size, 744 bytes oob size and it requires 40bit ECC per 1KiB. If we do not provide the ECC info to the gpmi nand driver, it has to calculate the ECC correctability itself. The gpmi driver will gets the 56bit ECC for per 1KiB which is beyond its BCH's 40bit ecc capibility. The gpmi will quits in this case. But in actually, the gpmi can supports this nand chip if it can get the right ECC info. 2.) about the new fields. The @ecc_strength_ds stands for the ecc bits needed within the @ecc_step_ds. The two fields should be set from the nand chip's datasheets. For example: "4bit ECC for each 512Byte" could be: @ecc_strength_ds = 4, @ecc_step_ds = 512. "40bit ECC for each 1024Byte" could be: @ecc_strength_ds = 40, @ecc_step_ds = 1024. 3.) Why do not re-use the @strength and @size in the nand_ecc_ctrl{}? The @strength and @size in nand_ecc_ctrl{} is used by the nand controller driver, while the @ecc_strength_ds and @ecc_step_ds are get from the datasheet. Signed-off-by: Huang Shijie <b32955@freescale.com> Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: increase max OOB size to 744Huang Shijie2014-04-16
| | | | | | | | | The oob size of Micron's MT29F64G08CBABAWP is 744 bytes. So increase the NAND_MAX_OOBSIZE to 744. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: reword nand_chip bad block interface commentsBrian Norris2014-04-16
| | | | | | | | | | | | | | | | This remedies a few problems: (1) The use of "the" vs. "a" is a little confusing, IMO. (2) nand_chip.block_bad is used exclusively for checking the OOB bad block markers of a NAND. Any BBT functionality is handled in nand_bbt.c, so this description should differentiate itself from nand_bbt.c. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: add a helper to check the SLC/MLC nand chipHuang Shijie2014-04-16
| | | | | | | | Add a helper to check if a nand chip is SLC or MLC. This helper makes the code more readable. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand_base: Only use GET/SET FEATURES command on chips that support them.David Mosberger2014-04-16
| | | | | | | | | Spansion's S34MLx chips support ONFI but not the GET/SET FEATURES calls. Signed-off-by: David Mosberger <dmosberger@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: remove NAND_BBT_SCANEMPTYBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | NAND_BBT_SCANEMPTY is a strange, badly-supported option with omap as its single remaining user. NAND_BBT_SCANEMPTY was likely used by accident in omap2[1]. And anyway, omap2 doesn't scan the chip for bad blocks (courtesy of NAND_SKIP_BBTSCAN), and so its use of this option is irrelevant. This patch drops the NAND_BBT_SCANEMPTY option. [1] http://lists.infradead.org/pipermail/linux-mtd/2012-July/042902.html Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Ivan Djelic <ivan.djelic@parrot.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: hide in-memory BBT implementation detailsBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | nand_base.c shouldn't have to know the implementation details of nand_bbt's in-memory BBT. Specifically, nand_base shouldn't perform the bit masking and shifting to isolate a BBT entry. Instead, just move some of the BBT code into a new nand_markbad_bbt() interface. This interface allows external users (i.e., nand_base) to mark a single block as bad in the BBT. Then nand_bbt will take care of modifying the in-memory BBT and updating the flash-based BBT (if applicable). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00285671 mmc: setup emmc boot partition configure methodsRichard Zhu2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Configure boot partition Expose the interfaces that used to enable the configurations of the boot mode of the eMMC cards. usage how-to and examples: Enable the boot partition 1 boot enabled. "echo 8 > /sys/devices/soc0/soc.1/2100000.aips-bus/ 219c000.usdhc/mmc_host/mmc2/mmc2\:0001/boot_config" In order to make sure that the re-read the ext-csd of card can be completed successfully, add the method to wait for the finish of the busy state. - setup boot_info message output Output bit means of important esd_csd register Read esd_csd info each time when cat boot_info becasue user may change config affect esd_csd value. - Boot partition access howto: About the details, please refer to the guidance of Documentation/mmc/mmc-dev-parts.txt To enable write access to /dev/mmcblkXbootY, disable the forced read-only access with: echo 0 > /sys/block/mmcblkXbootY/force_ro To re-enable read-only access: echo 1 > /sys/block/mmcblkXbootY/force_ro NOTE: - The definitions of the EXT_CSD_PART_CONFIG and EXT_CSD_BOOT_BUS_WIDTH +------------------------------------------------------------+ | Bit7 | Bit6 | Bit5 Bit4 Bit3 | Bit2 Bit1 Bit0 | |------|----------|-----------------------|------------------| | X | BOOT_ACK | BOOT_PARTITION_ENABLE | PARTITION_ACCESS | +------------------------------------------------------------+ Bit7: Reserved Bit6: always set to vaule '1' when boot_part is enabled Bit[5:3]: 0x0 : Device not boot enabled (default) 0x1 : Boot partition 1 enabled for boot 0x2 : Boot partition 2 enabled for boot 0x7 : User area enabled for boot Bit[2:0]: 0x0 : No access to boot partition (default) 0x1 : R/W boot partition 1 0x2 : R/W boot partition 2 +--------------------------------------------------------------------+ | Bit7 Bit6 Bit5 | Bit4 Bit3 | Bit2 | Bit1 Bit0 | |----------------|----------------------------------|----------------| | X | BOOT_MODE | RESET_BOOT_BUS_WIDTH | BOOT_BUS_WIDTH | +--------------------------------------------------------------------+ Bit [4:3] : BOOT_MODE (non-volatile) 0x0 : Use single data rate + backward compatible timings in boot operation (default) 0x1 : Use single data rate + high speed timings in boot operation mode 0x2 : Use dual data rate in boot operation 0x3 : Reserved Bit [2]: RESET_BOOT_BUS_WIDTH (non-volatile) 0x0 : Reset bus width to x1, single data rate and backward compatible timings after boot operation (default) 0x1 : Retain boot bus width and boot mode after boot operation Bit[1:0] : BOOT_BUS_WIDTH (non-volatile) 0x0 : x1 (sdr) or x4 (ddr) bus width in boot operation mode (default) 0x1 : x4 (sdr/ddr) bus width in boot operation mode 0x2 : x8 (sdr/ddr) bus width in boot operation mode 0x3 : Reserved - example of the boot_info: boot_info:0x07; ALT_BOOT_MODE:1 - Supports alternate boot method DDR_BOOT_MODE:1 - Supports alternate dual data rate during boot HS_BOOTMODE:1 - Supports high speed timing during boot boot_size:2048KB boot_partition:0x48; BOOT_ACK:1 - Boot acknowledge sent during boot operation BOOT_PARTITION-ENABLE: 1 - Boot partition 1 enabled PARTITION_ACCESS:0 - No access to boot partition boot_bus:0x00 BOOT_MODE:0 - Use single data rate + backward compatible timings in boot operation RESET_BOOT_BUS_WIDTH:0 - Reset bus width to x1, single data rate and backwardcompatible timings after boot operation BOOT_BUS_WIDTH:0 - x1 (sdr) or x4 (ddr) bus width in boot operation mode Signed-off-by: Richard Zhu <r65037@freescale.com>
* driver core: bus_type: add dev_groupsGreg Kroah-Hartman2014-04-16
| | | | | | | | | | | | attribute groups are much more flexible than just a list of attributes, due to their support for visibility of the attributes, and binary attributes. Add dev_groups to struct bus_type which should be used instead of dev_attrs. dev_attrs will be removed from the structure soon. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* sysfs.h: add ATTRIBUTE_GROUPS() macroGreg Kroah-Hartman2014-04-16
| | | | | | | | | | | To make it easier for driver subsystems to work with attribute groups, create the ATTRIBUTE_GROUPS macro to remove some of the repetitive typing for the most common use for attribute groups. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* driver core: device.h: add RW and RO attribute macrosGreg Kroah-Hartman2014-04-16
| | | | | | | | | | Make it easier to create attributes without having to always audit the mode settings. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* spi: Provide common spi_message processing loopMark Brown2014-04-16
| | | | | | | | | | | | | | | | | | | | The loops which SPI controller drivers use to process the list of transfers in a spi_message are typically very similar and have some error prone areas such as the handling of /CS. Help simplify drivers by factoring this code out into the core - if drivers provide a transfer_one() function instead of a transfer_one_message() function the core will handle processing at the message level. /CS can be controlled by either setting cs_gpio or providing a set_cs function. If this is not possible for hardware reasons then both can be omitted and the driver should continue to implement manual /CS handling. This is a first step in refactoring and it is expected that there will be further enhancements, for example factoring out of the mapping of transfers for DMA and the initiation and completion of interrupt driven transfers. Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* spi: Provide per-message prepare and unprepare operationsMark Brown2014-04-16
| | | | | | | | | | | | | Many SPI drivers perform setup and tear down on every message, usually doing things like DMA mapping the message. Provide hooks for them to use to provide such operations. This is of limited value for drivers that implement transfer_one_message() but will be of much greater utility with future factoring out of standard implementations of that function. Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* spi: core: Add devm_spi_register_master()Mark Brown2014-04-16
| | | | | | | | | Help simplify the cleanup code for SPI master drivers by providing a managed master registration function, ensuring that the master is automatically unregistered whenever the device is unbound. Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* spi: DUAL and QUAD supportwangyuhang2014-04-16
| | | | | | | | | | | | | | | | | | | | | fix the previous patch some mistake below: 1. DT in slave node, use "spi-tx-nbits = <1/2/4>" in place of using "spi-tx-dual, spi-tx-quad" directly, same to rx. So correct the previous way to get the property in @of_register_spi_devices(). 2. Change the value of transfer bit macro(SPI_NBITS_SINGLE, SPI_NBITS_DUAL SPI_NBITS_QUAD) to 0x01, 0x02 and 0x04 to match the actual wires. 3. Add the following check (1)keep the tx_nbits and rx_nbits in spi_transfer is not beyond the single, dual and quad. (2)keep tx_nbits and rx_nbits are contained by @spi_device->mode example: if @spi_device->mode = DUAL, then tx/rx_nbits can not be set to QUAD(SPI_NBITS_QUAD) (3)if "@spi_device->mode & SPI_3WIRE", then tx/rx_nbits should be in single(SPI_NBITS_SINGLE) Signed-off-by: wangyuhang <wangyuhang2014@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* spi: fix SPI_BIT_MASK so it always fits into 32-bitsStephen Warren2014-04-16
| | | | | | | | | | | | | | On a 64-bit platform, ~0UL fills 64-bits, which causes SPI_BIT_MASK(32) not to fit into 32 bits. This causes a warning when the result is assigned to a 32-bit variable. Use ~0U instead to prevent this. This fixes: drivers/spi/spi-gpio.c: In function 'spi_gpio_probe': drivers/spi/spi-gpio.c:446:2: warning: large integer implicitly truncated to unsigned type [-Woverflow] Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* spi: Provide core support for runtime PM during transfersMark Brown2014-04-16
| | | | | | | | | | | | | | | | | Most SPI drivers that implement runtime PM support use identical code to do so: they acquire a runtime PM lock in prepare_transfer_hardware() and then they release it in unprepare_transfer_hardware(). The variations in this are mostly missing error checking and the choice to use autosuspend. Since these runtime PM calls are normally the only thing in the prepare and unprepare callbacks and the autosuspend API transparently does the right thing on devices with autosuspend disabled factor all of this out into the core with a flag to enable the behaviour. Signed-off-by: Mark Brown <broonie@linaro.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* driver: spi: Modify core to compute the message lengthSourav Poddar2014-04-16
| | | | | | | | | | | | Make spi core calculate the message length while populating the other transfer parameters. Usecase, driver can use it to populate framelength filed in their controller. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* spi: Support transfer speed checking in the coreMark Brown2014-04-16
| | | | | | | | Allow drivers to avoid implementing their own checks for simple rates by specifying the limits in the master structure. Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* spi: fix incorrect handling of min param in SPI_BPW_RANGE_MASKStephen Warren2014-04-16
| | | | | | | | | | | | | | | | SPI_BPW_RANGE_MASK is intended to work by calculating two masks; one representing support for all bits up-to-and-including the "max" supported value, and one representing support for all bits up-to-but-not-including the "min" supported value, and then taking the difference between the two, resulting in a mask representing support for all bits between (inclusive) the min and max values. However, the second mask ended up representing all bits up-to-and- including rather up-to-but-not-including. Fix this bug. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* spi: fix undefined behaviour in SPI_BPW_RANGE_MASKStephen Warren2014-04-16
| | | | | | | | | | | | | | | | | | | | The parameters to SPI_BPW_RANGE_MASK() are in the range 1..32. If 32 is used as a parameter, part of the expression is "1 << 32". Since 32 is >= the size of the type in use, such a shift is undefined behaviour. Add macro SPI_BIT_MASK to Implement a special case and thus avoid undefined behaviour. Use this new macro rather than BIT() when implementing SPI_BPW_RANGE_MASK(). This fixes build warnings such as: drivers/spi/spi-gpio.c:446:2: warning: left shift count >= width of type [enabled by default] SPI_BPW_MASK() already avoids this, since its parameter is also in range 1..32, yet it only shifts by up to one less than the input parameter. Reported-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* spi: introduce macros to set bits_per_word_maskStephen Warren2014-04-16
| | | | | | | | | | | | | Introduce two macros to make setting up spi_master.bits_per_word_mask easier, and avoid mistakes like writing BIT(n) instead of BIT(n - 1). SPI_BPW_MASK is for a single supported value of bits_per_word_mask. SPI_BPW_RANGE_MASK represents a contiguous set of bit lengths. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* spi/bitbang: Use core message pumpMark Brown2014-04-16
| | | | | | | | | Convert drivers using bitbang to use the core mesasge pump infrastructure, saving some code and meaning that these drivers get to take advantage of work done on improving the core implementation. Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* spi/bitbang: Unexport spi_bitbang_transfer()Mark Brown2014-04-16
| | | | | | | | | | Currently no drivers use the ability to override spi_bitbang_transfer() and if any started this would make it harder to convert the bitbang code to use transfer_one_message() so remove the export in order to prevent anyone starting. Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mmc: sdhci-esdhc-imx: add delay line setting supportDong Aisheng2014-04-16
| | | | | | | | | | | | | | | | | The DLL(Delay Line) is newly added to assist in sampling read data. The DLL provides the ability to programmatically select a quantized delay (in fractions of the clock period) regardless of on-chip variations such as process, voltage and temperature (PVT). This patch adds a user interface to set slave delay line via device tree. It's usually used in high speed mode like mmc DDR mode when the signal quality is not good caused by board design, e.g. the signal path is too long. User can manually set delay line to find a suitable data sampling window for card to work properly. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
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