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For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, ASRC needs to save
all the values of registers before the system suspend and restore them after
the system resume.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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period data
The original design:
-> Input DMA task -> complete()
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-> Output DMA task -> complete()
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| -> Last period polling work thread -> complete()
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Main thread --------------> wait_for_completion() of Input and last period
It's too complicated and worthless to use an extra work thread for last period data.
So this patch just switches the flow into a simpler approach:
-> Input DMA task -> complete()
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-> Output DMA task -> complete()
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Main thread --------------> wait_for_completion() of In/Output -> Last period polling
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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ASRC needs three clocks from SoC, they are:
mem_clk: Peripheral access clock
ipg_clk: Peripheral clock
asrck_clk: ASRC module clock
while the current driver only maintains two of them and has confusing
clock names. Thus fix it.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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Previously, we used sdma's event pending to forcibly re-schedule sdma
for work round, because sdma channel for ASRC input task would fail to
be opened due to its dma request always keeping high after ASRC opens
the pair, which cause sdma miss the trigger point of dma request.
Now, instead of using event pending, we clear the dma request on ASRC
driver side by setting its thresholds to an impossible trigger area
during its stall state. Since ASRC would stall its process when input
fifo is near empty or output fifo is near full, during the stall state,
the specific thresholds, 0 for input fifo and 63 for output fifo, would
never let asrc meet this condition. So dma request can be cleared and
raised again after we restore the true required thresholds.
Accordingly, since we don't need event pending any more, we dropped the
code from the sdma driver.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
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We don't need to set ASRC to STALL level everytime, instead we only need
to do that at the beginning. If we insert null data into input fifo during
the sequence of valid datas, there would be a noise occur to it.
By doing this, we can assure ASRC would keep each period's perturbation of
output dma task within 8 sample sizes, which is the default value for last
period number. Thus we don't need to expand the last period number any more.
This patch also dropped some unused functions since the driver no long needs
them and replaced wrapped function for channel number configuration with direct
regmap_update_bits() to make the driver clean.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
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We can determine the IP version from DT compatible name to decide which
clock map and channel bits should be used.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
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* Dropped unused header files.
* Use pair-explicit error massage.
* Fixed some coding style issue.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
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Use completion instead of counter to make driver clean and drop
implicit mdelay by using wait_for_completion().
Signed-off-by: Nicolin Chen <b42378@freescale.com>
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Dropped the legency readl/writel() and use regmap instead. Also removed
core clock's clk_prepare() and spin_lock()/unlock() outside regmap due to
regmap already has these features.
This patch also added a missing writable register to the regmap in order
to assure the regsiter updating success.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
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ASRC is using shp_2_mcu and mcu_2_shp sdma scripts that use spba bus to
transfer data, while the driver hasn't include the control code of spba
clock.
This would cause multiple pair conversion failed in most of time. Thus
we need to add its support.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
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* Add missing clock control
* Set ASRC clock to 7.5MHz as 3.0.35 does
* Use the same divisor for ideal ratio mode as 3.0.35 does
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <b42378@freescale.com>
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Add ASRC M2M driver.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
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