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* ENGR00293231 IPUv3 reg: Remove some unused macrosLiu Ying2014-04-16
| | | | | | | | | | | This patch removes two unused macros IPU_INT_CTRL_IRQ(irq) and IPU_INT_STAT_IRQ(irq) to save two lines of code. The existing another two macros IPUIRQ_2_STATREG(irq) and IPUIRQ_2_CTRLREG(irq) are the surrogates for them. Reviewed-by: Robby Cai <R63905@freescale.com> Cc: Oliver Brown <oliver.brown@freescale.com> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00292775 mipi csi2: Refine register accessLiu Ying2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | The original mipi csi2 driver uses readl()/writel() to access the 32 bit mipi csi2 registers in the following way where info->mipi_csi2_base is a pointer which points to a 32 bit I/O memory cell of the mipi csi2's base address: writel(value, info->mipi_csi2_base + offset); readl(info->mipi_csi2_base + offset); This makes the register offset values shrink 4 times, comparing to the offset values documented in the reference manual. For example, we need to change the offset value from 0x004 to 0x001 so that we may access the register MIPI_CSI2_N_LANES correctly. This patch redefines the type of info->mipi_csi2_base to 'void __iomem *', then the offset values can be the same to what they are documented. Also, the macro names for the registers are aligned to the documentation. Acked-by: Robby Cai <R63905@freescale.com> Cc: Oliver Brown <oliver.brown@freescale.com> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00292585 IPUv3: Fix a horizontal line at the middle playing 1080iOliver Brown2014-04-16
| | | | | | | | | Added additional check to handle stripe limits differently for upscaling and downscaling. Upscaling requires relaxed checking because input stripe may fall slighty outside of the input window. Downscaling requires strict limit checking. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00290579 IPUv3: Fix split mode warningsOliver Brown2014-04-16
| | | | | | Changed alignement for planar formats back to 16 pixels. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00291103 IPUv3 common:Don't initialize PRP_VF for MEM_VDI_MEMLiu Ying2014-04-16
| | | | | | | | | | | | | Since the channel MEM_VDI_MEM doesn't use the PRP_VF task, this patch removes the code to initialize the PRP_VF task for the channel MEM_VDI_MEM. This change may fix the issue caused by the unnesessary PRP_VF task output resolution limitation check. The issue can be reproduced by the following unit test case: mxc_vpu_test.out -D "-f 2 -y 2 -v m -i 1080i_shields1088i2997_shields_ter_4x300_15fps_track1.h264" Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00290679 mxc: mlb Fix the MLB150 not stable issue in ISOC mode.Luwei Zhou2014-04-16
| | | | | | | | | | | The MLB test bench has bug when testing the ISOC mode.When we press stop test button when completing test, MITB will cause MLB150 on ARD error.The mlbintr ISR handler is used to handle the error interrupt. In the ISR handler, the MLB150_MS0,MLB150MS1 should be cleared. The spec doesn't give detailed description. The spec only says that the registers need to be cleared before enabling interrupt. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00290654 IPUv3 dev:Workaround split mode downsize overflowLiu Ying2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The downsizing ratio overflow check should cover every stripe in the split mode. We need to do the overflow check correctly by taking the width/height 8-pixel alignment requirement into consideration since the alignment would be done when every stripe is checked in it's own ipu task. This patch takes a workaround for the issue which can be reproduced by this unit test case: ================================================================== mxc_v4l2_output.out -iw 1920 -ih 1080 -ow 200 -oh 200 -v 1 mxc_ipu mxc_ipu: ERR:create_split_child_task() ret:-22 mxc_ipu mxc_ipu: sp_task[0],no-0x12 fail state:-22, queue err:-22. mxc_ipu mxc_ipu: ERR: [0xac73ea00] no-0x10,state 3: error mxc_ipu mxc_ipu: ERR: no-0x10,ipu_queue_task err:-125 mxc_v4l2_output v4l2_out.35: display work fail ret = -125 mxc_ipu mxc_ipu: ERR:create_split_child_task() ret:-22 mxc_ipu mxc_ipu: sp_task[0],no-0x22 fail state:-22, queue err:-22. mxc_ipu mxc_ipu: ERR: [0xac73ea00] no-0x20,state 3: error mxc_ipu mxc_ipu: ERR: no-0x20,ipu_queue_task err:-125 mxc_v4l2_output v4l2_out.35: display work fail ret = -125 mxc_ipu mxc_ipu: ERR:create_split_child_task() ret:-22 mxc_ipu mxc_ipu: sp_task[0],no-0x32 fail state:-22, queue err:-22. mxc_ipu mxc_ipu: ERR: [0xac63c400] no-0x30,state 3: error mxc_ipu mxc_ipu: ERR: no-0x30,ipu_queue_task err:-125 mxc_v4l2_output v4l2_out.35: display work fail ret = -125 VIDIOC_QBUF failed -1 ================================================================== Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00290635-2 IPUv3 stripe:Fix a build warningLiu Ying2014-04-16
| | | | | | | | | | | This patch fixes the following build warning by initializing some local variables: drivers/mxc/ipu3/ipu_calc_stripes_sizes.c: In function ‘ipu_calc_stripes_sizes’: drivers/mxc/ipu3/ipu_calc_stripes_sizes.c:393:3: warning: ‘difwr’ may be used uninitialized in this function [-Wuninitialized] drivers/mxc/ipu3/ipu_calc_stripes_sizes.c:393:3: warning: ‘onw’ may be used uninitialized in this function [-Wuninitialized] drivers/mxc/ipu3/ipu_calc_stripes_sizes.c:393:3: warning: ‘inw’ may be used uninitialized in this function [-Wuninitialized] Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00290361-1 IPUv3 IC:Add check for a IDMAC errataLiu Ying2014-04-16
| | | | | | | | | | | The IPUv3 IDMAC has a bug to read 32bpp pixels from a graphics plane whose alpha component is at the most significant 8 bits. The bug only impacts on cases in which the relevant separate alpha channel is enabled. This patch adds check for the errata so that the bad cases won't be triggered. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00290337 ipuv3: Setup pixel clock tree after ipu resetSandor Yu2014-04-16
| | | | | | | | | | | | | | When the ipu pixel clocks are initialized, the default pixel clock rate will be calucated according to the present ipu register setting which is likely set by a bootloader. But these registers will be reset by the ipu reset function. If the default pixel clock rate is the same to what is requested later, the clk_set_rate function will treat this case as pixel clock unchanged. Move the pixel clock setup function after the ipu reset function to resolve this issue Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00290176 mxc: mlb: Fix MLB suspend/resume issueLuwei Zhou2014-04-16
| | | | | | | There is risk that mlb register will be access when clock is closed. This patch fix it. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00289381 mxc: asrc: Fix RCU stall in output_task_workerNicolin Chen2014-04-16
| | | | | | | | | | | | | In kernel 3.10.17, RCU has its threshold to detect RCU stall. So it might be risky for us to use a whole second to wait for the completion, which would be surely returned within 100ms. Thus, we shrink the wait period so as to circumvent some potential RCU stall issue. This patch also moved pair_hold into spin_lock protection due to a race with pair_hold in close() and release(). Signed-off-by: Nicolin Chen <b42378@freescale.com> (cherry picked from commit 5b35fca56107cb04bdf342969887b386683da901)
* ENGR00289553 IPU dev:correct downsize overflow check in rot caseLiu Ying2014-04-16
| | | | | | | | | | | | | | In rotation cases, the width and height of IPUv3 IC scaling block's output should align with the width and height of IPUv3 IC rotation block. And, users only tell the IPUv3 device driver about the parameters of scaling block's input and rotation block's output. So, we need to swap the width and height of rotation block in cache before we do downsize(a functionality of the scaling block) overflow check. This patch fixes the issue which can be reproduced by this unit test case: /unit_tests/mxc_v4l2_output.out -iw 128 -ih 128 -ow 176 -oh 10 -r 90 Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00274166 - Split mode has artifactsOliver Brown2014-04-16
| | | | | | | | | - Need to use different multiple and index parameters for vertical and horizontal stripes - Use correct multiple and index based upon pixel format - Allow input crop and size to be larger than width by upto 16 pixels Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00272541 IPUv3 IC: Split Downsizing overflow for size greater than 1024Oliver Brown2014-04-16
| | | | | | | | | | | | | | For downscaling, it is possible that downscaler output is greater than 1024. Added a function, calc_split_resize_coeffs, based upon _calc_resize_coeffs to calculate resizing and downscaling coefficients. In ipu_ic.c, checks for the range of *_resize_ratio are no longer needed. Non split cases will always have *_resize_ratio of zero. In ipu_device, additional checks are needed to check for an error from ipu_calc_stripes_sizes if calc_split_resize_coeffs fails. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00270037 mxc: mlb: Fix MLB crash when testing abnormallyLuwei Zhou2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If quit the test program via CTRL+c during the test and leaving the MITB still running, kernel crash sometimes happen when launching the test program for a second time. This patch fix this issue. The main modification is: * Initialize the wait queue head dynamically not statically * Enable/Disalbe IRQ when necessary Unable to handle kernel NULL pointer dereference at virtual address 00000000 pgd = 80004000 [00000000] *pgd=00000000 Internal error: Oops: 80000007 [#1] SMP ARM Modules linked in: mxc_mlb150 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.17-16879-g5d48ab5 #227 task: 80c2d908 ti: 80c22000 task.ti: 80c22000 PC is at 0x0 LR is at __wake_up_common+0x54/0x94 pc : [<00000000>] lr : [<8004b9fc>] psr: 90000193 sp : 80c23e18 ip : dc86ff1c fp : 80c23e44 r10: 00000000 r9 : 00000001 r8 : 00000000 r7 : 00000000 r6 : 7f002fe0 r5 : 7f0017fc r4 : dcaff0f4 r3 : 00000000 r2 : 00000000 r1 : 00000001 r0 : dc86ff1c Flags: NzcV IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c53c7d Table: 6c90004a DAC: 00000015 Process swapper/0 (pid: 0, stack limit = 0x80c22238) Stack: (0x80c23e18 to 0x80c24000) 3e00: 00000000 00000001 3e20: dc1d14c0 7f002fdc 20000193 00000001 00000001 00000000 00000000 80c7018e 3e40: 80c23e6c 8004bbf4 00000000 8004bbf4 00000004 0091a840 7f002f80 7f002e1c 3e60: 00000004 fffffff9 00000001 7f001054 ffffae63 00000009 0000005a 00000000 3e80: ffffffff 00000010 00000095 00000000 00000000 00000095 dc011180 7f001168 3ea0: dc482e40 80073c08 00000015 80c2a770 80c1e7e0 dc011180 00000095 00000000 3ec0: f4000100 00000000 00000000 80c22000 80c2a4d8 80073d70 00000000 dc011180 3ee0: 00000095 80076ae8 00000095 800733d0 80c1ee3c 8000e848 f400010c 80c2a8b8 3f00: 80c23f20 80008570 8005a15c 804299d0 60000013 ffffffff 80c23f54 8000dbc0 3f20: 80c23f68 0000005a 3437dc5e 00000015 34373d83 00000015 81aef080 80c30050 3f40: 00000000 00000000 80c22000 80c2a4d8 00000017 80c23f68 8005a15c 804299d0 3f60: 60000013 ffffffff 3437dc5e 00000015 80cc41a4 806152ac 81aef080 80cc41a4 3f80: 00000000 80c30050 00000000 80429b10 00000001 80c7017a 80c2a524 806152ac 3fa0: 80c22000 80c7017a 80c22000 8000eb7c 00067162 800599f0 000000d9 80c12ef0 3fc0: 00000000 80bd6a9c ffffffff ffffffff 80bd6548 00000000 00000000 80c12ef0 3fe0: 10c53c7d 80c2a4a0 80c12eec 80c2e6ec 1000406a 10008074 00000000 00000000 [<8004b9fc>] (__wake_up_common+0x54/0x94) from [<8004bbf4>] (__wake_up+0x3c/0x50) [<8004bbf4>] (__wake_up+0x3c/0x50) from [<7f001054>] (mlb_tx_isr+0xa0/0xf4 [mxc_mlb150]) [<7f001054>] (mlb_tx_isr+0xa0/0xf4 [mxc_mlb150]) from [<7f001168>] (mlb_ahb_isr+0xc0/0x134 [mxc_mlb150]) [<7f001168>] (mlb_ahb_isr+0xc0/0x134 [mxc_mlb150]) from [<80073c08>] (handle_irq_event_percpu+0x54/0x17c) [<80073c08>] (handle_irq_event_percpu+0x54/0x17c) from [<80073d70>] (handle_irq_event+0x40/0x60) [<80073d70>] (handle_irq_event+0x40/0x60) from [<80076ae8>] (handle_fasteoi_irq+0x80/0x158) [<80076ae8>] (handle_fasteoi_irq+0x80/0x158) from [<800733d0>] (generic_handle_irq+0x2c/0x3c) [<800733d0>] (generic_handle_irq+0x2c/0x3c) from [<8000e848>] (handle_IRQ+0x40/0x90) [<8000e848>] (handle_IRQ+0x40/0x90) from [<80008570>] (gic_handle_irq+0x2c/0x5c) [<80008570>] (gic_handle_irq+0x2c/0x5c) from [<8000dbc0>] (__irq_svc+0x40/0x50 Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00288421-4 mxc: asrc: keep map/unmap parameters symmeticNicolin Chen2014-04-16
| | | | | | | | We are using DEV_TO_MEM for dma_map but MEM_TO_DEV for dma_unmap, thus fix it. It also adds missing device pointer since assigning it to dma_free_coherent(). Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00288021 IPUv3 disp:get the integer part of div correctlySandor Yu2014-04-16
| | | | | | | | | | TV will show 639x480p60 when HDMI output 640x480p60. The same issue can be found when pixel clock sources from ipu internally. All video modes whose pixel clocks derive from DI clock work OK. It is caused by the wrong parent clock rate the driver gets. Fix the issue by getting the right parent clock(ipu->pixel_clk_sel). Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00287826 mxc: mlb: Fix MLB rcu stall issue when MITB is not set correctlyLuwei Zhou2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MLB lock and clock check has logic issue in code. The timeout cann't work and it will cause rcu-stall. Exception stack(0xdca21e68 to 0xdca21eb0) 1e60: 00000001 00000000 ffffff7f 0000270f 00002710 0000ffc0 1e80: 00000000 00000004 00000002 00000001 00000001 7f003b50 f0378000 dca21eb0 1ea0: 7f003b50 7f0009cc 20000013 ffffffff [<8000dc04>] (__irq_svc+0x44/0x58) from [<7f0009cc>] (mlb150_dev_unmute_syn_ch [<7f0009cc>] (mlb150_dev_unmute_syn_ch+0x34/0xd4 [mxc_mlb150]) from [<7f002584 [<7f002584>] (mxc_mlb150_ioctl+0x85c/0x898 [mxc_mlb150]) from [<800db86c>] (do_ [<800db86c>] (do_vfs_ioctl+0x40c/0x5e4) from [<800dba7c>] (SyS_ioctl+0x38/0x64) [<800dba7c>] (SyS_ioctl+0x38/0x64) from [<8000e000>] (ret_fast_syscall+0x0/0x48 INFO: rcu_sched self-detected stall on CPU 0: (14684 ticks this GP) idle=fdf/140000000000001/0 softirq=1555/1555 (t=14720 jiffies g=2 c=1 q=22) CPU: 0 PID: 628 Comm: mxc_mlb150_test Not tainted 3.10.17-16837-g187ed79-dirty [<80013d7c>] (unwind_backtrace+0x0/0xf4) from [<80011798>] (show_stack+0x10/0x [<80011798>] (show_stack+0x10/0x14) from [<8008575c>] (rcu_check_callbacks+0x3 [<8008575c>] (rcu_check_callbacks+0x3d0/0x7f8) from [<80033884>] (update_proce [<80033884>] (update_process_times+0x40/0x6c) from [<80064f48>] (tick_sched_ti [<80064f48>] (tick_sched_timer+0x4c/0x78) from [<80048508>] (__run_hrtimer.isr [<80048508>] (__run_hrtimer.isra.32+0x44/0xd4) from [<80048de4>] (hrtimer_inte [<80048de4>] (hrtimer_interrupt+0x108/0x294) from [<800136f0>] (twd_handler+0x [<800136f0>] (twd_handler+0x34/0x44) from [<80080208>] (handle_percpu_devid_ir [<80080208>] (handle_percpu_devid_irq+0x6c/0x84) from [<8007c958>] (generic_ha [<8007c958>] (generic_handle_irq+0x2c/0x3c) from [<8000e908>] (handle_IRQ+0x40 [<8000e908>] (handle_IRQ+0x40/0x90) from [<8000856c>] (gic_handle_irq+0x2c/0x5 [<8000856c>] (gic_handle_irq+0x2c/0x5c) from [<8000dc04>] (__irq_svc+0x44/0x5. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00287278 mxc: mlb: Enable the clock when open MLB device.Luwei Zhou2014-04-16
| | | | | | | The driver enalbe/disable the clock in probe()/remove(). It should be done in open()/close() hook function in fact. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00287256 mxc: mlb: Fix the SYNC mode hang issue when connected with MITBLuwei Zhou2014-04-16
| | | | | | | | | | | This patch fixes the hang and crash issue of MLB SYNC mode in the driver. The MITB will casue Sabreauto to hang and crash when testing the SYNC mode. It is because MITB will cause something error on MLB bus when stopping the SYNC test. The Sabreauto will keep entering error ISR and hang. Since we don't know the details about MITB, we make drivers provide IO_CTRL interface to disable the interrupt in SYNC mode. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00285441 mxc: mlb: Fix the receive issue of ISOC mode on SabreautoLuwei Zhou2014-04-16
| | | | | | | | | | | This patch fixes the receive issue of MLB ISO mode on Sabreauto side. During debug, it is found that the Sabreauto can only receive 1/5 packets of MITB sends.The MITB sends out 188 bytes per packet. The Sabreauto receives 188*5 bytes. It seems that the packet length on Sabreauto side is 5 times larger than MITB side. After changing the defautl block number to 1, Sabreauto passes the test. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00274782 fixed gpu crash when baseAddress is not 0 or 2GXianzhong2014-04-16
| | | | | | | | | | The baseAddress of contiguousVidMem is the actual physical address which is not subtracted by gpu baseAddress, but the allocated physical address has been subtracted by gpu baseAddress in gckVIDMEM_Lock, so the invalid offset is produced and used to calculate the logical address. Signed-off-by: Xianzhong <b07117@freescale.com> Acked-by: Shawn Guo
* ENGR00274478 fix gpu memory multi-lock failureXianzhong2014-04-16
| | | | | | | | | | this issue cause system boot with multi-user switch on JB4.3, root cause is gpu memory cannot be multi-locked in same process, gpu memory lock reference is added to allow multi-lock in kernel driver. Signed-off-by: Xianzhong <b07117@freescale.com> Acked-by: Jason Liu
* ENGR00277045-1 fix system reboot with video playbackXianzhong2014-04-16
| | | | | | | | | gpu virtual memory cannot be allocated for external use this issue occurs in ARD board with 2G above memory address Signed-off-by: Xianzhong <b07117@freescale.com> Acked-by: Jason Liu
* ENGR00285273-3 IPU dev:Remove unnecessary memset before kfreeLiu Ying2014-04-16
| | | | | | | | This patch removes unnecessary memset() before kfree(). Also, it fixes a potential NULL pointer dereference(writing to a freed block of memory). Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00285273-2 IPU dev:Remove an unnesessary checkLiu Ying2014-04-16
| | | | | | | This patch removes an unnesessary check before setting task ID to simplify the code. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00285273-1 IPU dev:Correct timeout setting from usersLiu Ying2014-04-16
| | | | | | | This patch corrects the logic to set timeout value specified by the users. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00284648 mxc: mlb: clean up the MLB driver code.Luwei Zhou2014-04-16
| | | | | | | | | | | This patch clean up the MLB driver code of i.MX6Q/DL AUTO. * Reorder the head file alphabetically * Fix code comments format * Fix the lines over 80 characters * Fix the return type to void for some private functions Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00283475 mxc: mlb : add MLB150 driver support.Luwei Zhou2014-04-16
| | | | | | | | | | | | | | | | This patch add MLB150 driver support.Copy files from 3.0.35 kernel. * Using of_xxx API to get resource from dts * Using devm_xxx API to simply the code * Change clk_enable()/clk_disable() to clk_prepare_enable()/ clk_disable_unprepare() * Fix some warning when compiling * Fix issue when handling errors in mxc_mlb150_probe() * Remove declaration of gpio_mlb_active(), gpio_mlb_inactive() out of mxc_mlb.h, because the functions are not invoked. * Add UAPI support. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00283192 Avoid vpu rmmod failure and modprobe warningHongzhang Yang2014-04-16
| | | | | | | | | | | | - Avoid vpu rmmod failure caused by regulator free failure Do not call regulator_put because regulators returned from devm_regulator_get are automatically regulator_put() on driver detach - Avoid vpu modprobe warning caused by unbalanced pm_runtime_enable Add missing call to pm_runtime_disable Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
* ENGR00283037 [gpu]Avoid gpu rmmod failure caused by regulator free failureLoren HUANG2014-04-16
| | | | | | | | | The failure is caused by duplicate regulator resource free. New devm_xxx API will free the resource automatically after remove() is called. Signed-off-by: Loren HUANG <b02279@freescale.com> Acked-by: Shawn Guo
* ENGR00281859-1 mxc: asrc: Add debug message for asrc_isr()Nicolin Chen2014-04-16
| | | | | | | | | | asrc_isr() is mainly used to detect and record overload error, so we add some print massage to make it easy to debug. Also fixed an incorrect function name -- dev_debug() by using the correct one -- dev_dbg() in dump_regs(). Signed-off-by: Nicolin Chen <B42378@freescale.com>
* ENGR00280852-9 mxc: asrc: Use threshold to clear dma requestNicolin Chen2014-04-16
| | | | | | | | | | | | | | | | | | | | Previously, we used sdma's event pending to forcibly re-schedule sdma for work round, because sdma channel for ASRC input task would fail to be opened due to its dma request always keeping high after ASRC opens the pair, which cause sdma miss the trigger point of dma request. Now, instead of using event pending, we clear the dma request on ASRC driver side by setting its thresholds to an impossible trigger area during its stall state. Since ASRC would stall its process when input fifo is near empty or output fifo is near full, during the stall state, the specific thresholds, 0 for input fifo and 63 for output fifo, would never let asrc meet this condition. So dma request can be cleared and raised again after we restore the true required thresholds. Accordingly, since we don't need event pending any more, we dropped the code from the sdma driver. Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00280852-8 mxc: asrc: Add polling mode working without dma for debuggingNicolin Chen2014-04-16
| | | | | | | Add polling mode for data transmitting without dma support for debugging when sdma may have issue. Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00280852-7 mxc: asrc: Only set ASRC to STALL level in start_conv()Nicolin Chen2014-04-16
| | | | | | | | | | | | | | | | We don't need to set ASRC to STALL level everytime, instead we only need to do that at the beginning. If we insert null data into input fifo during the sequence of valid datas, there would be a noise occur to it. By doing this, we can assure ASRC would keep each period's perturbation of output dma task within 8 sample sizes, which is the default value for last period number. Thus we don't need to expand the last period number any more. This patch also dropped some unused functions since the driver no long needs them and replaced wrapped function for channel number configuration with direct regmap_update_bits() to make the driver clean. Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00280852-6 mxc: asrc: Use devtype instead of specific DT propertiesNicolin Chen2014-04-16
| | | | | | | We can determine the IP version from DT compatible name to decide which clock map and channel bits should be used. Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00280852-5 mxc: asrc: Simplify codeNicolin Chen2014-04-16
| | | | | | | | * Dropped unused header files. * Use pair-explicit error massage. * Fixed some coding style issue. Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00280852-4 mxc: asrc: Use completion instead of counterNicolin Chen2014-04-16
| | | | | | | Use completion instead of counter to make driver clean and drop implicit mdelay by using wait_for_completion(). Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00280852-3 mxc: asrc: Use regmap to control register accessingNicolin Chen2014-04-16
| | | | | | | | | | | Dropped the legency readl/writel() and use regmap instead. Also removed core clock's clk_prepare() and spin_lock()/unlock() outside regmap due to regmap already has these features. This patch also added a missing writable register to the regmap in order to assure the regsiter updating success. Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00280852-1 mxc: asrc: Add spba clock control for sdma shp scriptNicolin Chen2014-04-16
| | | | | | | | | | | ASRC is using shp_2_mcu and mcu_2_shp sdma scripts that use spba bus to transfer data, while the driver hasn't include the control code of spba clock. This would cause multiple pair conversion failed in most of time. Thus we need to add its support. Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00280663-2 IPUv3 device: check downsize ratio overflowLiu Ying2014-04-16
| | | | | | | | IPUv3 IC task downsize scaling ratio cannot exceed or be equal to 8:1. This patch makes the code return error code if the ratio overflows. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00280663-1 IPUv3: improve IC scale check logicLiu Ying2014-04-16
| | | | | | | | This patch improves IPU IC task scale check logic so that we may return with error code if the calculation for scale coefficients fails. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00279368-3 mxc: asrc: Add missing clock controlNicolin Chen2014-04-16
| | | | | | | | | * Add missing clock control * Set ASRC clock to 7.5MHz as 3.0.35 does * Use the same divisor for ideal ratio mode as 3.0.35 does Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00278652-1 [Media]: Add MIPI CSI2 driver filesOliver Brown2014-04-16
| | | | | | | | | | | | | | | | | | | | | Copied mipi_csi.h from: commit 50ca92f4010a93be265de7aad501b4dcae095a63 Author: Sheng Nan <b38800@freescale.com> Date: Thu Mar 7 13:39:54 2013 +0800 ARM: include: remove definition of mipi-csi2 platform data Other files copied files from: commit 1fb93870965b7d8d67b4db6233a30c06d82f84fc Author: Liu Ying <Ying.Liu@freescale.com> Date: Thu Mar 21 12:15:52 2013 +0800 MIPI-CSI2:Fix a build warning - Changed includes files for 3.10 - Dropped deprecated __devexit - Added generic error message if probe fails - Added configuration and set default to 'n' Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00278350 gpu:viante 4.6.9p13 kernel part integrationLoren HUANG2014-04-16
| | | | | | | Integrated 4.6.9p13 kernel part change. Signed-off-by: Loren HUANG <b02279@freescale.com> Acked-by: Shawn Guo
* ENGR00277333 gpu: Enable OT limitation for gc880Loren HUANG2014-04-16
| | | | | | | | Enable OT limitation for gc880, without this limitation 3D core may stall system bus when it is running at a very low clock. Signed-off-by: Loren HUANG <b02279@freescale.com> Acked-by: Shawn Guo
* ENGR00276023-3: mxc: gpu-viv: get regulator by dts instead of hard codeRobin Gong2014-04-16
| | | | | | | Use devm_regulator_get rather than regulator_get in gpu driver since we have use DTS. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00277201-2 gpu: potential memory leak when umapping vg memoryLoren HUANG2014-04-16
| | | | | | | Release the allocate memory properly to avoid memory leak. Signed-off-by: Loren HUANG <b02279@freescale.com> Acked-by: Shawn Guo
* ENGR00277003 IPUv3: Update IC RGB2YUV CSC matrix parametersLiu Ying2014-04-16
| | | | | | | | | This patch updates IPUv3 IC RGB to YUV color space conversion matrix's parameters to align with the default VIV GPU CSC implementation so that we may pass relevant Android CTS test cases. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-03 11:32:24 -0400