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* mtd: nand: remove obsolete 'ecclayout' fieldBrian Norris2014-04-16
| | | | | | | This field is never used, except to print it out. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: add a helper to check the SLC/MLC nand chipHuang Shijie2014-04-16
| | | | | | | | Add a helper to check if a nand chip is SLC or MLC. This helper makes the code more readable. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: denali: use NAND_CI_CELLTYPE_MSK instead of hardcoded constantAkinobu Mita2014-04-16
| | | | | | | | | | | Use NAND_CI_CELLTYPE_MSK to extract the cell type from nand_chip.cellinfo instead of hardcoded constant. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Cc: Artem Bityutskiy <dedekind1@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: correct extemded param page error handlingBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | If the ONFI extended parameter page gives codeword_size == 0, the extended ECC information is corrupt and should not be used. Currently, we (correctly) avoid using the information, but we don't report the error to the caller, so the caller doesn't know that we didn't initialize ecc_strength_ds and ecc_step_ds. Now the caller can warn the user that it does not have sufficient information. This also removes the false and useless "ONFI extended param page detected" debug message (it was printed even on the aforementioned corruption, and for the success case, we don't really want a print). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: cleanup ONFI printed errors, warningsBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ONFI detection routine is too verbose in some cases and not verbose enough in others. This patch refactors it to print only when there are significant warnings/errors. Probing in 16-bit mode: It is unnecessary to print until after the READID (address 20h) command. READID *has* to work properly in whatever bus width configuration we are in, or else no identification mode works. So we can silence some useless warnings on systems which come up in 16-bit mode and do not even respond with an O-N-F-I string. Valid parameter page: Nobody needs to see this. Do we inform the user every time other hardware responds properly? Instead, add an error message if *no* uncorrupted parameter pages are found. ONFI ECC: Most drivers don't yet use the reported minimum ECC values, so it shouldn't yet be a fatal condition if the extended parameter page is incorrect. But we should at least give a warning for the corner cases that we don't expect. ONFI flash detected: Nobody needs to see this. This is the expected case, that we detect ONFI properly, or else it wasn't ONFI-compliant and is detected by some other routine. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Huang Shijie <b32955@freescale.com> Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: fix memory leak in ONFI extended parameter pageBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | | | This fixes a memory leak in the ONFI support code for detecting the required ECC levels from this commit: commit 6dcbe0cdd83fb5f77be4f44c9e06c535281c375a Author: Huang Shijie <b32955@freescale.com> Date: Wed May 22 10:28:27 2013 +0800 mtd: get the ECC info from the Extended Parameter Page In the success case, we never freed the 'ep' buffer. Also, this fixes an oversight in the same commit where we (harmlessly) freed the NULL pointer. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: fixup kerneldoc, rename parameterBrian Norris2014-04-16
| | | | | | | | | | | | First, the function argument is 'offset' not 'column'. Second, the 'data_buf' name is inconsistent with the rest of this file. Just use 'buf'. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Gupta, Pekon <pekon@ti.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: set ONFI nand's default hooks in nand_set_defaults()Huang Shijie2014-04-16
| | | | | | | | | | | | We may do some ONFI get/set features operations before we call the nand_scan_tail(). So move the default ONFI nand hooks into nand_set_defaults(). Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: set the ecc step size for master/slave mtd_infoHuang Shijie2014-04-16
| | | | | | | | | Set the ecc step size for master/slave mtd_info{}. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: silence some shift wrap warningsDan Carpenter2014-04-16
| | | | | | | | | | | | There are static checkers which complain when we declare variables as 64 bit bitfields but only use the lower 32 bits because of shift wrapping. In this case "len" is declared as u64 as opposed to unsigned long or something which might be 32 bits. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: parse out the ECC info for the full-id nand chipsHuang Shijie2014-04-16
| | | | | | | | Parse out the ECC information for the full-id nand chips. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: replace the hardcode with the onfi_feature()Huang Shijie2014-04-16
| | | | | | | | | | | The current code uses the hardcode to detect the 16-bit bus width. Use the onfi_feature() to replace it. Signed-off-by: Huang Shijie <b32955@freescale.com> [Brian: small fixup] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: get the ECC info from the Extended Parameter PageHuang Shijie2014-04-16
| | | | | | | | | | | | | | | | | | | | | Since the ONFI 2.1, the onfi spec adds the Extended Parameter Page to store the ECC info. The onfi spec tells us that if the nand chip's recommended ECC codeword size is not 512 bytes, then the @ecc_bits is 0xff. The host _SHOULD_ then read the Extended ECC information that is part of the extended parameter page to retrieve the ECC requirements for this device. This patch implement the reading of the Extended Parameter Page, and parses the sections for ECC type, and get the ECC info from the ECC section. Tested this patch with Micron MT29F64G08CBABAWP. Acked-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Huang Shijie <b32955@freescale.com> Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: get the ECC info from the parameter page for ONFI nandHuang Shijie2014-04-16
| | | | | | | | | | From the ONFI spec, we can just get the ECC info from the @ecc_bits field of the parameter page. Signed-off-by: Huang Shijie <b32955@freescale.com> Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: detect OOB size for Toshiba 24nm raw SLCBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Toshiba NAND datasheets have not been very forthcoming on OOB size information; they do not provide any bitfields in the ID string for spare area. In their 24nm technology flash, however, Toshiba migrated their NAND to have 32 bytes spare per 512 bytes of page area (up from the traditional 16 bytes), as they now require 8-bit ECC or higher. I have discussed this issue directly with Toshiba representatives, and they acknowledge this problem. They recommend detecting these flash based on their technology node as follows: For 24nm Toshiba SLC raw NAND (not BENAND -- Built-in Ecc NAND), there are 32 bytes of spare area for every 512 bytes of in-band data area. We can implement this rule with the following snippet of a device ID decode table, which applies to all their 43nm, 32nm, and 24nm SLC NAND (this table is not fully in the NAND datasheets, but it was provided directly by Toshiba representatives): - ID byte 5, bit[7]: 1 -> BENAND 0 -> raw SLC - ID byte 6, bits[2:0]: 100b -> 43nm 101b -> 32nm 110b -> 24nm 111b -> Reserved I'm also working with Toshiba on including this bitfield description for their 5th and 6th ID bytes in their public data sheets. I will provide the 8-byte ID strings from the two 24nm Toshiba samples I have; their first 6 bytes match the documentation I received from Toshiba: 24nm SLC 1Gbit TC58NVG0S3HTA00 0x98 0xf1 0x80 0x15 0x72 0x16 0x08 0x00 24nm SLC 2Gbit TC58NVG1S3HTA00 0x98 0xda 0x90 0x15 0x76 0x16 0x08 0x00 I have also tested for regressions with: 43nm SLC 4Gbit TC58NVG2S3ETA00 0x98 0xdc 0x90 0x15 0x76 0x14 0x03 0x10 32nm SLC 8Gbit TC58NVG3SOFA00 0x98 0xd3 0x90 0x26 0x76 0x15 0x02 0x08 Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand_base: Only use GET/SET FEATURES command on chips that support them.David Mosberger2014-04-16
| | | | | | | | | Spansion's S34MLx chips support ONFI but not the GET/SET FEATURES calls. Signed-off-by: David Mosberger <dmosberger@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand_base: Use io{read, write}*_rep functions for transferAlexander Shiyan2014-04-16
| | | | | | | | | | This patch replaces the usage of loops in the nand_base code with io{read,write}{8,16}_rep calls instead. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: stop exporting nand_default_bbtBrian Norris2014-04-16
| | | | | | | | | I removed the last non-nand_base users of this, and we shouldn't have any more modules that need to access it. It's only non-static to share between nand_base and nand_bbt. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: remove NAND_BBT_SCANEMPTYBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | NAND_BBT_SCANEMPTY is a strange, badly-supported option with omap as its single remaining user. NAND_BBT_SCANEMPTY was likely used by accident in omap2[1]. And anyway, omap2 doesn't scan the chip for bad blocks (courtesy of NAND_SKIP_BBTSCAN), and so its use of this option is irrelevant. This patch drops the NAND_BBT_SCANEMPTY option. [1] http://lists.infradead.org/pipermail/linux-mtd/2012-July/042902.html Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Ivan Djelic <ivan.djelic@parrot.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: hide in-memory BBT implementation detailsBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | nand_base.c shouldn't have to know the implementation details of nand_bbt's in-memory BBT. Specifically, nand_base shouldn't perform the bit masking and shifting to isolate a BBT entry. Instead, just move some of the BBT code into a new nand_markbad_bbt() interface. This interface allows external users (i.e., nand_base) to mark a single block as bad in the BBT. Then nand_bbt will take care of modifying the in-memory BBT and updating the flash-based BBT (if applicable). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: eliminate castBrian Norris2014-04-16
| | | | | | | | | Just make 'res' an int. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: remove multiplied-by-2 block logicBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | The parent commit 771c568bcf915e708ae819ef9d07d862f7e2da86 ("mtd: nand: add accessors, macros for in-memory BBT") makes the following comment obsolete: /* * Note that numblocks is 2 * (real numblocks) here, see i+=2 * below as it makes shifting and masking less painful */ I don't think it ever could have been "less painful" to have to shift an extra bit (or 2, or 3) at various points in nand_bbt.c (and even outside, since we leak our in-memory format). But now it is certainly more painful, since we have nice macros and functions to retrieve the relevant portions of the BBT. This patch removes any points where the block number is doubled/halved/otherwise-shifted, instead representing the block number in its most natural form: as the actual block number. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: add accessors, macros for in-memory BBTBrian Norris2014-04-16
| | | | | | | | | | | | | | | There is an abundance of magic numbers and complicated shifting/masking logic in the in-memory BBT code which makes the code unnecessary complex and hard to read. This patch adds macros to represent the 00b, 01b, 10b, and 11b memory-BBT magic numbers, as well as two accessor functions for reading and marking the memory-BBT bitfield for a given block. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: gpmi: imx6: fix the wrong method for checking ready/busyHuang Shijie2014-04-16
| | | | | | | | | | | | In the imx6, all the ready/busy pins are binding togeter. So we should always check the ready/busy pin of the chip 0. In the other word, when the CS1 is enabled, we should also check the ready/busy of chip 0; if we check the ready/busy of chip 1, we will get the wrong result. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: gpmi: decouple the chip select from the DMA channelHuang Shijie2014-04-16
| | | | | | | | Decouple the chip select from the DMA channel, we use the DMA channel 0 to accecc all the nand devices. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: gpmi: scan two nand chipsHuang Shijie2014-04-16
| | | | | | | | | | | | | | Some nand chip has two DIEs in a single chip, such as Micron MT29F32G08QAA. Each die has its own chip select pin, so this chip acts as two nand chips. If we only scan one chip, we may find that we only get 2G for this chip, but in actually, this chip's size is 4G. So scan two chips by default. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: gpmi: use DMA channel 0 for all the nand chipsHuang Shijie2014-04-16
| | | | | | | | We only have one DMA channel : the channel 0. Use DMA channel 0 to access all the nand chips. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: gpmi: rewrite the gpmi_ecc_write_oob() to support the jffs2Huang Shijie2014-04-16
| | | | | | | | | | | | | When we use the ECC info which is get from the nand chip's datasheet, we may have some freed oob area now. This patch rewrites the gpmi_ecc_write_oob() to implement the ecc.write_oob(). We also update the comment for gpmi_hw_ecclayout. Yes! We can support the JFFS2 for the SLC nand now. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: gpmi-nand: janitorial cleanup: (commas after last element of ↵Lothar Waßmann2014-04-16
| | | | | | | | | struct initializer) Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: gpmi: fix ECC regressionDavid Woodhouse2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The "legacy" ECC layout used until 3.12-rc1 uses all the OOB area by computing the ECC strength and ECC step size ourselves. Commit 2febcdf84b ("mtd: gpmi: set the BCHs geometry with the ecc info") makes the driver use the ECC info (ECC strength and ECC step size) provided by the MTD code, and creates a different NAND ECC layout for the BCH, and use the new ECC layout. This causes a regression: We can not mount the ubifs which was created by the old NAND ECC layout. This patch fixes this issue by reverting to the legacy ECC layout. We will probably introduce a new device-tree property to indicate that the new ECC layout can be used. For now though, for the imminent 3.12 release, we just unconditionally revert to the 3.11 behaviour. This leaves a harmless cosmetic warning about an unused function. At this point in the cycle I really don't care. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: gpmi: remove the nand_scan()Huang Shijie2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | In order to make the nand_scan() work, the current code uses the hack code to init the @nand_chip->ecc.size and the @nand_chip->ecc.strength. and re-init some the ECC info in the gpmi_pre_bbt_scan(). This code is really a little ugly. The patch does following changes: (1) Use the nand_scan_ident()/nand_scan_tail() to replace the nand_scan(). (2) Init all the necessary values in the gpmi_init_last() before we call the nand_scan_tail(). (3) remove the code setting the ECC info, let the mtd layer to do the real job. (4) remove the gpmi_scan_bbt(). we do not need this function any more. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: gpmi: set the BCH's geometry with the ecc infoHuang Shijie2014-04-16
| | | | | | | | | | | | | If the nand chip provides us the ECC info, we can use it firstly. The set_geometry_by_ecc_info() will use the ECC info, and calculate the parameters we need. Rename the old code to legacy_set_geometry() which will takes effect when there is no ECC info from the nand chip or we fails in the ECC info case. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: gpmi-nand: use more sensible error codes at various placesLothar Waßmann2014-04-16
| | | | | | | | Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: refactor chip->block_markbad interfaceBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | | | | The chip->block_markbad pointer should really only be responsible for writing a bad block marker for new bad blocks. It should not take care of BBT-related functionality, nor should it handle bookkeeping of bad block stats. This patch refactors the 3 users of the block_markbad interface (plus the default nand_base implementation) so that the common code is kept in nand_block_markbad_lowlevel(). It removes some inconsistencies between the various implementations and should allow for more centralized improvements in the future. Because gpmi-nand no longer needs the nand_update_bbt() function, let's stop exporting it as well. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> (for gpmi-nand parts) Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: gpmi-nand: don't use devm_pinctrl_get_select_default() in probeWolfram Sang2014-04-16
| | | | | | | | | | Since commit ab78029 (drivers/pinctrl: grab default handles from device core), we can rely on device core for setting the default pins. Compile tested only. Acked-by: Linus Walleij <linus.walleij@linaro.org> (personally at LCE13) Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: gpmi-nand: remove unnecessary platform_set_drvdata()Jingoo Han2014-04-16
| | | | | | | | | | | | | The driver core clears the driver data to NULL after device_release or on probe failure, since commit 0998d0631001288a5974afc0b2a5f568bcdecb4d (device-core: Ensure drvdata = NULL when no driver is bound). Thus, it is not needed to manually clear the device driver data to NULL. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: gpmi-nand: fix error return from gpmi_get_clks()Michał Mirosław2014-04-16
| | | | | | | | Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: mxc_nand: remove duplicated ecc_stats countingMichael Grzeschik2014-02-13
| | | | | | | | | | | | commit 0566477762f9e174e97af347ee9c865f908a5647 upstream. The ecc_stats.corrected count variable will already be incremented in the above framework-layer just after this callback. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mtd: gpmi: fix kernel BUG due to racing DMA operationsHuang Shijie2013-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 7b3d2fb92067bcb29f0f085a9fa9fa64920a6646 upstream. [1] The gpmi uses the nand_command_lp to issue the commands to NAND chips. The gpmi issues a DMA operation with gpmi_cmd_ctrl when it handles a NAND_CMD_NONE control command. So when we read a page(NAND_CMD_READ0) from the NAND, we may send two DMA operations back-to-back. If we do not serialize the two DMA operations, we will meet a bug when 1.1) we enable CONFIG_DMA_API_DEBUG, CONFIG_DMADEVICES_DEBUG, and CONFIG_DEBUG_SG. 1.2) Use the following commands in an UART console and a SSH console: cmd 1: while true;do dd if=/dev/mtd0 of=/dev/null;done cmd 1: while true;do dd if=/dev/mmcblk0 of=/dev/null;done The kernel log shows below: ----------------------------------------------------------------- kernel BUG at lib/scatterlist.c:28! Unable to handle kernel NULL pointer dereference at virtual address 00000000 ......................... [<80044a0c>] (__bug+0x18/0x24) from [<80249b74>] (sg_next+0x48/0x4c) [<80249b74>] (sg_next+0x48/0x4c) from [<80255398>] (debug_dma_unmap_sg+0x170/0x1a4) [<80255398>] (debug_dma_unmap_sg+0x170/0x1a4) from [<8004af58>] (dma_unmap_sg+0x14/0x6c) [<8004af58>] (dma_unmap_sg+0x14/0x6c) from [<8027e594>] (mxs_dma_tasklet+0x18/0x1c) [<8027e594>] (mxs_dma_tasklet+0x18/0x1c) from [<8007d444>] (tasklet_action+0x114/0x164) ----------------------------------------------------------------- 1.3) Assume the two DMA operations is X (first) and Y (second). The root cause of the bug: Assume process P issues DMA X, and sleep on the completion @this->dma_done. X's tasklet callback is dma_irq_callback. It firstly wake up the process sleeping on the completion @this->dma_done, and then trid to unmap the scatterlist S. The waked process P will issue Y in another ARM core. Y initializes S->sg_magic to zero with sg_init_one(), while dma_irq_callback is unmapping S at the same time. See the diagram: ARM core 0 | ARM core 1 ------------------------------------------------------------- (P issues DMA X, then sleep) --> | | (X's tasklet wakes P) --> | | | <-- (P begin to issue DMA Y) | (X's tasklet unmap the | scatterlist S with dma_unmap_sg) --> | <-- (Y calls sg_init_one() to init | scatterlist S) | [2] This patch serialize both the X and Y in the following way: Unmap the DMA scatterlist S firstly, and wake up the process at the end of the DMA callback, in such a way, Y will be executed after X. After this patch: ARM core 0 | ARM core 1 ------------------------------------------------------------- (P issues DMA X, then sleep) --> | | (X's tasklet unmap the | scatterlist S with dma_unmap_sg) --> | | (X's tasklet wakes P) --> | | | <-- (P begin to issue DMA Y) | | <-- (Y calls sg_init_one() to init | scatterlist S) | Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mtd: nand: hack ONFI for non-power-of-2 dimensionsBrian Norris2013-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 4355b70cf48363c50a9de450b01178c83aba8f6a upstream. Some bright specification writers decided to write this in the ONFI spec (from ONFI 3.0, Section 3.1): "The number of blocks and number of pages per block is not required to be a power of two. In the case where one of these values is not a power of two, the corresponding address shall be rounded to an integral number of bits such that it addresses a range up to the subsequent power of two value. The host shall not access upper addresses in a range that is shown as not supported." This breaks every assumption MTD makes about NAND block/chip-size dimensions -- they *must* be a power of two! And of course, an enterprising manufacturer has made use of this lovely freedom. Exhibit A: Micron MT29F32G08CBADAWP "- Plane size: 2 planes x 1064 blocks per plane - Device size: 32Gb: 2128 blockss [sic]" This quickly hits a BUG() in nand_base.c, since the extra dimensions overflow so we think it's a second chip (on my single-chip setup): ONFI param page 0 valid ONFI flash detected NAND device: Manufacturer ID: 0x2c, Chip ID: 0x44 (Micron MT29F32G08CBADAWP), 4256MiB, page size: 8192, OOB size: 744 ------------[ cut here ]------------ kernel BUG at drivers/mtd/nand/nand_base.c:203! Internal error: Oops - BUG: 0 [#1] SMP ARM [... trim ...] [<c02cf3e4>] (nand_select_chip+0x18/0x2c) from [<c02d25c0>] (nand_do_read_ops+0x90/0x424) [<c02d25c0>] (nand_do_read_ops+0x90/0x424) from [<c02d2dd8>] (nand_read+0x54/0x78) [<c02d2dd8>] (nand_read+0x54/0x78) from [<c02ad2c8>] (mtd_read+0x84/0xbc) [<c02ad2c8>] (mtd_read+0x84/0xbc) from [<c02d4b28>] (scan_read.clone.4+0x4c/0x64) [<c02d4b28>] (scan_read.clone.4+0x4c/0x64) from [<c02d4c88>] (search_bbt+0x148/0x290) [<c02d4c88>] (search_bbt+0x148/0x290) from [<c02d4ea4>] (nand_scan_bbt+0xd4/0x5c0) [... trim ...] ---[ end trace 0c9363860d865ff2 ]--- So to fix this, just truncate these dimensions down to the greatest power-of-2 dimension that is less than or equal to the specified dimension. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mtd: nand: fix NAND_BUSWIDTH_AUTO for x16 devicesBrian Norris2013-09-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 68e8078072e802e77134664f11d2ffbfbd2f8fbe upstream. The code for NAND_BUSWIDTH_AUTO is broken. According to Alexander: "I have a problem with attach NAND UBI in 16 bit mode. NAND works fine if I specify NAND_BUSWIDTH_16 option, but not working with NAND_BUSWIDTH_AUTO option. In second case NAND chip is identifyed with ONFI." See his report for the rest of the details: http://lists.infradead.org/pipermail/linux-mtd/2013-July/047515.html Anyway, the problem is that nand_set_defaults() is called twice, we intend it to reset the chip functions to their x16 buswidth verions if the buswidth changed from x8 to x16; however, nand_set_defaults() does exactly nothing if called a second time. Fix this by hacking nand_set_defaults() to reset the buswidth-dependent functions if they were set to the x8 version the first time. Note that this does not do anything to reset from x16 to x8, but that's not the supported use case for NAND_BUSWIDTH_AUTO anyway. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reported-by: Alexander Shiyan <shc_work@mail.ru> Tested-by: Alexander Shiyan <shc_work@mail.ru> Cc: Matthieu Castet <matthieu.castet@parrot.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mtd: omap2: allow bulding as a moduleArnd Bergmann2013-08-15
| | | | | | | | | | | | | | | | | | | | | | | commit 930d800bded771b26d9944c47810829130ff7c8c upstream. The omap2 nand device driver calls into the the elm code, which can be a loadable module, and in that case it cannot be built-in itself. I can see no reason why the omap2 driver cannot also be a module, so let's make the option "tristate" in Kconfig to fix this allmodconfig build error: ERROR: "elm_config" [drivers/mtd/nand/omap2.ko] undefined! ERROR: "elm_decode_bch_error_page" [drivers/mtd/nand/omap2.ko] undefined! Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Tony Lindgren <tony@atomide.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Cc: Afzal Mohammed <afzal@ti.com> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* drivers/mtd/nand: don't check resource with devm_ioremap_resourceWolfram Sang2013-05-18
| | | | | | | devm_ioremap_resource does sanity checks on the given resource. No need to duplicate this in the driver. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* Merge tag 'for-linus-20130509' of git://git.infradead.org/linux-mtdLinus Torvalds2013-05-09
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MTD update from David Woodhouse: - Lots of cleanups from Artem, including deletion of some obsolete drivers - Support partitions larger than 4GiB in device tree - Support for new SPI chips * tag 'for-linus-20130509' of git://git.infradead.org/linux-mtd: (83 commits) mtd: omap2: Use module_platform_driver() mtd: bf5xx_nand: Use module_platform_driver() mtd: denali_dt: Remove redundant use of of_match_ptr mtd: denali_dt: Change return value to fix smatch warning mtd: denali_dt: Use module_platform_driver() mtd: denali_dt: Fix incorrect error check mtd: nand: subpage write support for hardware based ECC schemes mtd: omap2: use msecs_to_jiffies() mtd: nand_ids: use size macros mtd: nand_ids: improve LEGACY_ID_NAND macro a bit mtd: add 4 Toshiba nand chips for the full-id case mtd: add the support to parse out the full-id nand type mtd: add new fields to nand_flash_dev{} mtd: sh_flctl: Use of_match_ptr() macro mtd: gpio: Use of_match_ptr() macro mtd: gpio: Use devm_kzalloc() mtd: davinci_nand: Use of_match_ptr() mtd: dataflash: Use of_match_ptr() macro mtd: remove h720x flash support mtd: onenand: remove OneNAND simulator ...
| * mtd: bf5xx_nand: Use module_platform_driver()Sachin Kamat2013-04-05
| | | | | | | | | | | | | | | | | | module_platform_driver macro removes some boilerplate and makes the code simpler. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: denali_dt: Remove redundant use of of_match_ptrSachin Kamat2013-04-05
| | | | | | | | | | | | | | | | | | Since this driver is dt only and denali_nand_dt_ids is always compiled in, use of of_match_ptr() macro is not necessary. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: denali_dt: Change return value to fix smatch warningSachin Kamat2013-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | platform_get_irq() also returns -ENXIO upon failure. Use it instead of hardcoded return type. Fixes the following smatch warning: drivers/mtd/nand/denali_dt.c:93 denali_dt_probe() info: why not propagate 'denali->irq' from platform_get_irq() instead of (-6)? Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: denali_dt: Use module_platform_driver()Sachin Kamat2013-04-05
| | | | | | | | | | | | | | | | | | module_platform_driver() removes some boilerplate and makes the code simpler. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: denali_dt: Fix incorrect error checkSachin Kamat2013-04-05
| | | | | | | | | | | | | | | | | | The return value of devm_ioremap_nocache should be checked here instead of res. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: nand: subpage write support for hardware based ECC schemesGupta, Pekon2013-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for subpage (partial-page) writes when using hardware based ECC schemes. Advantages: (1) reduces storage overhead when using file-systems like UBIFS, which store LEB header at page-size granularity. (2) allows independent subpage writes, thereby increasing NAND storage efficiency for non-page aligned data. + updated cafe_nand and lpc32xx_mlc NAND drivers for change in chip->write_page interface. Signed-off-by: Gupta, Pekon <pekon@ti.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-21 13:18:22 -0400