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* ENGR00319936-1 mmc: sdhci-esdhc-imx: do not enable wakeup by defaultDong Aisheng2014-06-25
| | | | | | | | | | | | | | | After adding mega fast support, the default enabled usdhc wakeup will block M/F to gate off power domain. To avoid this issue, we only claim wakeup capability and reply on user to enable it via sysfs according to real needs. The drawback of such change is that for SDIO WiFi Wakeup On Wireless feature, User has to enable both uSDHC and WiFi WoW wakeup mannually to make WoW work well. BTW, due to the wakeup feature is controller itself, so we do not need to reply on WiFi PM flags to enable it. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00302227-6 mmc: sdhci-esdhc-imx: add imx6sx supportDong Aisheng2014-04-16
| | | | | | | | The imx6sx usdhc is derived from imx6sl, the difference is minor. imx6sx have the errata ESDHC_FLAG_ERR004536 fixed. So introduce a new compatible string for imx6sx to distinguish them. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00295564 mmc: sdhci-esdhc-imx: no need busfreq for imx6qdlDong Aisheng2014-04-16
| | | | | | | | | | | | | The usdhc of i.MX6Q/DL can work well under low power mode without request high bus freq. So we do not need request bus freq for i.MX6Q/DL. It can save power for i.MX6D/DL due to it saves a lot busfreq switch cost as well as the CPU time runing on high bus freq after switch during low power mode. A new flag ESDHC_FLAG_BUSFREQ is added to indicated this requirement. Currently only i.MX6SL is using it. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00295184-7 mmc: sdhci: do not enable card cd wakeup for gpio caseDong Aisheng2014-04-16
| | | | | | | Do not need to enable the controller card cd interrupt wakeup if using GPIO as card detect since it's meaningless. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00295184-5 mmc: sdhci-esdhc-imx: add wakeup feature for sdio irqDong Aisheng2014-04-16
| | | | | | | Enable wakeup for SDIO IRQ when the host is able to keep power during suspend. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00295184-3 mmc: sdhci-esdhc-imx: add keep power feature during suspendDong Aisheng2014-04-16
| | | | | | | IMX boards can keep power for cards during suspend. User can enable it from device tree. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00295184-1 mmc: sdhci: do not enable card detect interrupt for gpio cd typeDong Aisheng2014-04-16
| | | | | | | | | | | Except SDHCI_QUIRK_BROKEN_CARD_DETECTION and MMC_CAP_NONREMOVABLE, we also do not need to handle controller native card detect interrupt for gpio as card detect case. If we wrong enabled the card detect interrupt for gpio case, it will cause a lot of unexpected card detect interrupts during data transfer which should not happen. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00292140 mmc: sdhci: fix possible sleep in atomic in sdio_irq enable ↵Dong Aisheng2014-04-16
| | | | | | | | | | | function The sdhci_runtime_pm_get API is able to sleep, so should not call it in sdhci_enable_sdio_irq_nolock which is executed with spin_lock_irqsave in sdhci_enable_sdio_irq. Move it out of spin lock to fix this issue. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00289406-2 mmc: sdhci-esdhc-imx: add SDHCI_QUIRK2_NOSTD_TIMEOUT_COUNTERDong Aisheng2014-04-16
| | | | | | | | The max timeout counter for uSDHC is SDCLK x (1 << 28), not as standard controller defined as TMCLK x (1 <<27). Add SDHCI_QUIRK2_NOSTD_TIMEOUT_COUNTER quirk to handle it. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00289406-1 mmc: sdhci: add quirk for get max timeout counterDong Aisheng2014-04-16
| | | | | | | | | The max timeout counter of some SoCs like i.MX6 uSDHC may not be standard, add SDHCI_QUIRK2_NOSTD_TIMEOUT_COUNTER quirk to get the correct max timeout counter from platform specific code. Then we can calculate the correct max_discard_to value. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00289279 mmc: sdhci: get runtime pm when sdio irq is enabledDong Aisheng2014-04-16
| | | | | | | | SDIO cards may need clock to send the card interrupt to host. Thus, we get runtime pm when sdio irq is enabled to prevent the clock resource is released and put it when sdio irq is disabled. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00288842 mmc: sdhci-esdhc-imx: add ADMA Length Mismatch errata fixDong Aisheng2014-04-16
| | | | | | | | | | The uSDHC has an ADMA Length Mismatch errata ERR004536 which may cause ADMA work abnormally. The errata has already been fixed for i.MX6Q TO1.2 and i.MX6DL TO1.1 by enable the bit 7 in 0x6c register. Unfortunately this fix is not included in i.MX6SL. So we disable ADMA for i.MX6SL and use SDMA instead. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00287331-3 sdhci-esdhc-imx: do not need disable clock during remove functionDong Aisheng2014-04-16
| | | | | | | | | | | | | | Since the clock is managed by runtime pm currently, we do not need disable it again during driver remove function, or it will cause clock disable count mismatch issue since the clocks have already been disabled. mx6slevk:/sys/bus/platform/drivers/sdhci-esdhc-imx# echo 2194000.usdhc > unbind mmc1: card aaaa removed ------------[ cut here ]------------ WARNING: at drivers/clk/clk.c:780 clk_disable+0x18/0x24() .... Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00287331-2 sdhci-esdhc-imx: use bus freq in runtime pmDong Aisheng2014-04-16
| | | | | | | Request BUS_FREQ_HIGH when bus is busy and then release BUS_FREQ_HIGH when bus becomes idle. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* mmc: sdhci: fix ctrl_2 on super-speed selectionGiuseppe CAVALLARO2014-04-16
| | | | | | | | | | | This patch fixes the HC ctrl_2 programming where, in case of SDR104 and HS200, we have to write 100b in the the UHS Mode bits. We wrote 101b that is reserved from Arasan Specs. Reported-by: Youssef Triki <youssef.triki@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Chris Ball <cjb@laptop.org> (cherry picked from commit 599115686d8f62999a871f7d7ee87de3b939b258)
* mmc: sdhci: fix caps2 for HS200Giuseppe CAVALLARO2014-04-16
| | | | | | | | | | | | | | Although the HC supports HS200 (eMMC) the caps2 are always zero; this means there's no way to use the super speed mode (when init the card). If the HC support SDR104, for SD3.0, so it also supports HS200 for eMMC and this patch just sets the MMC_CAP2_HS200 in the host caps2 field. Reported-by: Youssef Triki <youssef.triki@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Reviewed-by: Philip Rakity <prakity@nvidia.com> Signed-off-by: Chris Ball <cjb@laptop.org> (cherry picked from commit 156e14b126ffb6f040bc6f1aff3c51077e42a744)
* mmc: sdhci: add ability to stay runtime-resumed if the card is powered upAdrian Hunter2014-04-16
| | | | | | | | | | | If card power is dependent on SD bus power then the host controller must not be runtime suspended while the card is powered up. Add the ability to stay runtime-resumed in that case and enable it with a new quirk SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Chris Ball <cjb@laptop.org> (cherry picked from commit f0710a557cb17746b09234f01073a2cdafe4f4a5)
* ENGR00286971-4 Revert "ENGR00278504-1 mmc: sdhci: add quirk for broken acmd23"Dong Aisheng2014-04-16
| | | | | | | | | The ACMD23 unwork issue is fixed now. so the former quirk to disable ACMD23 can be removed. This reverts commit fd27fce042bfd289eab6dbb7c98ab3adb48ca25b. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00286971-3 Revert "ENGR00278504-2 sdhci-esdhc-imx: add broken auto cmd23"Dong Aisheng2014-04-16
| | | | | | | | | | This reverts commit 7b725c102e1ddfbaca5856af7c286bfd626363ea. Conflicts: drivers/mmc/host/sdhci-esdhc-imx.c Signed-off-by: Dong Aisheng <b29396@freescale.com>
* mmc: sdhci: Avoid needless loop while handling SDIO interrupts in sdhci_irq()Alexey Neyman2014-04-16
| | | | | | | | | | Ignore Card Interrupt bit in the interrupt status if we already know that mmc_signal_sdio_irq() is going to be called at the end of sdhci_irq(). This avoids a needless loop in sdhci_irq() repeatedly reading interrupt status and doing nothing. Signed-off-by: Alexey Neyman <stilor@att.net> Acked-by: Dong Aisheng <b29396@freescale.com>
* mmc: sdhci-esdhc-imx: add runtime pm supportDong Aisheng2014-04-16
| | | | | | | | The root clock will be disabled in runtime pm which can be used to save power. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-esdhc-imx: fix runtime pm unblance issueDong Aisheng2014-04-16
| | | | | | | | | | Since we're using common esdhc_send_command for tuning commands and the core code will call pm_runtime_put after command is finished. So we add a pm_runtime_get_sync here to get the blance. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-esdhc-imx: clear SDHCI_CTRL_EXEC_TUNING should not affect other bitsDong Aisheng2014-04-16
| | | | | | | | | | | | | | | | | | | | | Current code will clear all turning related bits like ESDHC_STD_TUNING_EN and ESDHC_MIX_CTRL_FBCLK_SEL when clear SDHCI_CTRL_EXEC_TUNING. This may cause the card which has already passed the turning to become unwork since the turning status lost. We observed this failure when enable runtime pm. BTW, imx needs to enable ESDHC_MIX_CTRL_FBCLK_SEL bit for turned clock. The FBCLK_SEL will be cleared when SDHCI_CTRL_TUNED_CLK is cleared and SDHCI_CTRL_EXEC_TUNING is not set. This is used in case we change to another normal card from a UHS card in the same slot. FBCLK_SEL is not needed for normal card. After that, SDHCI_CTRL_EXEC_TUNING will only affect ESDHC_MIX_CTRL_EXE_TUNE. Clearing it does not affect the turned card to remain working on UHS mode. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-esdhc-imx: tuning bits should not be cleared during resetDong Aisheng2014-04-16
| | | | | | | | | | We should not clear tuning bits during reset or the SD3.0/eMMC4.5 card working on UHS mode may not work after reset since the former tuning settings was lost. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-pltfm: export pltfm suspend/resume apiDong Aisheng2014-04-16
| | | | | | | | It is helpful for platforms code to use to elimiate duplicated code. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-esdhc-imx: add eMMC HS200 mode supportDong Aisheng2014-04-16
| | | | | | | Add support for eMMC 4.5 cards to work on hs200 mode. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org>
* mmc: sdhci-esdhc-imx: add MMC_CAP_1_8V_DDR for mx6Dong Aisheng2014-04-16
| | | | | | | The i.MX6 supports 1.8v/3.3v eMMC DDR mode, so add this flag. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org>
* mmc: sdhci-esdhc-imx: fix cpas over write issueDong Aisheng2014-04-16
| | | | | | | | We should use '|=' instead '=', or it may over write the original caps assigned before this line. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org>
* mmc: sdhci-esdhc-imx: add SDHCI_TRANSFER_MODE read functionDong Aisheng2014-04-16
| | | | | | | | Used to read out the correct value of SDHCI_TRANSFER_MODE register for upper layer. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org>
* mmc: sdhci: clear auto cmd setting bits for no data cmdsDong Aisheng2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | The auto cmd settings bits should be cleared before sending new commands or we may receive command timeout error for normal commands due to wrongly pre-sent auto cmd. e.g. we receive CMD13 timeout error due to ACMD23 is wrongly enabled by former data commands. mmc2: new high speed DDR MMC card at address 0001 mmcblk1: mmc2:0001 SEM08G 7.39 GiB mmcblk1boot0: mmc2:0001 SEM08G partition 1 2.00 MiB mmcblk1boot1: mmc2:0001 SEM08G partition 2 2.00 MiB mmcblk1rpmb: mmc2:0001 SEM08G partition 3 128 KiB mmcblk1: p1 p2 p3 p4 < p5 p6 p7 > mmc2: Timeout waiting for hardware interrupt. mmcblk1boot1: unknown partition table mmc2: Timeout waiting for hardware interrupt. mmcblk1boot0: unknown partition table Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org>
* mmc: sdhci: remove unneeded call when have preset value quirkDong Aisheng2014-04-16
| | | | | | | | | Remove unneeded call of call sdhci_enable_preset_value when having SDHCI_QUIRK2_PRESET_VALUE_BROKEN. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci-esdhc-imx: add preset value quirk for mx6Dong Aisheng2014-04-16
| | | | | | | | The i.MX6 does not support preset value feature. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci-esdhc-imx: enable SDR50 tuning for imx6q/dlDong Aisheng2014-04-16
| | | | | | | | | The imx6q/dl supports SDR50 tunning, enable it for a better timing on SDR50 mode. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci-esdhc-imx: add delay line setting supportDong Aisheng2014-04-16
| | | | | | | | | | | | | | | | | The DLL(Delay Line) is newly added to assist in sampling read data. The DLL provides the ability to programmatically select a quantized delay (in fractions of the clock period) regardless of on-chip variations such as process, voltage and temperature (PVT). This patch adds a user interface to set slave delay line via device tree. It's usually used in high speed mode like mmc DDR mode when the signal quality is not good caused by board design, e.g. the signal path is too long. User can manually set delay line to find a suitable data sampling window for card to work properly. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci-esdhc-imx: add DDR mode support for mx6Dong Aisheng2014-04-16
| | | | | | | | | | | | | | | | | | | When DDR mode is enabled, the initial pre_div should be 2. And the pre_div value should be changed accordingly from ... 02h) Base clock divided by 4 01h) Base clock divided by 2 00h) Base clock divided by 1 to .. 02h) Base clock divided by 8 01h) Base clock divided by 4 00h) Base clock divided by 2 Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci: report error once the maximum tuning loops exhausted or timeoutDong Aisheng2014-04-16
| | | | | | | | | | The original code missed to report an error when the maximum tuning loops exhausted or timeout, it will cause the upper layer to wrongly think the tuning process is passed. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci-esdhc-imx: fix reading cap_1 register value for mx6slDong Aisheng2014-04-16
| | | | | | | | | | | | When reading CAP_1 register for mx6sl, ignore bit[0-15] as it stores CAP_2 register value which is new introduced in mx6sl. Without this fix, the max clock for mx6sl may not be correct since it's wrongly calculated by reading CAP_1 register. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci-esdhc-imx: add std tuning support for mx6slDong Aisheng2014-04-16
| | | | | | | | | | | | | | | | | The mx6sl supports standard sdhci tuning, then esdhc_executing_tuning is only needed for mx6q/dl. We introduce is_imx6_usdhc() and is_imx6sl_usdhc() to handle the difference. The standard tuning is enabled by setting ESDHC_TUNE_CTRL_STD_TUNING_EN bit in new register ESDHC_TUNE_CTRL and operates with new tuning bits defined in SDHCI_ACMD12_ERR register. Note: mx6sl can also work on the old manually tuning mode as mx6q/dl if not enable standard tuning mode. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci-esdhc-imx: create struct esdhc_soc_dataShawn Guo2014-04-16
| | | | | | | | | | | | | | | | | | Create a struct esdhc_soc_data with moving 'flags' field from pltfm_imx_data into it, and pass the pointer of this SoC specific data structure through of_device_id.data directly, so that the translation from enum imx_esdhc_type to flags can be saved. With the change, enum imx_esdhc_type can be eliminated, since we can implement the is_imx*_esdhc() by checking the esdhc_soc_data pointer. The unused is_imx35_esdhc() and is_imx51_esdhc() are also removed, and the others are kept there as we will need to use them to handle some small register differences later, where use of new flags might be a little overkilled. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci-esdhc-imx: pdev->id_entry should be immutableShawn Guo2014-04-16
| | | | | | | | | | | | | | | As a good practice, device driver should not modify pdev->id_entry but keep it immutable. Let's assign of_device_id.data with imx_esdhc_type constants directly, so that we do not have to manipulate pdev->id_entry in .probe(). As the result, sdhci-esdhc-imx53 and sdhci-usdhc-imx6q can be removed from platform_device_id table now, since they will only probe from device tree. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci-esdhc-imx: add flag ESDHC_FLAG_USDHCDong Aisheng2014-04-16
| | | | | | | | | | Add flag ESDHC_FLAG_USDHC to tell that the ESDHC is actually an USDHC block, and replace the is_imx6q_usdhc() occurrences with inline function esdhc_is_usdhc() which checks the flag. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci-esdhc-imx: add flag ESDHC_FLAG_ENGCM07207Shawn Guo2014-04-16
| | | | | | | | | | | | | Just like the use of the flag ESDHC_FLAG_MULTIBLK_NO_INT, let's add another flag ESDHC_FLAG_ENGCM07207 to enable the workaround for errata ENGcm07207 and set the flag for i.MX25 and i.MX35 ESDHC. While at it, let's use BIT() macro for ESDHC_FLAG_MULTIBLK_NO_INT as well. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Chris Ball <chris@printf.net>
* ENGR00278646-11 mmc: sdhci-esdhc-imx: improve sd3.0 stabilityDong Aisheng2014-04-16
| | | | | | | | | | We observed on some sd3.0 cards(Toshiba SDHC U1) that it may require to reset host controller before sending the next tuning command or the tuning may fail and cause the card can not work on uhs mode. The root cause why the card fails on tuning without reset is still unknow. This could be treated as a workaround before finding root cause. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00278646-9 mmc: sdhci-esdhc: set actual_clock in clock settingDong Aisheng2014-04-16
| | | | | | | | | | | | | | | | This enables access the actual_clock via sys. root@imx6qsabreauto:~# cat /sys/kernel/debug/mmc0/ios clock: 198000000 Hz actual clock: 198000000 Hz vdd: 17 (2.9 ~ 3.0 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 2 (4 bits) timing spec: 6 (sd uhs SDR104) signal voltage: 0 (1.80 V) Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00278646-8 mmc: sdhci-esdhc: correct pre_div for imx6qDong Aisheng2014-04-16
| | | | | | | | | | According to spec, the pre_div for imx6q should be 1, or the biggest clock rate we can get is a half of host clock rate. This may cause we can not get the proper clock rate as we want. e.g. if the desired clock is 200Mhz, however, the host clock is 200Mhz too, then it causes the actual clock we get is 100Mhz due to pre_div is 2. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00278646-7 sdhci-esdhc-imx: change pinctrl state according to uhs modeDong Aisheng2014-04-16
| | | | | | | | | | | Without proper pinctrl state, the card may not be able to work on high speed stablely. e.g. SDR104. This patch add pinctrl state switch code according to different uhs mode include 100mhz sate, 200mhz sate and normal state (50Mhz and below). Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00278646-6 sdhci: sdhci-esdhci-imx: add sd3.0 clock tuning supportDong Aisheng2014-04-16
| | | | | | | | | | | | | | | | | Freescale i.MX6Q/DL uSDHC clock tuning progress is a little different from the standard tuning process defined in host controller spec v3.0. Thus we use platform_execute_tuning instead of standard sdhci tuning. The main difference are: 1) not only generate Buffer Read Ready interrupt when tuning is performing. It generates all other DATA interrupts like the normal data command. 2) SDHCI_CTRL_EXEC_TUNING is not automatically cleared by HW, instead it's controlled by SW. 3) SDHCI_CTRL_TUNED_CLK is not automatically set by HW, it's controlled by SW. 4) the clock delay for every tuning is set by SW. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00278646-4 sdhci: sdhci-esdhc-imx: support real clock on and off for imx6qDong Aisheng2014-04-16
| | | | | | | | | | | | | | | | | | The signal voltage switch follow requires to shutdown and output clock in a specific sequence according to standard host controller v3.0 spec. In that timing, the card must really receive clock or not. However, for i.MX6Q, the uSDHC will not output clock even the clock is enabled until there is command or data in transfer on the bus, which will then cause singal voltage switch always to fail. For i.MX6Q, we clear ESDHC_VENDOR_SPEC_FRC_SDCLK_ON bit to let controller to gate off clock automatically and set that bit to force clock output if clock is on. This is required by SD3.0 support. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00278646-3 mmc: sdhci-esdhci: move common esdhc_set_clock to platform driverDong Aisheng2014-04-16
| | | | | | | | | | | | | We need a lot of imx6 specific things into common esdhc_set_clock for support SD3.0 and eMMC DDR mode which is not needed for power pc platforms, so esdhc_set_clock seems not so common anymore. Instead of keeping add platform specfics things into this common API, we choose to move that code into platform driver itself to handle. This can also exclude the dependency between imx and power pc on this headfile and is easy for maintain in the future. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00278646-2 mmc: sdhci: allow platform access of sdhci_send_commandDong Aisheng2014-04-16
| | | | | | It helps for platform code to use it send tuning commands. Signed-off-by: Dong Aisheng <b29396@freescale.com>
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