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* ENGR00298994 ARM: imx: enable cpuidle on i.mx6sxAnson Huang2014-04-16
| | | | | | Enable cpuidle on i.MX6SX, derive from i.MX6Q cpuidle driver. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00299327 ARM: dts: imx6sx-17x17-arm2: add i2c1-4 supportFugang Duan2014-04-16
| | | | | | | Add i2c1-4 support for imx6sx-17x17-arm2 platform. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00299323-14 ARM: dts: imx6sx-17x17-arm2: add enet1 and enet2 for i.MX6sx ↵Fugang Duan2014-04-16
| | | | | | | | arm2 board Enable enet1 and enet2 for imx6sx arm2 board support. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00299323-13 ARM:imx:imx6sx: add enet init for imx6sx platformFugang Duan2014-04-16
| | | | | | | | | - Init GPR1 register to select enet1 and enet2 refrence clock from internal PLL. - Add enet MAC address checking from fuse. - Add some phy fixup, set RGMII IO voltage to 1.8V. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00299323-12 ARM: dts: imx6sx: add fec nodes and iomux pin groupFugang Duan2014-04-16
| | | | | | | - Add enet1 and enet2 nodes. - Add enet iomux pin group for enet1 and enet2. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00299323-11 ARM: imx: Add i.mx6sx enet clk supportFugang Duan2014-04-16
| | | | | | | | | Add i.mx6sx enet clk support: - Add enet2 refrence clock. - Add PTP clock. - Set enet system AHB clock to 200Mh. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00298524-6 ARM: imx: enable suspend/resume for i.mx6sxAnson Huang2014-04-16
| | | | | | | | | | | | | | | Enable suspend/resume feature for i.mx6sx 17x17 arm2 board, for dsm mode, as we use dedicated ocram space for low power function(start from 0x8f8000), but ROM code still use previous ocram space(0x900000) for checking jump address, so we need to enable ROMCP of data patch to workaround this issue. This patch only enables the suspend/resume function, will add low power related operation such as DDR IO HZ mode setting later, as there is still some necessary reference manual missing. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00298524-5 ARM: dts: imx6sx: Add romcp moduleAnson Huang2014-04-16
| | | | | | Add ROMCP module and set it as syscon. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00298524-3 ARM: imx: Enable imx6sx in defconfigAnson Huang2014-04-16
| | | | | | Enable imx6sx build in defconfig. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00298524-2 ARM: imx: Add MSL support for i.mx6sxAnson Huang2014-04-16
| | | | | | | | | | | | | | It adds initial MSL support for i.mx6sx, including below features: 1. add cpu type check; 2. add system timer support; 3. add clock tree support; 4. add machine layer init support; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> Acked-by: Jason Liu
* ENGR00298524-1 ARM: dts: imx6sx: Add i.mx6sx soc dts supportAnson Huang2014-04-16
| | | | | | | | Add i.MX6SX SOC and 17x17 arm2 board dts support, including necessary modules info. Signed-off-by: Anson Huang <b20788@freescale.com> Acked-by: Jason Liu
* ENGR00296547-2 ARM: dts: imx6qdl-sabreauto: add a new pinctrl for ECSPI1Huang Shijie2014-04-16
| | | | | | | | | The ECSPI1 needs the GPIO3_19 to select/de-select the SPI NOR chip. This patch adds a new pinctrl for this GPIO, and select this pinctrl when we enable the ECSPI1. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00296547-1 ARM: dts: imx6qdl-sabreauto-ecspi: use the gpio5_4 to enable ↵Huang Shijie2014-04-16
| | | | | | | | | | the EIM_D18 The ECSPI needs the pin EIM_D18 which is controlled by the steering. So we have to configurate the EIM_A24 to GPIO, and select the GPIO to LOW status. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ARM: 7873/1: vfp: clear vfp_current_hw_state for dying cpuYuanyuan Zhong2014-04-16
| | | | | | | | | | | The CPU_DYING notifier is called by cpu stopper task which does not own the context held in the VFP hardware. Calling vfp_force_reload() has no effect. Replace it with clearing vfp_current_hw_state. Signed-off-by: Yuanyuan Zhong <zyy@motorola.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> (cherry picked from commit 384b38b66947b06999b3e39a596d4f2fb94f77e4)
* ENGR00296510 ARM: dts: imx6qdl-sabreauto: use the gpio5_4 to enable the EIM_D18Huang Shijie2014-04-16
| | | | | | | | The WEIN NOR needs the pin EIM_D18 which is controlled by the steering. So we have to configurate the EIM_A24 to GPIO, and select the GPIO to LOW status. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00296212 ARM: imx_v7_defconfig: Select CONFIG_HIGHMEMAnson Huang2014-04-16
| | | | | | | | | | Select HIGHMEM config to avoid the vmalloc region overlap on boards that have big RAM. Previous imx_v7_defconfig change(CONFIG_CRYPTO_TEST) did NOT follow the savedefconfig rule, fix it as well. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00295892-2: ARM: dts: imx6qdl-sabresd: add retain-state-suspended ↵Robin Gong2014-04-16
| | | | | | | | property in dts Add property "retain-state-suspended" in dts. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00295814 ARM: dts: imx6qdl: correct gpio key's active stateAnson Huang2014-04-16
| | | | | | | | | | From schematic, below GPIO keys' active state is low, so we need to set correct active state in dts. i.MX6Q/DL-SABRESD board: power, vol+ and vol-. i.MX6Q/DL-SABREAUTO board: home, back, prog, vol+ and vol-. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00291086 crypto kernel module speed test in single failJay Monkman2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tcrypt module is used to test the crypto API by being passed a mode=<value> during module load. The test runs to completion before insmod/modprobe returns. That makes the RCU stall detection in newer kernels unhappy. The simple fix is to add CONFIG_PREEMPT to the kernel config. That's what this patch does. If that introduces other problems, crypto/tcrypt.c can be modified to call schedule() in the correct places. Here's a patch that should work if this one has to be reverted: --- a/crypto/tcrypt.c +++ b/crypto/tcrypt.c @@ -33,6 +33,7 @@ #include <linux/jiffies.h> #include <linux/timex.h> #include <linux/interrupt.h> +#include <linux/sched.h> #include "tcrypt.h" #include "internal.h" @@ -182,6 +183,7 @@ static void test_cipher_speed(const char *algo, int enc, unsigned int sec, goto out; } + schedule(); printk("test %u (%d bit key, %d byte blocks): ", i, *keysize * 8, *b_size); @@ -448,6 +450,7 @@ static void test_hash_speed(const char *algo, unsigned int sec, if (speed[i].klen) crypto_hash_setkey(tfm, tvmem[0], speed[i].klen); + schedule(); printk(KERN_INFO "test%3u " "(%5u byte blocks,%5u bytes per update,%4u updates): ", i, speed[i].blen, speed[i].plen, speed[i].blen / speed[i].plen); @@ -688,12 +691,12 @@ static void test_ahash_speed(const char *algo, unsigned int sec, break; } + schedule(); pr_info("test%3u " "(%5u byte blocks,%5u bytes per update,%4u updates): ", i, speed[i].blen, speed[i].plen, speed[i].blen / speed[i].plen); ahash_request_set_crypt(req, sg, output, speed[i].plen); - if (sec) ret = test_ahash_jiffies(req, speed[i].blen, speed[i].plen, output, sec); @@ -853,6 +856,7 @@ static void test_acipher_speed(const char *algo, int enc, unsigned int sec, goto out_free_req; } + schedule(); pr_info("test %u (%d bit key, %d byte blocks): ", i, *keysize * 8, *b_size); @@ -934,6 +938,7 @@ static void test_available(void) printk("alg %s ", *name); printk(crypto_has_alg(*name, 0, 0) ? "found\n" : "not found\n"); + schedule(); name++; } } Signed-off-by: Jay Monkman <jay.monkman@freescale.com>
* ENGR00295570 ARM: imx_v7_defconfig: enlarge the CMA size from 256MB to 320MBJason Liu2014-04-16
| | | | | | | | In order to support the dual video use-case, the current CMA reserved size is not enough now, need enlarge the CMA size from 256M to 320M by default. Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit ea578e2b5097f619a5a66aff26b7c422ffe30237)
* ENGR00295184-6 dts: imx6: enable sdio wakeup for corresponding boardsDong Aisheng2014-04-16
| | | | | | | | Enable the sdio wakeup capability for SDIO cards. Note: we do not enable it for sabresd usdhc4 since it has a solid eMMC card on it. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00295184-4 dts: imx6: enable keep power capability for corresponding boardsDong Aisheng2014-04-16
| | | | | | | All i.MX6 SabreAuto/SabreSD/EVK has the ability to keep card power during suspend. So add this capability for them. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00295184-2 dts: imx6qdl-sabreauto: use external vmmc for sd3 optionallyDong Aisheng2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | SD3.0 cards require power cycle the card during suspend/resume, or the card re-enumeration after resume will fail to be identified as UHS card since the card is already working on 1.8v mode and refuse to ack the S18R request, thus, it will then work on normal high speed mode instead. We have to use external vmmc regulator to power cycle the card during suspend/resume to reset card signal voltage to 3.3v frist for the later 1.8v voltage switch. However, due to the sabreauto board limitation, we can not use external regulator to powere off card by default since the card power is shared with card detect pullup. Disabling the vmmc regulator will also shutdown the cd pullup which causes incorrect illusion of card exist. (e.g. plug out the card, mmc core wll think the card is exist since cd pin is low but it never can find the card) HW rework removing R695 and enable PAD internal pullup is needed to fix this isssue. User can manually open the mask of vmmc in dts to enable using external regulator if your board has done the rework as said above. Or by default we still do not power off card during suspend. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00293505 ARM: dtsi: imx6qdl-sabresd: Change disp id for mipi dsiLiu Ying2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, by default, we assign ipu display ports for the following 5 types of display devices on the imx6q sabresd platform in this way: ---------------------------------------- | | ipu | di | |----------------------------------------| | ldb channel0 | 1(0 for imx6dl) | 0 | |----------------------------------------| | ldb channel1 | 1(0 for imx6dl) | 1 | |----------------------------------------| | hdmi | 0 | 0 | |----------------------------------------| | mipi dsi | 0 | 0 | |----------------------------------------| | parallel output | 0 | 0 | ---------------------------------------- So, the ipu0 di1 display port is not used by any display device. This patch assigns this unused display port to mipi dsi by default. Acked-by: Robby Cai <R63905@freescale.com> Cc: Oliver Brown <oliver.brown@freescale.com> Cc: Sandor Yu <R01008@freescale.com> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00294026-2 ARM: dts: imx: add viim device node in dtsRobin Gong2014-04-16
| | | | | | Enable viim device node in dts and enable in defconfig Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00291282-7 ARM: imx_v7_defconfig: Add USB PHY NOP driverPeter Chen2014-04-16
| | | | | | It is needed for USB HSIC controller Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00291282-3 ARM: imx6q-arm2-hsic: add usb hsic dtsPeter Chen2014-04-16
| | | | | | | | | Since hsic has pin conflict with ethernet, we disable ethernet at this dts. Besides, please make sure the line of data and strobe has unchanged between board boots up and hsic controller has benn enabled. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00291282-2 ARM: imx6: add more dts entries for hsic controllerPeter Chen2014-04-16
| | | | | | | | | - Add usbphy_nop, hsic uses nop phy driver - Add anatop phandle, hsic needs to access anatop register to change osc clock for different boards - Add phy_type, hsic needs to config PHY parameters at portsc Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00292021-2 ARM: imx6q: correct pll4_audio_div name in cko1_selsNicolin Chen2014-04-16
| | | | | | | There's a typo in cko1_sels[], thus fix it. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00292021-1 arm: dts: imx6sl-evk: Specify the IOMUX value of GPIO4_IO19Nicolin Chen2014-04-16
| | | | | | | | | | We are missing one pull-up resistor attached to GPIO4_IO19 on EVK board, thus use specific IOMUX value to pull up the GPIO4_IO19 by SoC itself. Otherwise, system like Android might not have the ability to determine whether the headphone is currently plugged into the jack. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00290601 [iMX6x] Ensure PLL is powered down when bypass rate is requested.Ranjani Vaidyanathan2014-04-16
| | | | | | | Ensure that PLL is powered down when bypass rate is requested and power it up when some other rate is requested. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00290496-2 ARM: imx_v7_defconfig: Enable gpio-led in configsRobin Gong2014-04-16
| | | | | | Enable the related option of configuration. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00290496-1 ARM: imx6: Add charging led support on Sabresd boardRobin Gong2014-04-16
| | | | | | | Enable led lighting while the board in charging status. Implement it on Sabresd board. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00289885 [iMX6Q] Add Secure Memory and SECVIO support.Dan Douglass2014-04-16
| | | | | | | | | 1. Pull in secure memory support from 3.0.35 kernel. 2. Pull in SECVIO support from 3.0.35 kernel. 3. Make changes to support device tree. 4. Add device tree setting for SECVIO sources. Signed-off-by: Dan Douglass <b41520@freescale.com>
* ENGR00289643-2 ASoC: fsl: Add missing spba clock for esai and spdifNicolin Chen2014-04-16
| | | | | | | | Both esai and spdif are using SDMA script to transmit and receive data while the essential spba clock is missed in the current two drivers. Thus add them. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00289643-1 arm: imx6sl: add missing spba clock to clock treeNicolin Chen2014-04-16
| | | | | | | | We are missing spba clock in imx6sl's clock tree, thus add it. Acked-by: Wang Shengjiu <b02247@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00289268 [iMX6x] Ensure there is no TLB miss when DDR is in self-refreshRanjani Vaidyanathan2014-04-16
| | | | | | | | | | During DDR frequency change code or in low power IDLE code (in iMX6SL), we need to ensure that all register addresses accessed in the IRAM code are in the TLB. There should be no TLB walks when DDR is in self-refresh. To ensure this flush the TLB before DDR frequency change and before low power IDLE (only iMX6SL) procedures. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00289278 dts: imx6qdl-sabreauto: fix usdhc1 pin conflict with gpmiDong Aisheng2014-04-16
| | | | | | | | | The SD1 on sabreauto baseboard is conflict with gpmi nand. The conflict pins are DAT4~DAT7. Since the SD3 on cpu board already supports 8 bit bus width, we do not want add an extra dts file for it, so we disable 8 bit and use 4 bit width for this issue. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00288578-6 ARM: imx: add mxs phy controller idPeter Chen2014-04-16
| | | | | | We use to use controller id to access different register regions Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00289037 dts: Remove hdcp ddc pin property in imx6qdl-sabresd.dtsiSandor Yu2014-04-16
| | | | | | | HDCP ddc pin property define in imx6q-sabresd-hdcp.dts, so remove the ddc pin preperty from imx6qdl-sabresd.dtsi. Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00264453 asoc: when codec probe failed, alsa return RETRY error.Shengjiu Wang2014-04-16
| | | | | | | | | | If there is no codec device, the machine driver will not register the card. then alsa will not return RETRY error. update the error handling for machine driver. Add for cs42888 and si476x. update dts file for sound-fm. Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* ENGR00288506 [iMX6SL] Improve Audio playback powerRanjani Vaidyanathan2014-04-16
| | | | | | | | | | | | | When ARM executes WFI in audio playback mode, its possible to lower the power consumed on the VDDHIGH_IN and VDDSOC_IN rails by: 1. Putting DDR into self-refresh 2. Lower DDR frequency to 25MHz 3. Float DDR IO pads. Also drop AHB to 8MHz in audio playback mode (aligning with 3.0.35) Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00288409 pcie: enable pcie pm when pcie is enabledRichard Zhu2014-04-16
| | | | | | | | | | | L2 can exit by 'reset' or Inband beacon (from remote EP) toggling phy_powerdown has same effect as 'inband beacon' So, toggle bit18 of GPR1, used as a workaround of errata "PCIe PCIe does not support L2 Power Down" WARNING: This is not official workaround for ERR005723. But we have not found issue yet. User should take own risk to use it. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00286487 pci: imx: eanble pcie msi supportRichard Zhu2014-04-16
| | | | | | | | | eanble pcie msi support on imx6 platforms * add check_device api in the msi chip. * add the quirks into pcie_port struct for the deviation from standard routines. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ARM: pci: add ->add_bus() and ->remove_bus() hooks to hw_pciThomas Petazzoni2014-04-16
| | | | | | | | | | | | | | | | | | | | | Some PCI drivers may need to adjust the pci_bus structure after it has been allocated by the Linux PCI core. The PCI core allows architectures to implement the pcibios_add_bus() and pcibios_remove_bus() for this purpose. This commit therefore extends the hw_pci and pci_sys_data structures of the ARM PCI core to allow PCI drivers to register ->add_bus() and ->remove_bus() in hw_pci, which will get called when a bus is added or removed from the system. This will be used for example by the Marvell PCIe driver to connect a particular PCI bus with its corresponding MSI chip to handle Message Signaled Interrupts. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Daniel Price <daniel.price@gmail.com> Tested-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: integrator: merge PCIv3 driver into one fileLinus Walleij2014-04-16
| | | | | | | | | | | | | | | | | | The Integrator/AP PCI bridget, "v3" is contained in two files, where pci.c is a socket container to plug in the v3 device. However to transition the v3 to enable device tree probing, it need to be converted to a platform device (so that it can have a device node in the device tree) and then we want the PCI driver in a single file, as any other device driver, so we can handle variants using compatible strings and device name, and get the base address etc from resources connected to the device node. To move toward this goal we consolidate all code in the pci_v3.c file. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* PCI: use weak functions for MSI arch-specific functionsThomas Petazzoni2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, the MSI architecture-specific functions could be overloaded using a fairly complex set of #define and compile-time conditionals. In order to prepare for the introduction of the msi_chip infrastructure, it is desirable to switch all those functions to use the 'weak' mechanism. This commit converts all the architectures that were overidding those MSI functions to use the new strategy. Note that we keep two separate, non-weak, functions default_teardown_msi_irqs() and default_restore_msi_irqs() for the default behavior of the arch_teardown_msi_irqs() and arch_restore_msi_irqs(), as the default behavior is needed by x86 PCI code. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Tested-by: Daniel Price <daniel.price@gmail.com> Tested-by: Thierry Reding <thierry.reding@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: linuxppc-dev@lists.ozlabs.org Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: linux390@de.ibm.com Cc: linux-s390@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: x86@kernel.org Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Luck <tony.luck@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: linux-ia64@vger.kernel.org Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: David S. Miller <davem@davemloft.net> Cc: sparclinux@vger.kernel.org Cc: Chris Metcalf <cmetcalf@tilera.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ENGR00288405: pcie: switch to upstreamed pcie driverRichard Zhu2014-04-16
| | | | | | | | | Based on community patch-set, re-setup pcie driver on imx6 platforms. * re-fine the pcie clks. * add the pcie support in dts files. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ARM: dts: imx6qdl: add pcie device nodeSean Cross2014-04-16
| | | | | | | | Add pcie device node for imx6qdl. Signed-off-by: Sean Cross <xobs@kosagi.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit 3a57291fa4ca7f7647d826f5b47082ef306d839f)
* ENGR00288568 Revert "ENGR00275213-1 arm: pcie: enable pcie on imx6 platforms"Richard Zhu2014-04-16
| | | | | | | | | | | | | switch to community upstreamed pcie driver. Revert "ENGR00275213-1 arm: pcie: enable pcie on imx6 platforms" This reverts commit d33370c77e57aed5a9b6733c9898418541fed54a. Conflicts: Documentation/devicetree/bindings/clock/imx6q-clock.txt arch/arm/mach-imx/clk-imx6q.c Signed-off-by: Richard Zhu <r65037@freescale.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-15 02:10:01 -0400