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* ENGR00304676-1 ARM: imx: gpc: update gpc driver for turning on PCIeRobin Gong2014-04-16
| | | | | | | | | | | For PCIe module on i.mx6sx, need send one power request to PCIe by GPC. So we need update gpc driver for the new requirement. We implement it by regulator notify framwork as pu power on/off in gpc driver. As PCIe use fs_initcall, we need make sure gpc driver ready before PCIe driver probe. Otherwise, cause system hang during PCIe driver probe, because the notify NOT installed ready and the gpc will NOT power on PCIe. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00304574-6 ARM: dts: imx6sx-17x17: add the gpmi DT nodeHuang Shijie2014-04-16
| | | | | | | Add the gpmi DT node. Since it has pin conflict with qspi, we disable it by default. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00304574-3 ARM: dts: imx6sx: add the DT node for gpmiHuang Shijie2014-04-16
| | | | | | Add the DT node for gpmi, including the pinctrl for gpmi. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00304574-1 ARM: dts: imx6sx: add dt node for apbh-dmaHuang Shijie2014-04-16
| | | | | | Add the dt node for apbh-dma. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00303542-4 mach:Update gpu clock to 720MLoren HUANG2014-04-16
| | | | | | | -Designed team confirmed GC400T is designed to run 720M. -Update the clock source for GC400T. Signed-off-by: Loren HUANG <b02279@freescale.com>
* ENGR00303542-3 dts:Add gpu description into imx6sx dtsiLoren HUANG2014-04-16
| | | | | | -Add gpu description into imx6sx dtsi to enable gc400t. Signed-off-by: Loren HUANG <b02279@freescale.com>
* ENGR00303542-2 Change pu dummy for i.mx6sxLoren HUANG2014-04-16
| | | | | | | -Change pu dummy for i.mx6sx to allow gpu power operation Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Loren Huang <b02279@freescale.com>
* ENGR00304563-2 ARM: dts: add fixed phy address to imx6sx 17x17/19x19 arm2 boardsFugang Duan2014-04-16
| | | | | | Add fixed phy-id property for imx6sx 17x17/19x19 arm2 boards. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00303778-2 ARM: dts: imx6sx-19x19-arm2: add pxp and v4l2 output supportRobby Cai2014-04-16
| | | | | | Enable pxp and v4l2 output driver on imx6sx 19x19 ARM2 board. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00303778-1 ARM: dts: imx6sx-sdb: add pxp v4l2 output support on SDBRobby Cai2014-04-16
| | | | | | Add pxp v4l2 output support Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00304229 ARM: IMX: Enhace the MAC address init function to support two MACsFugang Duan2014-04-16
| | | | | | | Since imx6sx has two ethernet MAC, and MAC address read from fuse. So enhance the MAC address init function to support two MACs. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00299939-2 ARM: imx6sl: Add dummy LDO2p5 regulator to support VBUS wakeupRanjani Vaidyanathan2014-04-16
| | | | | | | | | | | LDO2p5 cannot be disabled in low power idle mode when the USB driver enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy regulator that the USB driver will enable when VBUS wakeup is required. This patch ensures that the low power idle code checks the status of the dummy ldo2p5 regulator before disabling LDO2p5. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00299939-1 ARM: dts: imx6sl:Add dummy LDO2p5 regulator to support vbus ↵Ranjani Vaidyanathan2014-04-16
| | | | | | | | | | | wakeup LDO2p5 cannot be disabled in low power idle mode when the USB driver enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy regulator that the USB driver will enable when VBUS wakeup is required. This patch adds the dummy regulator to the dts files. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00303795-1 ARM: imx6sx: enable USB hsicPeter Chen2014-04-16
| | | | | | | | - Add USB hsic support for imx6sx - Enable hsic support at imx6sx 17x17 board - Enable usbotg1 and hsic support at imx6sx 19x19 board Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00304199 ARM: dtsi: add enet2 support for imx6sx arm2 platformsFugang Duan2014-04-16
| | | | | | | | | | | | | | | Add enet2 support for imx6sx 17x17/19x19 arm2 board. Since imx6sx has two enet interface, and all AR8031 ethernet daughter boards max7322 connect to same i2c bus, and same i2c slave address. Phy address also are the same in default. So need to change max7322 i2c slave address and phy address to others to avoid collision. Ar8031 ethernet daughter board rework: R9: switch to B, remove R22, install R21 with 10k. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00303791-1 ARM:imx6x: Add IRAM page table support for imx6sx.Ranjani Vaidyanathan2014-04-16
| | | | | | | | | | | | | Allocate page tables in IRAM that will be used when ever DDR is put into self-refresh. Add support for this to iMX6SX. Some common files are also changed to accomodate the OCRAM_S address that is used to store the IRAM page table in iMX6SX. This patch depends on the following two commits: ENGR297285-1 [MX6x] Support IRAM page table when DDR is in self-refresh. ENGR297285-2 [MX6x] Support IRAM page table when DDR is in self-refresh. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00297285-2 [MX6x] Support IRAM page table when DDR is in self-refresh.Ranjani Vaidyanathan2014-04-16
| | | | | | | | | | The bottom 16KB of the IRAM is reserved for the IRAM page table. Reduce the available IRAM size for the other drivers by 16KB. This commit is cherry-picked: d43a087f363b5dc91ddc4fc401540050d7f55c7f Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00297285-1 [MX6x] Support IRAM page table when DDR is in self-refreshRanjani Vaidyanathan2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Whenever DDR is explicitly put into self-refresh, we need to ensure that no access are made to the DDR. All the bus masters excpet ARM are shutdown gracefully. The ARM core can continue to access the DDR due to: 1. Speculative accesses This can be prevented by flushing the Branch Target Address Cache 2. Aggressive Prefetching This can be minimized by adding nops. Apart from this the TLB architecture in ARM does not guarantee that an entry remains in the TLB unless its explicitly locked. Even if free slots are available an entry maybe evicted. So flushing the TLB does not guarantee a page table walk will not happen. The solution is to put a minimized page table in IRAM that can be used when DDR is in self-refresh. The IRAM page tables should have entries for IRAM, AIPS1 and AIPS2 as these entries will be needed by the code that puts DDR into self-refresh. It should not contain any entries that point to the DDR. This patch set accomplishes the following: 1. Set the IRAM to be mapped as 1M sections in the high mem region. This makes it possible to create entries for the IRAM code in the IRAM page table. We need to ensure that both the DDR and IRAM page table have mapping for the IRAM code. 2. Ensure the IRAM, AIPS1, AIPS2 have entries in the IRAM page table. 3. Save TTBR1 4. Set TTBR1 to point to the page tables stored in IRAM. Switch to using TTBR1 before DDR is put into self-refresh. Ensure the following settings: a. TTBCR.N = 1 This means the 0-2G virtual address space is translated using TTBR0 and 2G-4G is translated using TTBR1. b. Set TTBCR.PD0 = 1 With this setting page table walks using TTBR0 are disabled. 4. After the DDR has exited self-refresh, reset TTBCR to 0 (TTBR0 will be used for translations now). 5. Restore TTBR1 Even though TTBR1 is only used to decode the top 2G of virtual address space, ARM requires that we allocate the entire 16KB for the page table. To minimize IRAM/OCRAM required, we put the code in the bottom 8K and page table entries in the top 8K. This requires the low power code be optimized to occupy as little space as possible. This commit is cherry-picked: 93ae491d9dbe34a91e2dd5832b02b0f0a390ddbe Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00303629-1: ARM: dts: imx6sx-sdb: support NOR Flash SF25FL128SAllen Xu2014-04-16
| | | | | | add Spansion SF25FL128S in sdb dts file. Signed-off-by: Allen Xu <b45815@freescale.com>
* ENGR00298127-2 ARM: dtsi: imx6qdl sabreauto: Disable mipi csiLiu Ying2014-04-16
| | | | | | | | | As the sabreauto CPU board schematics mentions, the MIPI connector isn't mechanically compatible with Freescale MIPI display and camera board, then we have no way to support MIPI features currently on this platform. So, let's disable MIPI CSI. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00298127-1 ARM: dtsi: imx6qdl sabreauto: Remove v4l2_cap_1 nodeLiu Ying2014-04-16
| | | | | | | | | As the sabreauto CPU board schematics mentions, the MIPI connector isn't mechanically compatible with Freescale MIPI display and camera board, then we have only the parallel CSI video input that is supported by the v4l2_cap_0 node. So, let's remove the orphan one - v4l2_cap_1. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00303300-2 arm: dts: Add MLB50 dts support on i.MX6SX-17x17-arm2 board.Luwei Zhou2014-04-16
| | | | | | | | Add MLB50 devicetree support on i.MX6SX-17x17-arm2 platform. Since the MLB50 has pin conflict with usdhc2 on i.MX6SX-17x17-arm2 board, add an extra dts file to enable mlb and disable usdhc2. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00302869-1 ARM: dts: imx6qdl: add cfg_clk for MIPI CSI2Robby Cai2014-04-16
| | | | | | | MIPI CSI2 depends on this clock to work. This patch also updates the binding document. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00302472-17 ARM: dts: imx6sx-19x19-arm2: Support Hannstar CABCLiu Ying2014-04-16
| | | | | | | | | This patch adds a device tree node for the Hannstar CABC function. We currently disable the CABC feature since it makes a panel's backlight unstable when display content varies considerably from time to time. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-15 ARM: dts: imx6sx-19x19-arm2: Support LVDS outputLiu Ying2014-04-16
| | | | | | | This patch adds the Hannstar XGA LVDS panel support on the imx6sx-19x19-arm2 board. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-14 ARM: dtsi: imx6sx: Add LDB DT nodeLiu Ying2014-04-16
| | | | | | | There is one LDB module embedded in the imx6sx SoC. This patch adds LDB devicetree node into imx6sx.dtsi. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-13 ARM: dts: imx6sx-19x19-arm2: Enable LCDIF1/2Liu Ying2014-04-16
| | | | | | | | This patch enables LCDIF1 and LCDIF2. LCDIF1 will drive the SEIKO parallel WVGA panel and LCDIF2 will drive LDB to support a 18bit LVDS panel. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-12 ARM: dts: imx6sx-19x19-arm2: Enable PWM3Liu Ying2014-04-16
| | | | | | | This patch enables PWM3 so that PWM backlight could be supported. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-8 ARM: dts: imx6qdl sabreauto: Remove LDB video mode stringLiu Ying2014-04-16
| | | | | | | This patch removes the video mode strings for framebuffers which are driven by LDB since they are specified in the lvds-channel DT node. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-7 ARM: dts: imx6qdl sabresd: Remove LDB video mode stringLiu Ying2014-04-16
| | | | | | | This patch removes the video mode strings for framebuffers which are driven by LDB since they are specified in the lvds-channel DT node. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-6 video: mxc: LDB driver refactorLiu Ying2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | This patch almost reworks the LDB driver to make the implementation simpler and clearer. The new version should support all the LDB modules embedded in imx53, imx6qdl and imx6sx. The lvds-channel subsidiary DT node is introduced to represent each LVDS channel. People may specify a channel's CRTC, working mode(dual mode or split mode), data width, data mapping, display timing and if it is a primary channel in the node. Change logs: * Use CTRC concept so that the driver may support both IPU and LCDIF as the display engines. * Add mxc dispdrv enable() callback. * Cache LDB ctrl register value at probe()/setup()/ enable() stages and finally write to the register at enable() stage. * Simplify logics for setting ctrl/bus muxing/clocks. * Use regmap to write crtl and bus muxing registers. * Remove LDB description in DT binding doc fsl_ipuv3_fb.txt. Instead, add a new one in fsl,ldb.txt. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00301078-2: ARM: dts: imx6sl-evk: add support for pfuze200 on imx6sl-evkRobin Gong2014-04-16
| | | | | | | | | | move pmic device node from imx6sl-evk.dtsi to upper-level, and add another layer on imx6sl-evk to diff pfuze100 or pfuze200. Meanwhile only works in ldo-enable mode if using pfuze200, since 'SW1C' switch regulator is cut for cost-down which means VDDARM_IN and VDDSOC_IN have to share the same switch regulator Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00301078-1: ARM: dts: imx6dl-sabresd: add support for pfuze200 on ↵Robin Gong2014-04-16
| | | | | | | | | | | | mx6dl-sabresd move pmic device node from imx6qdl-sabresd.dtsi to up-level, and add another layer on imx6dl-sabresd to diff pfuze100 or pfuze200. Meanwhile only work in ldo-enable mode if using pfuze200,since 'SW1C' switch regulator is cut for cost-down which means VDDARM_IN and VDDSOC_IN have to share the same switch regulator Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00303122-4 ARM: dtsi: Fix asrc clock providers for i.MX6 seriesNicolin Chen2014-04-16
| | | | | | Assign mem_clk, ipg_clk, and correct asrck_clk for i.MX6 series Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00303122-3 ARM: imx6sx: fix ASRC related clocks in the clock treeNicolin Chen2014-04-16
| | | | | | | | | | | | | | | | | | According to imx6sx RM, there are three clock providers for ASRC: Module clock Clock root Gate asrck_clock_d spdif0_clk_root N/A ipg_clk ahb_clk_root asrc_clk_enable mem_clk ahb_clk_root asrc_clk_enable while the current clock tree describes a clock named 'ASRC' that only describes the asrc_clk_enable function. Thus this patch first adds the other missing clocks to ASRC. [ Since we don't have the gate for asrck_clock_d, we can pass spdif0_clk to ASRC in the devicetree directly. ] Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00303122-2 ARM: imx6q: fix ASRC related clocks in the clock treeNicolin Chen2014-04-16
| | | | | | | | | | | | | | | | | | | | According to imx6q RM, there are three clock providers for ASRC: Module clock Clock root Gate asrck_clock_d spdif1_clk_root N/A ipg_clk ahb_clk_root asrc_clk_enable mem_clk ahb_clk_root asrc_clk_enable while the current clock tree describes a confusing clock named 'asrc' that combines this three clocks by rooting its rate from spdif1_clk_root but set its gate from ipg/mem_clk. Thus this patch first fixes the name asrc to the correct one -- spdif1 and adds the missing clocks to ASRC. [ Since we don't have the gate for asrck_clock_d, we can pass spdif0_clk to ASRC in the devicetree directly. ] Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00302235-3 pcie: enable pcie on imx6sx sdb boardRichard Zhu2014-04-16
| | | | | | enable pcie on imx6sx sdb board Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00302235-2 arm: enable pcie on imx6sxRichard Zhu2014-04-16
| | | | | | | | | - add mandatory pcie related clks in imx6sx clks tree - add pcie dts in imx6sx dts - add pcie kconfig option in imx6sx soc config - add pcie regulate into dts Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00302688-2 ARM:dts:imx6sx: Fixed code indentRanjani Vaidyanathan2014-04-16
| | | | | | Fixed code indent. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00302688-1 ARM:dts:imx6sx: Fixed build breakRanjani Vaidyanathan2014-04-16
| | | | | | Fixed dtb build break. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00301394 ARM:dts:imx6sx:Add support for imx6sx-19x19-arm2 board supportRanjani Vaidyanathan2014-04-16
| | | | | | Add dts files to support iMX6SX 19x19 ddr3 validation board. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00302299 ARM: dts: imx6sx: add adc support on i.MX6SX-17x17-ARM2 platformLuwei Zhou2014-04-16
| | | | | | add adc support for i.MX6SX-17x17-ARM2 platform. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00302353 ARM: dts: Add SSI<->WM8962 audio support for imx6sx-sdbNicolin Chen2014-04-16
| | | | | | | | Append audio nodes to the devicetree to add audio support for imx6sx-sdb with Wolfson WM8962 CODEC. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00302227-8 dts: imx6sx-sdb: add flexcan supportDong Aisheng2014-04-16
| | | | | | Add flexcan support Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00302227-7 dts: imx6sx-17x17-arm2: do not use sw polling for card detectDong Aisheng2014-04-16
| | | | | | | | | | | The SW polling for card detect will keep sending command repeatly at backgroud which will consume CPU MIPS and aslo affects the normal SD debug when enable CONFIG_MMC_DEBUG. Just as the board design, we simply treat it as no card detect support. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00302227-5 dts: imx6sx-sdb: add SD2 supportDong Aisheng2014-04-16
| | | | | | SD2 has no CD/WP pin and not power cycle and signal voltage switch capability. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00302227-4 dts: imx6sx-sdb: SD4 updateDong Aisheng2014-04-16
| | | | | | | Add CD/WP support and fix pinctrl setting that SD4 slot on SDB board is 4 bit, not 8 bit. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00302227-3 dts:imx6sx-sdb: add SD3 supportDong Aisheng2014-04-16
| | | | | | Add SD3 support Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00302227-2 dts: imx6sx-17x17-arm2: fix the pad setting of can gpiosDong Aisheng2014-04-16
| | | | | | | | | | | | | | We use the default GPIO pad ctrl setting for CAN before. However, we found the reset value of CAN gpio pad ctrl setting is 000030c1 which indicates the Drive Strength Field is HIZ. Thus there will be no output and GPIO output function will not work. Altough the board level pull up will make the CAN tranceiver work properly by default, however, we will not be able to shutdown the tranceiver by GPIO. Setting the correct driver strength for GPIO pad ctrl to make the pad out work properly. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00302227-1 dts:imx6sx-17x17-arm2: use external regulator for SDBDong Aisheng2014-04-16
| | | | | | | With using external regulator, we will be able to shutdown the power for the card during suspend. Signed-off-by: Dong Aisheng <b29396@freescale.com>
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