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* ENGR00280494-2 Add config for mfgtoolsFrank Li2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Build in USB Mass storage Enable CONFIG_FSL_UTP Must list all gadgets in config file otherwise CONFIG_USB_MASS_STORAGE becomes to m +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +CONFIG_USB_MASS_STORAGE=y +CONFIG_FSL_UTP=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set Signed-off-by: Frank Li <Frank.li@freescale.com>
* ENGR00281017 [MX6SL]Low power IDLE mode optimizationsRanjani Vaidyanathan2014-04-16
| | | | | | | | | | | | | | | | | Added a new bus freq mode - ultra_low_bus_freq_mode. In this mode the ARM is the only bus master that is active and the system is already in low power idle mode. And when ARM executes WFI in this mode, we do some aggressive power savings techinques like: 1. Drop DDR freq to 1MHz 2. Drop AHB freq to 3MHz 3. Float the DDR IO pads 4. If all PLLs are in bypass (which should be the case), do some analog power saving options like reducing the OSC-bias current, turning off the regular bandgap, disabling the regular 2P5, enabling the weak 2p5 etc. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00281804 ARM: imx6: init enet MAC addressFugang Duan2014-04-16
| | | | | | | | | | | | | | | Enet get MAC address order: From module parameters or kernel command line -> device tree -> pfuse -> mac registers set by bootloader -> random mac address. When there have no "fec.macaddr" parameters set in kernel command line, enet driver get MAC address from device tree. And then if the MAC address set in device tree and is valid, enet driver get MAC address from device tree. Otherwise,enet get MAC address from pfuse. So, in the condition, update the MAC address (read from pfuse) to device tree. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00281789-02 ARM: dts: imx6sl: correct the enet ipg clockFugang Duan2014-04-16
| | | | | | | Current imx6sl dts define enet_ref clock as ipg clock, which is not right. The ipg clock is "IMX6SL_CLK_ENET" defined at imx6sl-clock.h. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00281789-01 imx6sl: add missing enet clock for imx6slFugang Duan2014-04-16
| | | | | | There's a enet clock gate missing in clock tree, thus add it. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00280852-6 mxc: asrc: Use devtype instead of specific DT propertiesNicolin Chen2014-04-16
| | | | | | | We can determine the IP version from DT compatible name to decide which clock map and channel bits should be used. Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00280852-2 arm: dtsi: imx6qdl: Set sdma priority of ASRC to mediumNicolin Chen2014-04-16
| | | | | | Set the priority as what kernel 3.0.35 does to keep it safe. Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00280852-1 mxc: asrc: Add spba clock control for sdma shp scriptNicolin Chen2014-04-16
| | | | | | | | | | | ASRC is using shp_2_mcu and mcu_2_shp sdma scripts that use spba bus to transfer data, while the driver hasn't include the control code of spba clock. This would cause multiple pair conversion failed in most of time. Thus we need to add its support. Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00281613 imx_v7_defconfig: enable net VLAN 802.1QFugang Duan2014-04-16
| | | | | | Enable net VLAN 8021Q in imx_v7_defconfig. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00281446 ARM: dts: imx6: correct the power supply node name for epdcRobby Cai2014-04-16
| | | | | | | | The naming convention for power supply node in DTS is "%s-supply". With this patch regulator_get() will process in the DT way rather than traditional way. This patch has no functional impact. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00279946 dts: imx6qdl-sabreauto: add baseboard sd card slot supportDong Aisheng2014-04-16
| | | | | | | | NOTE since SD Card in main board takes a long route hence with Drive Speed High 80 OHMS causing error on high speed cards. Per suggestion DSE 40 OHMS is used. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00281036: [MX6SL]Align LPDDR2 freq change code to 8-byte boundaryRanjani Vaidyanathan2014-04-16
| | | | | | | | | | | This patch fixes 4 issues: 1. Add the .align 8 directive to the LPDDR2 freq change code, else the fncpy() function fails and the kernel does not boot. 2. Loads the correct L2_BASE_ADDR into register in lpddr2 freq change code 3. Fix the warning in clk_imx6sl.c 4. Change dev_WARN to dev_info in busfreq-imx6.c. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00280000 ARM: dts: imx6qdl-sabreauto: add dts files for ECSPI supportHuang Shijie2014-04-16
| | | | | | | The ecspi1 has pin conflict with the i2c3. This patch adds two dts files for the ECSPI support. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00280101-3 [iMX6x] Add support for bypass mode ratesRanjani Vaidyanathan2014-04-16
| | | | | | | Fix the code to report correct PFD and PLL clock rates when the PLL is in bypass state. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00280101-2 [iMX6SL/iMX6DL] Add busfreq supportRanjani Vaidyanathan2014-04-16
| | | | | | Change dtsi files to enable busfreq support. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00280101-1 [iMX6SL] Add busfreq supportRanjani Vaidyanathan2014-04-16
| | | | | | | Add support to scale the DDR frequency between 400MHz and 24MHz. Add support to scale AHB between 132MHz and 24MHz. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ARM: dts: imx6q: fix the wrong offset of the Pad Mux registerHuang Shijie2014-04-16
| | | | | | | | | | | The patch "0b7a76a ARM: dts: imx6q{dl}: add DTE pads for uart" adds the DTE pads for uart. For PAD_EIM_D29, the offset of the Pad Mux register should be 0x0c8, not 0x0c4. This patch fixes it. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: dts: enable the uart2 for imx6q-arm2Huang Shijie2014-04-16
| | | | | | | | enable the uart2 for imx6q-arm2 board. The uart2 works in the DTE mode, with the RTS/CTS and DMA enabled. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ENGR00279402-2 ARM: imx6q: imx6sl: System reset by checking the source settingRobin Gong2014-04-16
| | | | | | | Check the source setting in dts file to support different WDOG reset event. Correct imx6sl_restart instead of mxc_restart. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00279402-1 ARM: dts: imx6: add wdog reset source seclect in dtsRobin Gong2014-04-16
| | | | | | | | | | | | | | Some boards use another WDOG reset source to reboot system in ldo-bypass mode. We need add the property in board dts file so that we can easily know the WDOG reset source currently. For Sabresd, WDOG1 for ldo-enable mode(WDOG event), WDOG2 for ldo-bypass mode (reset external pmic to trigger POR event). For sl-evk board, there is no WDOG pin connected with external pmic as Sabresd , because mx6sl boot at 400Mhz. Then both ldo-enable and ldo-bypass mode use the common WDOG1 as reset source. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00279436 input: touchscreen: egalax: enable multitouchFugang Duan2014-04-16
| | | | | | | Disable single-touch support in imx_v7_defconfig to enable multitouch feature for egalax. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00279368-3 mxc: asrc: Add missing clock controlNicolin Chen2014-04-16
| | | | | | | | | * Add missing clock control * Set ASRC clock to 7.5MHz as 3.0.35 does * Use the same divisor for ideal ratio mode as 3.0.35 does Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00278941-3: arm: imx: add necessary flow for standby modeAnson Huang2014-04-16
| | | | | | | | Need to ensure that the ARM:IPG clock ratio is maintained at 12:5 when WFI is executed. This is the fix for the low power mode issue on i.MX6SL. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00278941-2: arm: imx: correct LDO bypass flow logicAnson Huang2014-04-16
| | | | | | | | The LDO analog bypass switch is necessary before entering DSM when LDO is working at digital bypass mode, previous coding logic is incorrect, fix it. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00278941-1: arm: imx: Fix suspend/resume unstable issueAnson Huang2014-04-16
| | | | | | | | | | As we need to float DDR IO when entering DSM, so those registers we need to access after DDR IO is floated must be contained in TLB, otherwise, the TLB update may case DDR access and lead to system hang. To make sure these registers' address is in TLB, we need to flush TLB first then access them manually. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00278667-3 [ARM]: imx_v7_defconfig enable adv7180 TV decoderOliver Brown2014-04-16
| | | | | | Enable the ADV7180 TV Decoder to imx_v7_defconfig Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00278667-2 [ARM]: dtsi: imx6qdl-sabreauto: add adv7180 driverOliver Brown2014-04-16
| | | | | | | | | Changes added to support adv7180 TV Decoder in the SabreAuto 3.10.9 Kernel device tree: -Added adv7180 support -Added reg_3p3v. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00278665-3 [ARM]: imx_v7_defconfig enable ov5640_mipi supportOliver Brown2014-04-16
| | | | | | Enable the ov5640 camera driver in the imx_v7_defconfig. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00278665-2 [ARM]: dtsi: imx6qdl-sabresd: add ov5640_mipi camera supportOliver Brown2014-04-16
| | | | | | Enabled ov5640_mipi in the SabreSD device tree. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00278646-10 ARM: dts: imx6qdl: add uhs pinctrl state for usdhc3Dong Aisheng2014-04-16
| | | | | | This is needed for supporting ultra high speed cards like SD3.0 cards. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00278646-5 ARM: dts: imx6qdl-sabresd: add no-1-8-v property for usdhcDong Aisheng2014-04-16
| | | | | | | The sabresd board does not have external 1.8v/3.3v signal voltage switch support for usdhc. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00279150 ARM: Kconfig: increase FORCE_MAX_ZONEORDER for ARCH_MXCJason Liu2014-04-16
| | | | | | | Need increase the FORCE_MAX_ZONEORDER to 14 for high resolution camera (GPU 2D user case). The default value 11(4MB) is not enough now. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00278666-3 [ARM]: Add ov5642 driver to imx_v7_defconfigOliver Brown2014-04-16
| | | | | | Enable the ov5640 camera driver in the imx_v7_defconfig. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00278666-2 ARM: dtsi: imx6qdl-sabresd: add ov564x camera supportOliver Brown2014-04-16
| | | | | | Enabled ov5642 in the SabreSD device tree. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00278920 [ARM] - dts update MIPI CSI2 node on SabreAutoOliver Brown2014-04-16
| | | | | | Correct the SabreAuto DTS. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00278663-4 [ARM]: imx_v7_defconfig add IPU v4l2Oliver Brown2014-04-16
| | | | | | Enable V4L2 capture driver in imx_v7_defconfig. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00278663-3 [ARM]: dts add IPU v4l2 capture driverOliver Brown2014-04-16
| | | | | | | Add V4L2 Capture support to device tree for SabreSD and SabreAuto Boards. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00278652-4 [ARM]: enable MIPI CSI2 in imx_v7_defconfigOliver Brown2014-04-16
| | | | | | Enable MIPI CSI2 as builtin in imx_v7_defconfig Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00278652-2 [ARM]: dts add MIPI CSI support for sabresd and sabreautoOliver Brown2014-04-16
| | | | | | Added MIPI CIS2 Device Tree support for SabreSD and SabreAuto. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00278683-1 [iMX6DLQ]: Add IOMUX configuration for IPU1 CSI0Oliver Brown2014-04-16
| | | | | | | | Add IOMUX configuration for IPU1 CSI0 for SabreSD and SabreAuto. This enables parallel CSI port required for OV564x on SabreSD and ADV7180 on SabreAuto. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00278822 ARM: imx_v7_defconfig: disable CONFIG_SWP_EMULATEShengjiu Wang2014-04-16
| | | | | | | | | | | | | | According to the help text in the config SWP_EMULATE in arch/arm/mm/Kconfig: "In some older versions of glibc [<=2.8] SWP is used during futex trylock() operations with the assumption that the code will not be preempted. This invalid assumption may be more likely to fail with SWP emulation enabled, leading to deadlock of the user application." The audio codec toolchain version is gcc-4.1.1-glibc-2.4, we need turn off the CONFIG_SWP_EMULATE in the imx_v7_defconfig. Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* ENGR00278672-3 ARM: imx_v7_defconfig: add the defconfig support for crypto/caamJason Liu2014-04-16
| | | | | | This patch add the defconfig support for crypto/caam Signed-off-by: Kudrick Jeffery <B37172@freescale.com>
* ENGR00278672-2 ARM: dts: add the imx6qdl.dtsi dts support for crypto/caamJason Liu2014-04-16
| | | | | | This patch add the imx6qdl.dtsi dts support for crypto/caam Signed-off-by: Kudrick Jeffery <B37172@freescale.com>
* ENGR00277382-2 [MX6SL] Add WaIT mode support for MX6SL.Ranjani Vaidyanathan2014-04-16
| | | | | | | | | | Enable WAIT mode support for MX6SL. Need to ensure that the ARM:IPG clock ratio is maintained at 12:5 when WFI is executed. This is the fix for the WAIT mode issue on MX6SL. Set AHB to 132Mhz at boot, which is the recommended freq for AHB. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00277382-1 [MX6SL] Ensure that PLL1 and PLL2 are always enabled.Ranjani Vaidyanathan2014-04-16
| | | | | | | | | | | Need to ensure that PLL1 and PLL2 have the enabled bit set even when the PLL is powered down and disabled. 1. Modifications to the ARM_PODF bits in the CCM require PLL1 to be enabled. 2. PLL2 will be set to bypass and enabled state (can be powered down) in low power IDLE mode. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00278432 [MX6x:Busfreq] Fix build warning.Ranjani Vaidyanathan2014-04-16
| | | | | | Fix build warning in arch/arm/mach-imx/busfreq_ddr3.c. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00269945: ARM: imx6: add the secondary sabreauto dts for pin conflictShawn Guo2014-04-16
| | | | | | | | | | | | The patch is to solve the pin conflicts between devices that are currently added in imx6qdl-sabreauto dts file. It has ecspi1, i2c3, and uart3 enabled while gpmi and weim disabled in the primary imx6qdl-sabreauto.dtsi, and creates the secondary imx6q/dl-sabreauto dts to have gpmi and weim enabled while others disabled. Since usbh1 and usbotg depend on GPIO from max7310 on i2c3, they have to be disabled as well in the secondary sabreauto dts files. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00269945: ARM: imx6: add sabresd hdcp dts filesShawn Guo2014-04-16
| | | | | | | | | | | It's basically a revert of commit fc52e42 (ENGR00269945: ARM: imx6: remove sabresd hdcp dts files). As we agree that maintaining multiple dts files for internal tree should not be a problem, let's add the hdcp dts files back as the solution to hdcp pin conflict. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00278489 imx: i.mx6d/q: disable the double linefill feature of PL310Jason Liu2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 But according to ARM PL310 errata: 752271 ID: 752271: Double linefill feature can cause data corruption Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 Workaround: The only workaround to this erratum is to disable the double linefill feature. This is the default behavior. without this patch, you will meet the following error when run the memtester application at: http://pyropus.ca/software/memtester/ FAILURE: 0x00100000 != 0x00200000 at offset 0x01365664. FAILURE: 0x00100000 != 0x00200000 at offset 0x01365668. FAILURE: 0x00100000 != 0x00200000 at offset 0x0136566c. FAILURE: 0x00100000 != 0x00200000 at offset 0x01365670. FAILURE: 0x00100000 != 0x00200000 at offset 0x01365674. FAILURE: 0x00100000 != 0x00200000 at offset 0x01365678. FAILURE: 0x00100000 != 0x00200000 at offset 0x0136567c. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00275034-5 ARM: imx_v7_defconfig: enable camera and v4l2 capture supportRobby Cai2014-04-16
| | | | | | | | | | Enable the following options on imx6sl CONFIG_VIDEO_V4L2_INT_DEVICE=y CONFIG_VIDEO_MXC_CAPTURE=y CONFIG_VIDEO_MXC_CSI_CAMERA=y CONFIG_MXC_CAMERA_OV5640=y Signed-off-by: Robby Cai <R63905@freescale.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 16:56:39 -0400