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* ENGR00320101 dts: imx6sx: Update the mma8451 device tree to add interrupt ↵luweizhou2014-06-26
| | | | | | | | | | mode option. The driver for android team need to enalbe mma8451 fifo overflow interrupt feather. So add the interrupt option into device tree. Signed-off-by: Luwei Zhou <b45643@freescale.com> (cherry picked from commit 443fd43f454215f615ee326ddb02911e05bcd2ae)
* Revert "ENGR00318063-5: ARM: imx: set CLK_SET_PARENT_GATE flag for glitchy ↵Shawn Guo2014-06-26
| | | | | | | | | | | | | | | | | mux clocks" This reverts commit cf56832a5ddf3a7caf3641bc272f59c7033f0b88. The change has a much bigger impact than we initially thought. It basically requires client drivers to check return of every single clk_set_parent() and clk_set_rate() call to know if they're doing something that clock driver prohibits for sake of glitch. The client drivers haven't been so ready for this change, so let's revert it from release branch and keep developing it on main branch for a while. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00320088 ARM: imx: disable Mega/Fast mix off featureAnson Huang2014-06-26
| | | | | | | As some modules in M/F domain are not ready for this feature, so need to disable it until every driver are ready for it. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00319792 ARM: imx: need to make sure MMDC auto self refresh is enabledAnson Huang2014-06-26
| | | | | | | | | | | When there is busfreq scaling between low power mode and audio bus mode, the enabling of MMDC auto self-refresh code will be skipped as they are both DLL off mode, it will cause DDR power increase, so we just move the enabling of the MMDC auto self-refresh mode to the end of busfreq change to make sure it is enabled after a DDR freq change. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00316496 ARM: imx: fix random failure for ddr3 freq scaling on i.mx6sxAnson Huang2014-06-26
| | | | | | | | | | | Improve DDR3 freq scaling procedure of i.MX6SX: 1. some code of condition check is incorrect; 2. better to keep MMDC command same as ddr script; 3. improve the clock tree change of mmdc path; 4. remove CON_REG req for MMDC. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00318063-8: ARM: imx6q: hide buggy ldb_di_sel from clk APIShawn Guo2014-06-25
| | | | | | | | | | | | | | | | | | | | | | | | The clk_set_parent() on the buggy mux ldb_di0_sel and ldb_di1_sel can possibly lock up the downstream divider and result in no clock output. Let's hard-code the parent to be pll2_pfd0_352m at boot time, and hide these two buggy muxes from clk API. Then no clk_set_parent() can be called on these muxes to switch parent clock at run-time. Kernel parameter 'ldb_di_clk_sel' is created to select parent of ldb_di_clk among the following clocks at boot time. 'pll5_video_div' 'pll2_pfd0_352m' 'pll2_pfd2_396m' 'mmdc_ch1_axi' 'pll3_usb_otg' Example format: ldb_di_clk_sel=pll5_video_div If the kernel parameter is absent or invalid, pll2_pfd0_352m will be selected by default. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-7: ARM: imx6q: mmdc_ch_axi clock should be non-gateableShawn Guo2014-06-25
| | | | | | | | | | | | | Per the updated CCM chapter, there is no gate for clock mmdc_ch1_axi. And there is a gate for mmdc_ch0_axi, but the gate also controls FABRIC clock, which means the gate cannot be gated anyway. That said, implementing these two clocks as gate does not make too much sense. Since the clocks are already referenced in quite some places, to minimize the impact of dropping the gate, instead of removing the clocks completely, we choose to point the clocks to their dividers. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag for PLL clocksShawn Guo2014-06-25
| | | | | | | | | | The i.MX6 Reference Manual requires PLLs to be powered down before changing its rate. Let's add flag CLK_SET_RATE_GATE for PLLs and audio/video dividers to enforce the check at clock core level. So any clk_set_rate() call from clients on these clocks will fail if the clocks are not disabled and unprepared. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-5: ARM: imx: set CLK_SET_PARENT_GATE flag for glitchy mux clocksShawn Guo2014-06-25
| | | | | | | | | | | | | | | | | | | The mux clocks found on imx6 SoCs are all glitchy ones except pll1_sw_clk_sel, axi_sel, periph_clk_sel and periph2_clk_sel. When switching parent clock of a glitchy mux without gating, a glitch could be generated and propagated into the downstream divider, and hence locks up the divider and results in no clock output. To avoid the situation, the parent switching should happen only when the clock is gated. Add CLK_SET_PARENT_GATE flag for i.MX mux clocks, so that clock core will make that check during clk_set_parent() call. Since glitchless clocks do not need this flag, we create imx_clk_mux_glitchless() without this flag for them. The periph_clk_sel and periph2_clk_sel are registered by imx_clk_busy_mux() which does not set this flag anyway, so they need no change. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-4: ARM: imx: drop flag CLK_SET_RATE_NO_REPARENT for ↵Shawn Guo2014-06-25
| | | | | | | | | | | | | | imx_clk_mux_flags All the users of function imx_clk_mux_flags() set CLK_SET_RATE_PARENT to request rate change propagatiopn up to parent. In this case, it should be good to clear flag CLK_SET_RATE_NO_REPARENT to let clk core find the best parent clock for the requested rate. Let's drop flag CLK_SET_RATE_NO_REPARENT for imx_clk_mux_flags(), so that function imx_clk_mux_flags_reparent() can just be saved. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-3: ARM: imx6sx: fix ocram_sels mux settingShawn Guo2014-06-25
| | | | | | | | | | | | | | | The current imx6sx clock driver combines two mux clocks ocram_alt_sel and ocram_sel into one, while ocram_alt_sel is a glitchy mux and ocram_sel is a glitchless one. Fix it to match the clock tree in Reference Manual. One thing clk API clients need to take care is that clk_set_parent() can be called on glitchy ocram_alt_sel only when ocram_sel selects the other path, i.e. periph. Otherwise, a glitch could be generated on ocram_alt_sel and get propagated into the divider ocram_podf. In that case, ocram_podf gets locked up and ocram clock has no output. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-2: ARM: imx6q: fix axi_sels mux settingShawn Guo2014-06-25
| | | | | | | | | | | | | | | | | | The current imx6q clock driver combines two mux clocks axi_alt_sel and axi_sel into one, while axi_alt_sel is a glitchy mux and axi_sel is a glitchless one. Fix it to match the clock tree in Reference Manual, and update busfreq driver regarding parent switching on that. Note, the parent checking before calling clk_set_parent() in busfreq driver isn't really necessary, because clk API will make the check and do nothing if the new parent is the same one as the old. One thing clk API clients need to take care is that clk_set_parent() can be called on glitchy axi_alt_sel only when axi_sel selects the other path, i.e. periph. Otherwise, a glitch could be generated on axi_alt_sel and get propagated into the divider axi_podf. In that case, axi_podf gets locked up and axi clock has no output. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-1: ARM: imx6sl: fix clock name in ocram_selsShawn Guo2014-06-25
| | | | | | | | The clock IMX6SL_CLK_OCRAM_ALT_SEL is registered with name "ocram_alt_sel", so the name in ocram_sels should be "ocram_alt_sel" than "ocram_alt_sels". Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00319936-2 dts: imx6sx: add usdhc into mege_fast wakeup sourceDong Aisheng2014-06-25
| | | | | | | The usdhc could also be wakeup source, thus add it into the mege_fast wakeup source list. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00319692 dts: imx6qdl-sabresd: make emmc on usdhc4 fixed to mmc0Dong Aisheng2014-06-24
| | | | | | | | | | | The mmc core will reserve the mmc index for the specific controller by add mmc alias in device tree. There's an eMMC chip on sabresd board on uSDHC slot 4. We want it be fixed to mmc0 to be used for finding rootfs persistently. So adding Alias mmc0 to usdhc4 in device tree. Signed-off-by: Dong Aisheng <b29396@freescale.com> (cherry picked from commit 4cd99820322abca9c9d2b82ee2513aa9d096c02b)
* ENGR00319480 ARM: dts: imx6sx: add enet as mege_fast wakeup sourceFugang Duan2014-06-20
| | | | | | | | For imx6sx 17x17/19x19 arm2 board, add enet as mege_fast wakeup source. For imx6sx sdb board, it don't support wake on lan, so it cannot support enet as mega_fast wake up source. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00319455-4 imx_v7_defconfig: enable canfd by defaultDong Aisheng2014-06-20
| | | | | | | | enable canfd by default. The defconfig is generated by make ARCH=arm savedefconfig which got the uneeded CONFIG_USB_PHY removed. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00319455-3 dts: imx6sx-sdb: add canfd supportDong Aisheng2014-06-20
| | | | | | Introduce a new dtb imx6sx-sdb-canfd.dtb due to pin conflict with flexcan. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00319455-2 imx6sx: enable can transceiver by default for canfdDong Aisheng2014-06-20
| | | | | | | | Switch on the transceiver by default for board with canfd enabled since canfd driver does not handle it. Two CAN instances share the same switch. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00318773-11 ARM: imx6qdl: Remove incorrect clock sourcesNicolin Chen2014-06-19
| | | | | | | | | The clock sources from ASRC, ESAI and MLB are not actually from CCM but outside PAD inputs. So we these clock sources over here are totally wrong and should be fixed. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00318259-2 ARM: imx: support mega fast domain power off in DSMAnson Huang2014-06-17
| | | | | | | | | | Add mega fast domain power off feature in DSM, it can save about 0.72mW power; If there is any module in Mega/Fast domain enabled as wakeup source, then Mega/Fast domain's power will be kept on in DSM. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00318259-1 ARM: dts: imx6sx: add mege_fast wakeup source infoAnson Huang2014-06-17
| | | | | | | | Add Mega/Fast domain's wakeup source info for kernel, if there is wakeup source in Mega/Fast domain enabled, then this domain's power can NOT be disabled in DSM. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00318392 ARM:imx6x: Save/restore SCU and some CP15 registers across ↵Ranjani Vaidyanathan2014-06-13
| | | | | | | | | | | | | | | suspend/resume This patch ensures that the SCU and certain A9 CP15 registers state are maintained across a suspend/resume cycle: 1. Need to ensure that SCU standby bit is set again after suspend/resume cycle, else the system will never WAIT mode after a suspend/resume cycle. This bit should be enabled on all SMP systems immaterial of whether CPUIDLE is enabled or not. 2. Several A9 errata workarounds involve setting bits in the ARM diagnostic register. Save/restore this register across a suspend/resume cycle. 3. Save and restore the A9 power control register also. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00318207 ARM:imx6x:Busfreq:Fix build warnings in busfreq driver.Ranjani Vaidyanathan2014-06-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following build warnings in busfreq driver: /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq-imx6.c: In function 'imx6_dt_find_ddr_sram': /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq-imx6.c:736:29: warning: assignment makes integer from pointer without a cast [enabled by default] ddr_freq_change_iram_phys = (void *)ddr_iram_addr; ^ CC drivers/base/firmware_class.o /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c: In function 'init_mmdc_ddr3_settings_imx6sx': /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c:404:22: warning: assignment makes pointer from integer without a cast [enabled by default] iram_iomux_settings = ddr_freq_change_iram_base + ddr_code_size; ^ /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c: In function 'init_mmdc_ddr3_settings_imx6q': /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c:539:22: warning: assignment makes pointer from integer without a cast [enabled by default] iram_iomux_settings = ddr_freq_change_iram_base + ddr_code_size; ^ CC arch/arm/mach-imx/busfreq_lpddr2.o /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c: In function 'init_mmdc_lpddr2_settings': /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c:96:2: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement] unsigned long ddr_code_size; ^ /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c:101:3: warning: passing argument 1 of 'memcpy' makes pointer from integer without a cast [enabled by default] mx6_change_lpddr2_freq = (void *)fncpy( Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00317542-2 ARM:dts:imx6x: Allocate 4K of IRAM for DDR freq change code.Ranjani Vaidyanathan2014-06-12
| | | | | | | Allocate 4K of IRAM space for DDR freq change code in the dts files. Also reduce the regular IRAM available for other functions by this amount. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00317542-1 ARM:imx6x: Dynamically calculate the size of low power mode code.Ranjani Vaidyanathan2014-06-12
| | | | | | | | | | | | | This patch adds support for dynamically calculating the size of all low power code (suspend, ddr freq change and low power idle). This allows for easy code changes in the future. This patch also moves the DDR frequency change code from lower 8K of the memory allocated for IRAM page table to regular IRAM. With this the lower 8K of the IRAM page table only contains suspend/resume and low power IDLE code. This gives a little more flexibility to the cdoe size for suspend/resume and low power IDLE. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00317861 ARM: imx: add cpufreq support when VPU running at 352MHzAnson Huang2014-06-11
| | | | | | | | | When VPU 352MHz is supported, PLL2_PFD2 will run at 352MHz instead of 396MHz, CPUFreq driver will use PLL2_PFD2 when it is running at 396MHz setpoint, so when VPU 352MHz is enabled, CPUFreq can be enabled but need to remove the 396MHz setpoint. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00315400 ARM: imx: add lpddr2 busfreq support for i.mx6sxAnson Huang2014-06-04
| | | | | | | | | | Add freq scaling for lpddr2 of i.MX6SX, support 3 setpoints: high -> 400MHz audio -> 100MHz low -> 24MHz Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00314570-1 arm: add pcie power control on imx6sxRichard Zhu2014-05-26
| | | | | | | imx6sx pcie has standalone ldo domain, add the power control routines on the ldo regulator call back. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00314571 pcie: resolve one compile warning on pcie pmRichard Zhu2014-05-26
| | | | | | resolve one compile warning on pcie pm Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00309838 ARM: imx6sl: gpc: add chip revision check for dispmixRobby Cai2014-05-23
| | | | | | | The dispmix feature works without problem since TO1.2. This patch adds the back-compatibility for older chip. Signed-off-by: Robby Cai <r63905@freescale.com>
* ENGR00313889 ARM DTS: Enable v4l2 capture function for imx6sx lcdif1 dtsSandor Yu2014-05-18
| | | | | | | | | LCDIF1 pin conflict with camera, ov5640 driver is disabled in imx6sx 19x19 arm2 lcdif1 dts file, v4l2 capture function shouldn't disabled in the dts, remove the disable code. Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00309881 ARM:imx6: Disable L1 and L2 when DDR is in self-refresh.Ranjani Vaidyanathan2014-05-16
| | | | | | | | | When switching to page tables in IRAM, we are switching from a cacheable to non-cacheable page table. Based on recommendation from ARM, we need to ensure that branch prediction, L1 data nd L2 are disabled when DDR is put into self-refresh. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00313685-15 ARM: dts: imx: apply ENET IRQ workaround for sabresd boardShawn Guo2014-05-16
| | | | | | | | | | | | | | | This is pretty much an example to demonstrate how the GPIO6 workaround for bug ERR006687 (ENET: Only the ENET wake-up interrupt request can wake the system from Wait mode) should be applied for a board. Basically it requires a setup of MX6QDL_PAD_GPIO_6__ENET_IRQ in pinctrl entry, and an overwrite on the property interrupts-extended to replace the ENET GIC IRQ with GPIO1_6. Since the pad GPIO6 is used by I2C3 on the board, we have to create sabresd-enetirq.dts with I2C3 disabled to enable this workaround. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00313685-13 ARM: dts: imx6qdl: use interrupts-extended for fecTroy Kisky2014-05-16
| | | | | | | | | | | | | | | | commit 454cf8f54d9918c8017f2eee7fb0138927ef2afd upstream. We need to be able to override interrupts in board file to workaround a hardware bug for ethernet interrupts waking the processor by using interrupts-extended. So, use interrupts-extended here as well. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/boot/dts/imx6qdl.dtsi
* ENGR00313685-12 ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQTroy Kisky2014-05-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit d8c765e0d1ddbd5032c2491c82cc9660c2f0e7f2 upstream. From "Chip Errata for the i.MX 6Dual/6Quad" ERR006687 ENET: Only the ENET wake-up interrupt request can wake the system from Wait mode. The ENET block generates many interrupts. Only one of these interrupt lines is connected to the General Power Controller (GPC) block, but a logical OR of all of the ENET interrupts is connected to the General Interrupt Controller (GIC). When the system enters Wait mode, a normal RX Done or TX Done does not wake up the system because the GPC cannot see this interrupt. This impacts performance of the ENET block because its interrupts are serviced only when the chip exits Wait mode due to an interrupt from some other wake-up source. Adding MX6QDL_PAD_GPIO_6__ENET_IRQ is the 1st step to workaround this problem. The input reg is set to 0x3c to set IOMUX_OBSRV_MUX1 to ENET_IRQ. The mux reg value is 0x11, so that the observable mux is routed to this pin and to the gpio controller(sion bit). These magic values come from Ranjani Vaidyanathan's patch: "ENGR00257847-1 MX6Q/DL-Fix Ethernet performance issue when WAIT mode is active" Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> CC: Ranjani Vaidyanathan <ra5478@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00313685-10 of/irq: Fix bug in interrupt parsing refactor.Grant Likely2014-05-16
| | | | | | | | | | | | | | | | commit 78119fd1068cc068f6112a57a5f6de0e5b20245a upstream. Commit 2361613206e6, "of/irq: Refactor interrupt-map parsing" introduced a bug. The irq parsing will fail for some nodes that don't have a reg property. It is fixed by deferring the check for reg until it is actually needed. Also adjust the testcase data to catch the bug. Signed-off-by: Grant Likely <grant.likely@linaro.org> Tested-by: Stephen Warren <swarren@nvidia.com> Tested-by: Ming Lei <tom.leiming@gmail.com> Tested-by: Stephen Warren <swarren@nvidia.com> Cc: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00313685-9 of/irq: create interrupts-extended propertyGrant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | | | commit 79d9701559a9f3e9b2021fbd292f5e70ad75f686 upstream. The standard interrupts property in device tree can only handle interrupts coming from a single interrupt parent. If a device is wired to multiple interrupt controllers, then it needs to be attached to a node with an interrupt-map property to demux the interrupt specifiers which is confusing. It would be a lot easier if there was a form of the interrupts property that allows for a separate interrupt phandle for each interrupt specifier. This patch does exactly that by creating a new interrupts-extended property which reuses the phandle+arguments pattern used by GPIOs and other core bindings. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Kumar Gala <galak@codeaurora.org> [grant.likely: removed versatile platform hunks into separate patch] Cc: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00313685-8 microblaze/pci: Drop PowerPC-ism from irq parsingGrant Likely2014-05-16
| | | | | | | | | | | | | commit f27446c3ad5b6d3b5b28ec0176e23d3ceca595d8 upstream. The Microblaze PCI code copied the PowerPC irq handling, but powerpc needs to handle broken device trees that are not present on Microblaze. This patch removes the powerpc special case and replaces it with a direct of_irq_parse_and_map_pci() call. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00313685-7 of/irq: Create of_irq_parse_and_map_pci() to consolidate arch ↵Grant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | code. commit 16b84e5a505c790538e534ad8dfda9c288691e40 upstream. Several architectures open code effectively the same code block for finding and mapping PCI irqs. This patch consolidates it down to a single function. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/mach-integrator/pci_v3.c arch/mips/pci/pci-rt3883.c
* ENGR00313685-6 of: Add testcases for interrupt parsingGrant Likely2014-05-16
| | | | | | | | | | commit a9f10ca76d784023fc45f01f025b54e9960f4ec1 upstream. This patch extends the DT selftest code with some test cases for the interrupt parsing functions. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00313685-4 of/irq: Refactor interrupt-map parsingGrant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 2361613206e66ce59cc0e08efa8d98ec15b84ed1 upstream. All the users of of_irq_parse_raw pass in a raw interrupt specifier from the device tree and expect it to be returned (possibly modified) in an of_phandle_args structure. However, the primary function of of_irq_parse_raw() is to check for translations due to the presence of one or more interrupt-map properties. The actual placing of the data into an of_phandle_args structure is trivial. If it is refactored to accept an of_phandle_args structure directly, then it becomes possible to consume of_phandle_args from other sources. This is important for an upcoming patch that allows a device to be connected to more than one interrupt parent. It also simplifies the code a bit. The biggest complication with this patch is that the old version works on the interrupt specifiers in __be32 form, but the of_phandle_args structure is intended to carry it in the cpu-native version. A bit of churn was required to make this work. In the end it results in tighter code, so the churn is worth it. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: drivers/of/irq.c
* ENGR00313685-3 of/irq: simplify args to irq_create_of_mappingGrant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | | | commit e6d30ab1e7d1281784672c0fc2ffa385cfb7279e upstream. All the callers of irq_create_of_mapping() pass the contents of a struct of_phandle_args structure to the function. Since all the callers already have an of_phandle_args pointer, why not pass it directly to irq_create_of_mapping()? Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/mach-integrator/pci_v3.c arch/mips/pci/pci-rt3883.c kernel/irq/irqdomain.c
* ENGR00313685-2 of/irq: Replace of_irq with of_phandle_argsGrant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | commit 530210c7814e83564c7ca7bca8192515042c0b63 upstream. struct of_irq and struct of_phandle_args are exactly the same structure. This patch makes the kernel use of_phandle_args everywhere. This in itself isn't a big deal, but it makes some follow-on patches simpler. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/mach-integrator/pci_v3.c arch/mips/pci/pci-rt3883.c include/linux/of_irq.h
* ENGR00313685-1 of/irq: Rename of_irq_map_* functions to of_irq_parse_*Grant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 0c02c8007ea5554d028f99fd3e29fc201fdeeab3 upstream. The OF irq handling code has been overloading the term 'map' to refer to both parsing the data in the device tree and mapping it to the internal linux irq system. This is probably because the device tree does have the concept of an 'interrupt-map' function for translating interrupt references from one node to another, but 'map' is still confusing when the primary purpose of some of the functions are to parse the DT data. This patch renames all the of_irq_map_* functions to of_irq_parse_* which makes it clear that there is a difference between the parsing phase and the mapping phase. Kernel code can make use of just the parsing or just the mapping support as needed by the subsystem. The patch was generated mechanically with a handful of sed commands. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/mach-integrator/pci_v3.c arch/mips/pci/pci-rt3883.c drivers/of/irq.c
* ENGR00313508-03 ARM: dts: imx6sx: add enet magic pattern supportFugang Duan2014-05-15
| | | | | | Add enet magic pattern support for imx6sx arm2 platforms. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00313508-01 ARM: imx6sx: add enet sleep mode supportFugang Duan2014-05-15
| | | | | | Add enet sleep mode support for imx6sx arm2 platforms. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00313202 ARM: imx: add VPU 352M support for i.MX6QAnson Huang2014-05-13
| | | | | | | | | | | | | | | | | | When VPU freq is set to 352MHz, it need to source clk from PLL2_PFD2_396M, and PLL2_PFD2_396M need to change freq to 352M. VDDSOC/PU needs to be at highest setpoint when VPU@352Mhz, cpufreq will be disabled as it will not save any power if VDDSOC/PU's voltage stays at highest setpoint. Busfreq will be disabled as it needs PLL2_PFD2 to be as 396MHz to achieve low power audio freq setpoint. To enable VPU 352MHz feature, select it in menuconfig, it is disabled by default. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00312939 ARM:imx6x: Ensure that the suspend/resume code saves the registers.Ranjani Vaidyanathan2014-05-13
| | | | | | | | | The suspend/resume code needs to save the ARM registers that is used in the code. The return paths from the suspend code can be different, based on if an interrupt is pending. So we cannot depend on the kernel code to restore the registers. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00313280-2 ASoC: fsl: Merge upsteamed cs42xx8 driver.Shengjiu Wang2014-05-13
| | | | | | | | | | | | | | | | | | The upsteamed commit is 0c516b4ff85c0be4cee5b30ae59c9565c7f91a00 ASoC: cs42xx8: Add codec driver support for CS42448/CS42888 This patch adds support for the Cirrus Logic CS42448/CS42888 Audio CODEC that has six/four 24-bit AD and eight 24-bit DA converters. [ CS42448/CS42888 supports both I2C and SPI control ports. As initial patch, this patch only adds the support for I2C. ] Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Acked-by: Brian Austin <brian.austin@cirrus.com> Acked-by: Paul Handrigan <Paul.Handrigan@cirrus.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Shengjiu Wang <b02247@freescale.com>
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