| Commit message (Collapse) | Author | Age |
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The clk_set_parent() on the buggy mux ldb_di0_sel and ldb_di1_sel can
possibly lock up the downstream divider and result in no clock output.
Let's hard-code the parent to be pll2_pfd0_352m at boot time, and hide
these two buggy muxes from clk API. Then no clk_set_parent() can be
called on these muxes to switch parent clock at run-time.
Kernel parameter 'ldb_di_clk_sel' is created to select parent of
ldb_di_clk among the following clocks at boot time.
'pll5_video_div'
'pll2_pfd0_352m'
'pll2_pfd2_396m'
'mmdc_ch1_axi'
'pll3_usb_otg'
Example format: ldb_di_clk_sel=pll5_video_div
If the kernel parameter is absent or invalid, pll2_pfd0_352m will be
selected by default.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Per the updated CCM chapter, there is no gate for clock mmdc_ch1_axi.
And there is a gate for mmdc_ch0_axi, but the gate also controls FABRIC
clock, which means the gate cannot be gated anyway. That said,
implementing these two clocks as gate does not make too much sense.
Since the clocks are already referenced in quite some places, to
minimize the impact of dropping the gate, instead of removing the clocks
completely, we choose to point the clocks to their dividers.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The i.MX6 Reference Manual requires PLLs to be powered down before
changing its rate. Let's add flag CLK_SET_RATE_GATE for PLLs and
audio/video dividers to enforce the check at clock core level. So any
clk_set_rate() call from clients on these clocks will fail if the clocks
are not disabled and unprepared.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The mux clocks found on imx6 SoCs are all glitchy ones except
pll1_sw_clk_sel, axi_sel, periph_clk_sel and periph2_clk_sel. When
switching parent clock of a glitchy mux without gating, a glitch could
be generated and propagated into the downstream divider, and hence locks
up the divider and results in no clock output.
To avoid the situation, the parent switching should happen only when
the clock is gated. Add CLK_SET_PARENT_GATE flag for i.MX mux clocks,
so that clock core will make that check during clk_set_parent() call.
Since glitchless clocks do not need this flag, we create
imx_clk_mux_glitchless() without this flag for them. The periph_clk_sel
and periph2_clk_sel are registered by imx_clk_busy_mux() which does not
set this flag anyway, so they need no change.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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imx_clk_mux_flags
All the users of function imx_clk_mux_flags() set CLK_SET_RATE_PARENT
to request rate change propagatiopn up to parent. In this case, it
should be good to clear flag CLK_SET_RATE_NO_REPARENT to let clk core
find the best parent clock for the requested rate.
Let's drop flag CLK_SET_RATE_NO_REPARENT for imx_clk_mux_flags(), so
that function imx_clk_mux_flags_reparent() can just be saved.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The current imx6sx clock driver combines two mux clocks ocram_alt_sel
and ocram_sel into one, while ocram_alt_sel is a glitchy mux and
ocram_sel is a glitchless one. Fix it to match the clock tree in
Reference Manual.
One thing clk API clients need to take care is that clk_set_parent()
can be called on glitchy ocram_alt_sel only when ocram_sel selects the
other path, i.e. periph. Otherwise, a glitch could be generated on
ocram_alt_sel and get propagated into the divider ocram_podf. In that
case, ocram_podf gets locked up and ocram clock has no output.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The current imx6q clock driver combines two mux clocks axi_alt_sel and
axi_sel into one, while axi_alt_sel is a glitchy mux and axi_sel is a
glitchless one. Fix it to match the clock tree in Reference Manual,
and update busfreq driver regarding parent switching on that. Note,
the parent checking before calling clk_set_parent() in busfreq driver
isn't really necessary, because clk API will make the check and do
nothing if the new parent is the same one as the old.
One thing clk API clients need to take care is that clk_set_parent()
can be called on glitchy axi_alt_sel only when axi_sel selects the other
path, i.e. periph. Otherwise, a glitch could be generated on
axi_alt_sel and get propagated into the divider axi_podf. In that case,
axi_podf gets locked up and axi clock has no output.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The clock IMX6SL_CLK_OCRAM_ALT_SEL is registered with name
"ocram_alt_sel", so the name in ocram_sels should be "ocram_alt_sel"
than "ocram_alt_sels".
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The usdhc could also be wakeup source, thus add it into the mege_fast
wakeup source list.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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The mmc core will reserve the mmc index for the specific controller
by add mmc alias in device tree.
There's an eMMC chip on sabresd board on uSDHC slot 4.
We want it be fixed to mmc0 to be used for finding rootfs persistently.
So adding Alias mmc0 to usdhc4 in device tree.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit 4cd99820322abca9c9d2b82ee2513aa9d096c02b)
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For imx6sx 17x17/19x19 arm2 board, add enet as mege_fast wakeup source.
For imx6sx sdb board, it don't support wake on lan, so it cannot support
enet as mega_fast wake up source.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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enable canfd by default.
The defconfig is generated by make ARCH=arm savedefconfig
which got the uneeded CONFIG_USB_PHY removed.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Introduce a new dtb imx6sx-sdb-canfd.dtb due to pin conflict with flexcan.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Switch on the transceiver by default for board with canfd enabled
since canfd driver does not handle it.
Two CAN instances share the same switch.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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The clock sources from ASRC, ESAI and MLB are not actually from CCM but
outside PAD inputs. So we these clock sources over here are totally wrong
and should be fixed.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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Add mega fast domain power off feature in DSM, it can save about
0.72mW power;
If there is any module in Mega/Fast domain enabled as wakeup source,
then Mega/Fast domain's power will be kept on in DSM.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add Mega/Fast domain's wakeup source info for kernel, if there
is wakeup source in Mega/Fast domain enabled, then this domain's
power can NOT be disabled in DSM.
Signed-off-by: Anson Huang <b20788@freescale.com>
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suspend/resume
This patch ensures that the SCU and certain A9 CP15 registers state are maintained across
a suspend/resume cycle:
1. Need to ensure that SCU standby bit is set again after suspend/resume cycle, else
the system will never WAIT mode after a suspend/resume cycle. This bit should be enabled
on all SMP systems immaterial of whether CPUIDLE is enabled or not.
2. Several A9 errata workarounds involve setting bits in the ARM diagnostic register.
Save/restore this register across a suspend/resume cycle.
3. Save and restore the A9 power control register also.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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Fix the following build warnings in busfreq driver:
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq-imx6.c: In function 'imx6_dt_find_ddr_sram':
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq-imx6.c:736:29: warning: assignment makes integer from pointer
without a cast [enabled by default]
ddr_freq_change_iram_phys = (void *)ddr_iram_addr;
^
CC drivers/base/firmware_class.o
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c: In function 'init_mmdc_ddr3_settings_imx6sx':
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c:404:22: warning: assignment makes pointer from integer
without a cast [enabled by default]
iram_iomux_settings = ddr_freq_change_iram_base + ddr_code_size;
^
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c: In function 'init_mmdc_ddr3_settings_imx6q':
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c:539:22: warning: assignment makes pointer from integer
without a cast [enabled by default]
iram_iomux_settings = ddr_freq_change_iram_base + ddr_code_size;
^
CC arch/arm/mach-imx/busfreq_lpddr2.o
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c: In function 'init_mmdc_lpddr2_settings':
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c:96:2: warning: ISO C90 forbids mixed declarations and
code [-Wdeclaration-after-statement]
unsigned long ddr_code_size;
^
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c:101:3: warning: passing argument 1 of 'memcpy' makes
pointer from integer without a cast [enabled by default]
mx6_change_lpddr2_freq = (void *)fncpy(
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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Allocate 4K of IRAM space for DDR freq change code in the dts files.
Also reduce the regular IRAM available for other functions by this amount.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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This patch adds support for dynamically calculating the size of all
low power code (suspend, ddr freq change and low power idle). This allows
for easy code changes in the future.
This patch also moves the DDR frequency change code from lower 8K of the memory
allocated for IRAM page table to regular IRAM. With this the lower 8K of the
IRAM page table only contains suspend/resume and low power IDLE code. This
gives a little more flexibility to the cdoe size for suspend/resume and low
power IDLE.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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When VPU 352MHz is supported, PLL2_PFD2 will run at 352MHz instead of
396MHz, CPUFreq driver will use PLL2_PFD2 when it is running at 396MHz
setpoint, so when VPU 352MHz is enabled, CPUFreq can be enabled but
need to remove the 396MHz setpoint.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add freq scaling for lpddr2 of i.MX6SX, support 3 setpoints:
high -> 400MHz
audio -> 100MHz
low -> 24MHz
Signed-off-by: Anson Huang <b20788@freescale.com>
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imx6sx pcie has standalone ldo domain, add the power
control routines on the ldo regulator call back.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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resolve one compile warning on pcie pm
Signed-off-by: Richard Zhu <r65037@freescale.com>
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The dispmix feature works without problem since TO1.2.
This patch adds the back-compatibility for older chip.
Signed-off-by: Robby Cai <r63905@freescale.com>
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LCDIF1 pin conflict with camera, ov5640 driver is disabled in
imx6sx 19x19 arm2 lcdif1 dts file,
v4l2 capture function shouldn't disabled in the dts,
remove the disable code.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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When switching to page tables in IRAM, we are switching from a cacheable
to non-cacheable page table. Based on recommendation from ARM, we need to
ensure that branch prediction, L1 data nd L2 are disabled when DDR is put
into self-refresh.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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This is pretty much an example to demonstrate how the GPIO6 workaround
for bug ERR006687 (ENET: Only the ENET wake-up interrupt request can
wake the system from Wait mode) should be applied for a board.
Basically it requires a setup of MX6QDL_PAD_GPIO_6__ENET_IRQ in pinctrl
entry, and an overwrite on the property interrupts-extended to replace
the ENET GIC IRQ with GPIO1_6.
Since the pad GPIO6 is used by I2C3 on the board, we have to create
sabresd-enetirq.dts with I2C3 disabled to enable this workaround.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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commit 454cf8f54d9918c8017f2eee7fb0138927ef2afd upstream.
We need to be able to override interrupts in board file to
workaround a hardware bug for ethernet interrupts
waking the processor by using interrupts-extended.
So, use interrupts-extended here as well.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Conflicts:
arch/arm/boot/dts/imx6qdl.dtsi
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commit d8c765e0d1ddbd5032c2491c82cc9660c2f0e7f2 upstream.
From "Chip Errata for the i.MX 6Dual/6Quad"
ERR006687 ENET: Only the ENET wake-up interrupt request can wake the
system from Wait mode.
The ENET block generates many interrupts. Only one of these interrupt lines
is connected to the General Power Controller (GPC) block, but a logical OR
of all of the ENET interrupts is connected to the General Interrupt Controller
(GIC). When the system enters Wait mode, a normal RX Done or TX Done does not
wake up the system because the GPC cannot see this interrupt. This impacts
performance of the ENET block because its interrupts are serviced only when
the chip exits Wait mode due to an interrupt from some other wake-up source.
Adding MX6QDL_PAD_GPIO_6__ENET_IRQ is the 1st step to
workaround this problem.
The input reg is set to 0x3c to set IOMUX_OBSRV_MUX1 to ENET_IRQ.
The mux reg value is 0x11, so that the observable mux is routed to
this pin and to the gpio controller(sion bit). These magic values
come from Ranjani Vaidyanathan's patch:
"ENGR00257847-1 MX6Q/DL-Fix Ethernet performance issue when WAIT mode is active"
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Ranjani Vaidyanathan <ra5478@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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commit 78119fd1068cc068f6112a57a5f6de0e5b20245a upstream.
Commit 2361613206e6, "of/irq: Refactor interrupt-map parsing" introduced
a bug. The irq parsing will fail for some nodes that don't have a reg
property. It is fixed by deferring the check for reg until it is
actually needed. Also adjust the testcase data to catch the bug.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Ming Lei <tom.leiming@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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commit 79d9701559a9f3e9b2021fbd292f5e70ad75f686 upstream.
The standard interrupts property in device tree can only handle
interrupts coming from a single interrupt parent. If a device is wired
to multiple interrupt controllers, then it needs to be attached to a
node with an interrupt-map property to demux the interrupt specifiers
which is confusing. It would be a lot easier if there was a form of the
interrupts property that allows for a separate interrupt phandle for
each interrupt specifier.
This patch does exactly that by creating a new interrupts-extended
property which reuses the phandle+arguments pattern used by GPIOs and
other core bindings.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Kumar Gala <galak@codeaurora.org>
[grant.likely: removed versatile platform hunks into separate patch]
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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commit a9f10ca76d784023fc45f01f025b54e9960f4ec1 upstream.
This patch extends the DT selftest code with some test cases for the
interrupt parsing functions.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Add enet magic pattern support for imx6sx arm2 platforms.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Add enet sleep mode support for imx6sx arm2 platforms.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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When VPU freq is set to 352MHz, it need to source clk
from PLL2_PFD2_396M, and PLL2_PFD2_396M need to change
freq to 352M.
VDDSOC/PU needs to be at highest setpoint when VPU@352Mhz,
cpufreq will be disabled as it will not save any power if
VDDSOC/PU's voltage stays at highest setpoint.
Busfreq will be disabled as it needs PLL2_PFD2 to be
as 396MHz to achieve low power audio freq setpoint.
To enable VPU 352MHz feature, select it in menuconfig,
it is disabled by default.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The suspend/resume code needs to save the ARM registers that is used
in the code. The return paths from the suspend code can be different, based
on if an interrupt is pending. So we cannot depend on the kernel code to
restore the registers.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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The upsteamed commit is 0c516b4ff85c0be4cee5b30ae59c9565c7f91a00
ASoC: cs42xx8: Add codec driver support for CS42448/CS42888
This patch adds support for the Cirrus Logic CS42448/CS42888 Audio CODEC that
has six/four 24-bit AD and eight 24-bit DA converters.
[ CS42448/CS42888 supports both I2C and SPI control ports. As initial patch,
this patch only adds the support for I2C. ]
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Acked-by: Brian Austin <brian.austin@cirrus.com>
Acked-by: Paul Handrigan <Paul.Handrigan@cirrus.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Shengjiu Wang <b02247@freescale.com>
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Enable cpufreq support for i.MX6SX, currently three setpoints
are supported, the freq/volt table are as below:
VDDARM_CAP VDDSOC_CAP
996M: 1.250V 1.175V
792M: 1.175V 1.175V
396M: 1.075V 1.175V
All upper voltages are 25mV higher then the minimum value defined
in datasheet, this 25mV is to cover board level IR drop.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add cpufreq related opp info to support cpufreq
driver for i.MX6SX.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Set DDR/IO to low power mode for i.MX6SX when system enter
DSM mode, it can save ~8mW power(from 25mA lower to 19mA).
Signed-off-by: Anson Huang <b20788@freescale.com>
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Create standalone dts for a9 when m4 is running, since there
are some conflictions in the following modules
* i2c3
* flexcan1&2
* uart2
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Add busfreq support for i.MX6SX, add a new ddr3 asm code
and use a busfreq info structure to pass necessary info
for low level busfreq change function, the structure will be
placed in front of ocram function.
Signed-off-by: Anson Huang <b20788@freescale.com>
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From reference manual, periph2_pre's parent list option 3 is
pll4_audio_div, not pll2_198m. And periph2_clk2 's parent of
option 1 should be osc, not pll2.
Need to mask handshake of mmdc ch0.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add busfreq support;
Signed-off-by: Anson Huang <b20788@freescale.com>
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Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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cherry-picked commit is 43d24e76b69826ce32292f47060ad78cdd0197fa
Header of this commit is "ASoC: fsl_esai: Add ESAI CPU DAI driver", use upstream
driver to replace current one.
Merged feature is:
1. Move setting of PRRC and PCRC to the end of hw_params, and disable it in
shutdown function.
2. Merged the xrun handler with this commit.
3. Use dma init with NO_RESIDUE|NO_DT|COMPAT.
4. Add spba clock for ESAI
Signed-off-by: Shengjiu Wang <b02247@freescale.com>
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There are three clock for ESAI, esai_extal, esai_ipg, esai_mem.
Make the clock for ESAI more clear.
Signed-off-by: Shengjiu Wang <b02247@freescale.com>
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We disable spdif and sai in imx6sx-*-arm2.dts and only enable them
in their sub-dts like imx6sx-17x17-arm2-spdif.dts while we haven't
put the sound nodes into the sub-dts because the dependancy between
sound and spdif/sai. This would result people get the frequent -517
probe error everytime they insert a new device or module.
So this patch puts them to the sub-dts.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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