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* ARM: imx: replace imx6q_restart() with mxc_restart()Shawn Guo2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | The imx6q_restart() works fine with normal reboot but will run into problem with emergency reboot like sysrq-b. In that case, of_iomap() gets called from interrupt context and hence triggers the BUG_ON in __get_vm_area_node(). Actually, since commit c1e31d1 (ARM: imx: create mxc_arch_reset_init_dt() for DT boot), imx6q/dl should try to use mxc_restart() by calling mxc_arch_reset_init_dt() beforehand, where things like of_iomap() can be done. The patch updates mxc_restart() a little bit to get it work for imx6q/dl and kill imx6q_restart() completely. Reported-by: Nathan Lynch <nathan_lynch@mentor.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit 87a84b69824d7fd63b20f3bc98d75c0238b8e7d0) Conflicts: arch/arm/mach-imx/mach-imx6q.c Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00286961-3 ARM: dtsi: imx6qdl: Use non-default value for audmux pinctrlNicolin Chen2014-04-16
| | | | | | | | | | | | | It's better to specify pinctrl value so that we can clearly know what the exact configuration they are. Also, when we need to set pinctrl state from another state to default one, it must be given the exact values of pinctrl. And this patch also sets TXD iomux to PUE keep. This would force TXD pin not to pull down its signal during an unused state so that it won't distort its output signal during that state. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00286960-2 arm: imx: improve status check of clock gateAnson Huang2014-04-16
| | | | | | | | | | | | For ccm clock gate, both 2b'11 and 2b'01 should be treated as clock enabled, see below description in CCM: 2b'00: clock is off during all modes; 2b'01: clock is on in run mode, but off in wait and stop mode; 2b'10: Not applicable; 2b'11: clock is on during all modes, except stop mode. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00286960-1 arm: imx: initialize clock gate statusAnson Huang2014-04-16
| | | | | | | | | | | Some clocks gates need to be set to 2b'01 to allow CCM auto disabling them when system enters WAIT mode, this setting can save many runtime power. These clock gates are normally always enabled, so no need to add another status for clk gate enable function, just set them to right status when system boot up is good enough. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00286744-3 arm: imx: optimize power number for busfreqAnson Huang2014-04-16
| | | | | | | | | i.MX6DL's axi clock is sourcing from pfd540 by default, need to switch axi clock from pfd540 to periph when system enters low bus mode, this is to allow pfd540 to be disabled, and it also keeps clk tree correct. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00286744-2 arm: dts: imx6dl: add clks for busfreqAnson Huang2014-04-16
| | | | | | | | Need to switch axi clock from pfd540 to periph when system enters low bus mode, so add necessary clks for bufreq driver. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00286744-1 arm: imx: add necessary interface for pfdAnson Huang2014-04-16
| | | | | | | | | | | Common clk framework will disable unused clks only if they are enabled by default, so we need to add is_enabled callback for clk framework to get clks' status. pfd clocks are enabled by default, so we need to add this interface for common clk framework to disable unused pfds. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00287081 [iMX6SL] - Make sure MMDC clocks are enabled at bootRanjani Vaidyanathan2014-04-16
| | | | | | | Need to enable MMDC clocks to maintain the correct usecount, else PLL2 can get disabled incorrectly thus hanging the system. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00286345 [iMX6DL] Fixed random hang bug in bus freq driverRanjani Vaidyanathan2014-04-16
| | | | | | | | | Incorrect clock disable of PLL2 caused random hangs during DDR freq change in iMX6DL. Remove PERCLK freq change code as this is not required for TO1.1 and later. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00286971-2 dts: imx6-sabreauto: disabled flexcan when max7310 is goneDong Aisheng2014-04-16
| | | | | | | | | | | Flexcan transceiver is using GPIOs from max7310 on i2c3. Since max7310 is gone on below dts files, so there's no reason to keep flexcan alive in those dts files. Note: since flexcan1 is disabled by default, so did not need to add it. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00286971-1 imx6q: add sanity check for getting gpio for flexcanDong Aisheng2014-04-16
| | | | | | | | | | | | This is used to avoid a warning: WARNING: at /home/b29397/work/projects/linux-2.6-imx/drivers/gpio/gpiolib.c:126 gpio_to_desc+0x30/0x44() invalid GPIO -517 Modules linked in: .... gpiod_request: invalid GPIO Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00286724-11 imx_v7_defconfig: add flexcan supportDong Aisheng2014-04-16
| | | | | | Add flexcan support. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00286724-10 dts: sabreauto: add new dts for flexcan1 supportDong Aisheng2014-04-16
| | | | | | | The flexcan1 is pin conflict with fec. So we add a new dts file with flexcan1 enabled with fec disabled for user to use. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00286724-9 dts: imx6qdl: add properties for flexcan to support wakeupDong Aisheng2014-04-16
| | | | | | | According to binding doc, add missed properties for remote wakeup support. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00286724-7 ARM: dts: sabreauto: add flexcan supportDong Aisheng2014-04-16
| | | | | | The flexcan1 is disabled by default since it's conflict with fec. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00286724-6 ARM: imx6q: use auxdata to pass flexcan_switch function hookDong Aisheng2014-04-16
| | | | | | | Before we have a common can tranceiver binding to handle gpios operations, we use auxdata to pass flexcan_switch function first. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00286724-4 ARM: dts: imx6q: complement of can propertiesDong Aisheng2014-04-16
| | | | | | Add missed properties. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00286724-3 ARM: dts: imx6q: change to generic name for flexcanDong Aisheng2014-04-16
| | | | | | | As following the device tree naming rule, we change the device node name to a more generic one and use phandle name specificly. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00286273-3 arm: dtsi: imx6sl: add iram property to support internal SRAMNicolin Chen2014-04-16
| | | | | | | By doing this, we can allow SDMA driver to allocate its memory from iram when using i.MX6 SoloLite SoC. Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00286426-5 ARM: dts: imx6: add anatop phandle for usbphyPeter Chen2014-04-16
| | | | | | Add anatop phandle for usbphy Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00286181 ARM: i.MX6: add more chip revision supportJason Liu2014-04-16
| | | | | | | With the new tap-out of i.MX6DQ(TO1.5) and i.MX6DL/SOLO(TO1.2), we need add more chip revision support in order to report the chip revision correctly. Signed-off-by: Jason Liu <r64343@freescale.com>
* ARM: dts: imx6q-arm2: enable USB OTGPeter Chen2014-04-16
| | | | | | | Enable USB OTG controller at imx6q-arm2 board Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ENGR00286041 arm: imx: avoid warning message of speed grading check on i.MX6DLAnson Huang2014-04-16
| | | | | | | | | i.MX6DL did NOT have 1.2GHz setpoint, no need to check speed grading fuse for 1.2GHz opp, otherwise, there will be always warning message of "failed to disable 1.2 GHz OPP" when system boot up on i.MX6DL. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00285897 mx6 busfreq: fix system crash while enter low bus with 'maxcpus=1'Robin Gong2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use for_each_online_cpu instead of for_each_present_cpu to take this case, otherwise system will crash as below when go into low bus with 'maxcpus=1' setting in command line. Unable to handle kernel NULL pointer dereference at virtual address 00000000 pgd = 80004000 [00000000] *pgd=00000000 Internal error: Oops: 817 [#1] SMP ARM Modules linked in: CPU: 0 PID: 68 Comm: kworker/0:2 Not tainted 3.10.17-16647-g0868f35 #27 Workqueue: events reduce_bus_freq_handler task: ac156d80 ti: ac2a2000 task.ti: ac2a2000 PC is at update_ddr_freq+0x98/0x2d0 LR is at 0x0 pc : [<80021928>] lr : [<00000000>] psr: 400f0013 sp : ac2a3e98 ip : 00000000 fp : 814db740 r10: 016e3600 r9 : 00000000 r8 : 00000000 r7 : 814de900 r6 : 80c60cc0 r5 : 0000000f r4 : 80c60dc0 r3 : 00000000 r2 : 80c60dc0 r1 : 80c60d34 r0 : 00000000 Flags: nZcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c53c7d Table: 3c49404a DAC: 00000015 Process kworker/0:2 (pid: 68, stack limit = 0xac2a2238) Stack: (0xac2a3e98 to 0xac2a4000) 3e80: 00000000 00000000 3ea0: 00000000 00000000 00000001 80c60cc0 80c603a4 80c60cc0 814de900 00000000 3ec0: 00000000 ac2a2038 814db740 80020154 00000064 ac02f6c0 00000004 80c2103c 3ee0: 80c60d38 814db740 814de900 80020628 ac135780 8003d7ac 00000001 ac083eb8 3f00: 00000000 00000000 00000003 ac135780 814db754 ac135798 ac2a2000 ac2a2030 3f20: 00000001 ac2a2000 814db740 8003e4b8 8003e380 00000000 00000000 80c5fcc1 3f40: ac2a3f64 ac083ea0 00000000 ac135780 8003e380 00000000 00000000 00000000 3f60: 00000000 800437e0 fd7efff9 00000000 7faf7bfd ac135780 00000000 00000000 3f80: ac2a3f80 ac2a3f80 00000000 00000000 ac2a3f90 ac2a3f90 ac2a3fac ac083ea0 3fa0: 8004372c 00000000 00000000 8000e018 00000000 00000000 00000000 00000000 3fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 3fe0: 00000000 00000000 00000000 00000000 00000013 00000000 fffc7fae d4cadbdb [<80021928>] (update_ddr_freq+0x98/0x2d0) from [<80020154>] (reduce_bus_freq+ 0x58/0x518) [<80020154>] (reduce_bus_freq+0x58/0x518) from [<80020628>] (reduce_bus_freq_ handler+0x14/0x24) [<80020628>] (reduce_bus_freq_handler+0x14/0x24) from [<8003d7ac>] (process_one _work+0x10c/0x374) [<8003d7ac>] (process_one_work+0x10c/0x374) from [<8003e4b8>] (worker_thread+ 0x138/0x3fc) [<8003e4b8>] (worker_thread+0x138/0x3fc) from [<800437e0>] (kthread+0xb4/0xb8) [<800437e0>] (kthread+0xb4/0xb8) from [<8000e018>] (ret_from_fork+0x14/0x3c) Code: e5940014 e3002dc0 e594e018 e34820c6 (e5835000) ---[ end trace 206df98575045d04 ]--- Unable to handle kernel paging request at virtual address ffffffec pgd = 80004000 [ffffffec] *pgd=3ff7e821, *pte=00000000, *ppte=00000000 Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00286060 arm: imx6q/dl: fix 1588 clock init failFugang Duan2014-04-16
| | | | | | | | | | | | | | | | | | Bug log during kernel boot: ... failed to find fsl,imx6q-iomux-gpr regmap ... The issue is imx6q_1588_init() is called before of_platform_populate(). of_platform_populate() walks the device tree and creates devices from nodes. imx6q_1588_init() call syscon_regmap_lookup_by_compatible() to get the device base on the given device node, since the device cannot created for the node, so it is failed. So, move the 1588 init function to behind of of_platform_populate(). Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00285692 arm: imx: add necessary clock gates into clk treeAnson Huang2014-04-16
| | | | | | | | | | 1. add epit1, epit2 and tzasc2 clock gate to clk tree so that clk framework can manage these clock gates; 2. adjust ipu2_di1 clock gate registry code to follow hardware register CG index sequence. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00285646 enable usb peripheral mode for auto spi-nor and gpmi nandFrank Li2014-04-16
| | | | | | | enable usb peripheral mode for sabreauto ecspi.dtb and gpmi-weim.dtb because mfgtools need usb device support Signed-off-by: Frank Li <Frank.Li@freescale.com>
* ENGR00284981-2 arm: dts: imx6qdl: correct caam clock indexAnson Huang2014-04-16
| | | | | | Correct caam module clocks index according to clock tree. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00284981-1 arm: imx: add clock nodes for caamAnson Huang2014-04-16
| | | | | | | Add caam clock gate nodes into clock tree, so that caam driver can manage its clock gate to save power. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00284023 [iMX6DL/iMX6SL]Align VDDARM and VDDSOC voltages to latest datasheetRanjani Vaidyanathan2014-04-16
| | | | | | Add 25mV PMIC tolerence to the voltages. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00284019: [iMX6SL] Add low power mode optimizationsRanjani Vaidyanathan2014-04-16
| | | | | | | | | | | | | | Add optimizations so that the low power IDLE mode numbers match between the 3.10.9 and 3.0.35 kernel. Optimizations include: 1. Disable unused PLLs and PFDs in clock init 2. Some of the drivers call clk_prepare in probe and enable much later. clk_pllv3_prepare locks the PLL disallowing some of the low power optimizations. For iMX6SL ensure that clk_pllv3_prepare does not lock the PLL. 3. Ensure that MMDC_CH0_LPM_HS is set when WAIT mode is entered. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ARM: dts: imx6sl: add pinctrl uhs states for usdhcDong Aisheng2014-04-16
| | | | | | | This is needed for SD3.0 cards working on UHS mode. Signed-off-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ENGR00284180-2 ARM: dts: imx6sl-evk: enable the SPI NORHuang Shijie2014-04-16
| | | | | | enable the spi nor for imx6sl-evk boards. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00284180-1 ARM: dts: imx6sl: add a pinctrl for ECSPI1Huang Shijie2014-04-16
| | | | | | add a pinctrl for ECSPI1. This pinctrl can be used in the imx6sl-evk board. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00283508-6 arm: dts: imx6sl: support hog pins sleep modeAnson Huang2014-04-16
| | | | | | | | | | | As i.MX6SL EVK board is very sensitive to DSM power, so we need to lower IO power of hog pins: MX6SL_PAD_KEY_ROW5__GPIO4_IO03 MX6SL_PAD_KEY_COL6__GPIO4_IO04 MX6SL_PAD_LCD_RESET__GPIO2_IO19 Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00283508-4 arm: dts: imx6sl: support kpp pin sleep modeAnson Huang2014-04-16
| | | | | | | | | | | | | | | | | | Improve those kpp pins pad setting with no_pad_ctrl defined, actually they are using default pad setting, to support pin mode switch, we need to set them manually. As i.MX6SL EVK board is very sensitive to DSM power, so we need to lower IO power of KPP pins: MX6SL_PAD_KEY_ROW0__KEY_ROW0 MX6SL_PAD_KEY_ROW1__KEY_ROW1 MX6SL_PAD_KEY_ROW2__KEY_ROW2 MX6SL_PAD_KEY_COL0__KEY_COL0 MX6SL_PAD_KEY_COL1__KEY_COL1 MX6SL_PAD_KEY_COL2__KEY_COL2 Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00283508-2 arm: dts: imx6sl: support pwm pin sleep modeAnson Huang2014-04-16
| | | | | | | | | As i.MX6SL EVK board is very sensitive to DSM power, so we need to lower IO power of PWM pin: MX6SL_PAD_PWM1__GPIO3_IO23 Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00283496 ARM: clk: imx6sl: update epdc pixel clock treeRobby Cai2014-04-16
| | | | | | | Add CLK_SET_RATE_PARENT flag for epdc pixel clock to allow the rate change operation to propagate up to the clock's parent in order to get desired rate. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00281769 [iMX6SL] Allow uart to be sourced from 24MHz XTALRanjani Vaidyanathan2014-04-16
| | | | | | | | | | In order to optmize low power IDLE numbers all PLLs should be in bypass. On imx6sl, UART can be sourced directly from the 24MHz XTAL. Its frequency is limited to 4MHz due to an internal divide by 6 divider. For customer who don't require higher uart speeds add "uart_at_4M" to the kernel command line. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00283480 imx_v7_defconfig: enable MLB150 moduleLuwei Zhou2014-04-16
| | | | | | Add MLB150 module support in imx_v7_defconfig Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00283470 ARM: dts: imxqdl-sabreauto: add dts support for MLB150Luwei Zhou2014-04-16
| | | | | | | This patch add MLB150 dts support on SabreAuto.The PAD setting is aligned to 3.0.35 kernel. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00283540-01 dts:imx6sl: add fec sleep pinctrl for pin PM stateAnson Huang2014-04-16
| | | | | | | | | | when system suspend, need to set pins to low power state to save IO power consumption, there are three states of pinctrl: "default", "idle" and "sleep". Currently enet supports default and sleep state. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00280494-2 Add config for mfgtoolsFrank Li2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Build in USB Mass storage Enable CONFIG_FSL_UTP Must list all gadgets in config file otherwise CONFIG_USB_MASS_STORAGE becomes to m +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +CONFIG_USB_MASS_STORAGE=y +CONFIG_FSL_UTP=y +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set Signed-off-by: Frank Li <Frank.li@freescale.com>
* ENGR00281017 [MX6SL]Low power IDLE mode optimizationsRanjani Vaidyanathan2014-04-16
| | | | | | | | | | | | | | | | | Added a new bus freq mode - ultra_low_bus_freq_mode. In this mode the ARM is the only bus master that is active and the system is already in low power idle mode. And when ARM executes WFI in this mode, we do some aggressive power savings techinques like: 1. Drop DDR freq to 1MHz 2. Drop AHB freq to 3MHz 3. Float the DDR IO pads 4. If all PLLs are in bypass (which should be the case), do some analog power saving options like reducing the OSC-bias current, turning off the regular bandgap, disabling the regular 2P5, enabling the weak 2p5 etc. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00281804 ARM: imx6: init enet MAC addressFugang Duan2014-04-16
| | | | | | | | | | | | | | | Enet get MAC address order: From module parameters or kernel command line -> device tree -> pfuse -> mac registers set by bootloader -> random mac address. When there have no "fec.macaddr" parameters set in kernel command line, enet driver get MAC address from device tree. And then if the MAC address set in device tree and is valid, enet driver get MAC address from device tree. Otherwise,enet get MAC address from pfuse. So, in the condition, update the MAC address (read from pfuse) to device tree. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00281789-02 ARM: dts: imx6sl: correct the enet ipg clockFugang Duan2014-04-16
| | | | | | | Current imx6sl dts define enet_ref clock as ipg clock, which is not right. The ipg clock is "IMX6SL_CLK_ENET" defined at imx6sl-clock.h. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00281789-01 imx6sl: add missing enet clock for imx6slFugang Duan2014-04-16
| | | | | | There's a enet clock gate missing in clock tree, thus add it. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00280852-6 mxc: asrc: Use devtype instead of specific DT propertiesNicolin Chen2014-04-16
| | | | | | | We can determine the IP version from DT compatible name to decide which clock map and channel bits should be used. Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00280852-2 arm: dtsi: imx6qdl: Set sdma priority of ASRC to mediumNicolin Chen2014-04-16
| | | | | | Set the priority as what kernel 3.0.35 does to keep it safe. Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00280852-1 mxc: asrc: Add spba clock control for sdma shp scriptNicolin Chen2014-04-16
| | | | | | | | | | | ASRC is using shp_2_mcu and mcu_2_shp sdma scripts that use spba bus to transfer data, while the driver hasn't include the control code of spba clock. This would cause multiple pair conversion failed in most of time. Thus we need to add its support. Signed-off-by: Nicolin Chen <b42378@freescale.com>
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