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* ENGR00310290 ARM: imx: enable necessary clocks for i.mx6sxAnson Huang2014-04-25
| | | | | | | | On i.MX6SX, when CA9 and CM4 are working together, CA9 can NOT disable those shared modules' clock, so keep those clocks CM4 needs always enabled. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00309977-2 ARM: imx6q/sl: Set SPDIF clock to 22736841HzNicolin Chen2014-04-23
| | | | | | | | | | | | | | | | | | | | Since we no longer use clk_set_rate() in spdif driver, the rate we provide to it on imx6q/sl platforms is no more contented for its supporting sample rates. By setting the clock to 22736841Hz, we can get the sample rates: 48008Hz for 48000Hz 32005Hz for 32000Hz 43859Hz for 44100Hz The results for 48KHz and 32KHz has changed comparing to the previous release, but the one for 44100Hz has a bit lose even though it should be the best we can get based on the current clock rate. If user want to playback a perfect 44100Hz, they need to change the parent clock rate. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00309977-1 ARM: imx6sx: Separate SPDIF and Audio clocksNicolin Chen2014-04-23
| | | | | | | | | | | | | | | | | | | Shawn's patch -- ARM: imx: shared gate support for i.MX clk_gate2 clocko has fixed the problem of clock conflicts due to sharing a same gate. So from now on, we can no longer need to take care the shared gate clock for each audio clock route. Thus this patch separates them by using the new clock registering helper function. And meanwhile, we set a proper rate for each route so as to support each module. For S/PDIF, we use 98304000Hz so that the current driver would perfectly get 32000Hz and 48000Hz sample rate playback support, even though we can only get 43885Hz for 44100Hz sample rate in this way -- If user want to playback 44100Hz group sample rates, they need to change the parent rate. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00309934 ARM: imx_v7_defconfig: Select CONFIG_USB_G_NCM as moduleLi Jun2014-04-23
| | | | | | Enable g_ncm as module for use g_ncm gadget driver. Signed-off-by: Li Jun <b47624@freescale.com>
* ARM: imx: add shared gate clock supportShawn Guo2014-04-22
| | | | | | | | | | | | | | | It's quite common on i.MX that one gate bit controls the gating of multiple clocks, i.e. this is a shared gate. The patch adds the function imx_clk_gate2_shared() for such case. The clocks controlled by the same gate bits should call this function with a pointer to a single share count variable, so that the gate bits will only be operated on the first enabling and the last disabling of these shared gate clocks. Thanks to Gerhard Sittig <gsi@denx.de> for this idea. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ARM: imx: lock is always valid for clk_gate2Shawn Guo2014-04-22
| | | | | | | | The imx specific clk_gate2 always has a valid lock with the clock. So the validation on gate->lock is not really needed. Remove it. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ARM: imx: define struct clk_gate2 on our ownShawn Guo2014-04-22
| | | | | | | | | | | | | The imx clk-gate2 driver implements an i.MX specific gate clock, which has two bits controlling the gate states. While this is a completely separate gate driver from the common clk-gate one, it reuses the common clk_gate structure. Such reusing makes the extending of clk_gate2 clumsy. Let's define struct clk_gate2 on our own to make the driver independent of the common clk-gate one, and ease the clk_gate2 extending at a later time. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00309828 ARM: imx6sx: Add imx6sx-17x17-arm2-mlb.dtb in MakefileLuwei Zhou2014-04-22
| | | | | | Add imx6sx-17x17-arm2-mlb.dtb in devicetree makefile list Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ARM: imx6: clk: i.MX6 DualLite/Solo i2c4 clockIain Paton2014-04-19
| | | | | | | | | | Compared to i.MX6 Quad/Dual the CCM_CCGR1 register in the i.MX6 Solo/DualLite replaces the ecspi5 clock with the i2c4 clock. Handle this difference using cpu_is_imx6dl(). Signed-off-by: Iain Paton <ipaton0@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00309297-2 ARM: imx6sx: Updata asrc_p2p DT bindingsNicolin Chen2014-04-18
| | | | | | | | Since we changed asrc_p2p's DT bindings to support record case, we should update it in imx6sx platform as well. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00309073-1 ASoC: fsl: Naming of p2p item is not properShengjiu Wang2014-04-17
| | | | | | Change the output-rate, output-width to p2p-rate, p2p-width. Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* ENGR00308643 Add imx6sx-19x19-arm2-csi.dtsSandor Yu2014-04-17
| | | | | | | csi camera ov5640 pin conflict with esai and sai in 19x19 arm2 board, add this file to resolve it. Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00307014-08 enable vadc in defconfigSandor Yu2014-04-17
| | | | | | Default add vadc to defconfig as module. Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00307014-07 ARM: DTS: Add vadc driver in imx6sx dtsSandor Yu2014-04-17
| | | | | | | Add vadc item in imx6sx.dtsi and enable it in 19x19 arm2 and sdb board. Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00307014-04 ARM: imx6x: Set vadc clock source from Pll3Sandor Yu2014-04-17
| | | | | | Set vadc clock parent to PLL3 USB OTG. Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00309031-2 dts: imx6sx-sdb-emmc: add emmc support on uSDHC4Dong Aisheng2014-04-17
| | | | | | | | | The eMMC interface is shared with uSDHC4 BOOT card slot and the eMMC chip is DNP by default. User needs burn the eMMC chip onto the board manually and do hw rework to enable eMMC signals. We create a new dts imx6sx-sdb-emmc.dts for easy eMMC test after doing hw rework. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00309031-1 dts: imx6sx-sdb: move usdhc4 gpios pins out of hog groupDong Aisheng2014-04-17
| | | | | | | | | | | | | | For imx6sx sdb board, the eMMC interface and uSDHC4 BOOT card slot are shared and the eMMC chip is DNP by default. If burn the eMMC chip onto the board and do hw rework to enable eMMC signals, the cd-gpio and wp-gpios will be reused as eMMC DATA signals. So we'd better move this two gpio pin out of hog group for easy disable this gpio setting in another dts. It's required for the next patch which adds the eMMC support in another dts file. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ARM: dts: imx6sl-evk: Keep VGEN1 regulator always enabledFabio Estevam2014-04-16
| | | | | | | | | | | | | | | | | | | On imx6sl-evk board the VGEN1 regulator powers up the NVCC_1P2V domain of the imx6sl SoC, so we need to keep it always powered. According to imx6sl datasheet the GPIO block has three supplies: NVCC33_IO, NVCC18_IO and NVCC_1P2V and it states that: "All digital I/O supplies (NVCC_xxxx) must be powered under normal conditions whether the associated I/O pins are in use or not" This problem has been observed by the fact that a GPIO connected to an LED could not work when the PMIC driver was enabled. Keeping VGEN1 regulator always enabled fixes the problem. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit d2c3936ebe88ce3cc188d01be0c684884e396293)
* ENGR00308382-2 mcc: enable mcc a9 linux demoRichard Zhu2014-04-16
| | | | | | enable mcc a9 linux demo on imx6sx. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00308060-4 arm: add the mcc supportRichard Zhu2014-04-16
| | | | | | enable imx6sx mcc support. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00308060-2 mcc: implementation mcc on imx6sxRichard Zhu2014-04-16
| | | | | | | | | | | | | | | | | | | - inherited mcc ver 001.002 from vibryd mqx release. - use mu general int4 as the cpu2cpu int (num is 122 at a9 side). - add linux wait_event/wake_up mechanism on the buffer management of share memory - replace wait_event_interruptible### by wait_event###, so the sleep task wouldn't be waken up by reboot or CTRL+C signals. - use the offset address to do the MQX_TO_VIRT and VIRT_TO_MQX exchanges. - regmap_bits_updat can't write 1 to clear the bit-set asr, use regmap_read/write - fix mu irq clear hang issue only do the regmap once in the isr register func, and replace the multi-regmap operations in the kinds of mx6sx mcc related apis by one global imx_mu_reg. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00308060-1 mcc: implementation mcc common on imx6sxRichard Zhu2014-04-16
| | | | | | | | | | | | | - inherited mcc ver 001.002 from vibryd mqx release. - let lwevent related codes mqx specified. - use the offset address to do the MQX_TO_VIRT and VIRT_TO_MQX exchanges. - add some modification in mcc common codes, since all the shm access should be protected by sema4. - double check the list head, and make the recv more robust. Acked-by: Shawn Guo Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00308478 ARM: dts: imx6sx-sdb: Add camera support via the camera adapterRobby Cai2014-04-16
| | | | | | | | | | | | | | Previously we support camera features via mx51 expansion board due to footprint mirror issue on imx6sx sdb board. Now we switch to the adapter board (sch700-28342) to support same features. And the support via mx51 expansion board is deprecated. The changes include - Change the PINs setting for power and reset signal. - Add status flag to avoid the conflict use of LCD1_RESET pin by LCDIF1/CSI. For LCDIF1, it's used as LCD_PWR_EN, for CSI/camera, as RESET pin. Signed-off-by: Robby Cai <r63905@freescale.com>
* ENGR00305366-01 net: fec: disable netfilter in defaultFugang Duan2014-04-16
| | | | | | | Disable netfilter feature for enet can increase 30Mbps bandwidth for imx6sx enet tx path. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00307635-8 ARM: imx6sx: Add SAI support to each board level dtsNicolin Chen2014-04-16
| | | | | | | | | | | SAI has pin conflicts with other moudles on all current boards of Solo X and two sdma event conflicts with UART5. Thus this patch adds new dtbs for SAI cases that occupy the pins and the event IDs of SDMA. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00307635-7 ARM: imx6sx: Update SAI DT bindings and its pinctrl groupsNicolin Chen2014-04-16
| | | | | | | | | | Since we adds clock controls to SAI driver, we should also update its DTB to support it. This patch also appends two essential pinctrl groups to the DTB. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00307635-5 ASoC: imx-wm8962: Add non-SSI cpu dai supportNicolin Chen2014-04-16
| | | | | | | | | | | | The current imx-wm8962 machine driver is designed for SSI as CPU DAI only while as its name we should make the driver more generic to any other CPU DAI on i.MX serires -- ESAI, SAI for example. So this patch makes the driver more general so as to support those non-SSI cases. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00307635-4 ARM: imx6sx: Use 24.576MHz for both SSI and SAI clocksNicolin Chen2014-04-16
| | | | | | | SAI derives its mclk from SSI_CLK, so this patch sets a default value for them. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00307635-3 ARM: imx6sx: Update sdma DT bindingNicolin Chen2014-04-16
| | | | | | | | | Since we've created a new compatible for imx6sx-sdma, we here update its dtsi accordingly. Acked-by: Robin Gong <b38343@freescale.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00306955-2 ARM:dts:im6x: Add device tree for IRAM used by low power code.Ranjani Vaidyanathan2014-04-16
| | | | | | | Ensure that fsl,lpm-sram is only set for the memory that is used by low power code in the dts files. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00306955-1 ARM:imx6x Ensure that both IRAM and OCRAM_S can be mapped in ↵Ranjani Vaidyanathan2014-04-16
| | | | | | | | | | | | | | | | | | | the IRAM page table To prevent a page table walk in the DDR, its required that the low power code use a minimal set of page tables that are stored in IRAM. This IRAM page table needs to have a known virtual address so the mapping needs to be created at the beginning of boot using iotable_init(). This patch fixes the following issues: 1. Ensure that OCRAM_S, IRAM, AIPS1 and AIPS2 can all be mapped by the IMX_IO_P2V macro. 2. Ensure Section mapping is used for the required addresses in the IRAM page table. 3. Obtain the address of the IRAM/OCRAM_S to be used by low power code from the device tree. Since the device tree is not setup early in the boot, use the flat device tree apis to get the address. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00306653-3: ARM: imx_v7_defconfig enable snvs_pwrkey driver by defaultRobin Gong2014-04-16
| | | | | | enable snvs_pwrkey driver by default Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00306653-1: ARM: dts: imx6sx: add snvs power key nodeRobin Gong2014-04-16
| | | | | | | Put snvs-pwrkey device node in imx6sx.dtsi since all boards with i.mx6sx were designed with ONOFF as power key and it's a function at soc level. Signed-off-by: Robin Gong <b38343@freescale.com>
* Input: tsc2007 - add device tree support.Denis Carikli2014-04-16
| | | | | Signed-off-by: Denis Carikli <denis@eukrea.com> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
* ENGR00306443-2 dts:Add QoS description in imx6sx dtsLoren HUANG2014-04-16
| | | | | | Add QoS description in imx6sx dts for gc400t QoS adjustment. Signed-off-by: Loren HUANG <b02279@freescale.com>
* ENGR00306443-1 mx6sx:Update the gc400t QoSLoren HUANG2014-04-16
| | | | | | | | | | Per SoC team recommandation, update the gc400t QoS value to write 2 and Read 8. It can improve gpu performance in most case. 3d fill: 165->172Mpixel/s 2d fill: 190->228Mpixel/s Signed-off-by: Loren HUANG <b02279@freescale.com>
* ENGR00298286 arm: dts: imx6qdl: add clock to CAAM.Dan Douglass2014-04-16
| | | | | | | | CAAM depends on the clock used by WEIM interface. This patch supplied by Haung Shijie corrects the issue by adding the clock to the device tree entry for CAAM. Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
* ENGR00306569: ARM: dts: imx6sx-sdb: Add mma8451 sensor dts supportLuwei Zhou2014-04-16
| | | | | | | This patch add mma8451 sensor device tree support on i.MX6SX-SDB platform. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ARM: 7669/1: keep __my_cpu_offset consistent with generic oneMing Lei2014-04-16
| | | | | | | | | | | | | | | | | | | | | Commit 14318efb(ARM: 7587/1: implement optimized percpu variable access) introduces arm's __my_cpu_offset to optimize percpu vaiable access, which really works well on hackbench, but will cause __my_cpu_offset to return garbage value before it is initialized in cpu_init() called by setup_arch, so accessing percpu variable before setup_arch may cause kernel hang. But generic __my_cpu_offset always returns zero before percpu area is brought up, and won't hang kernel. So the patch tries to clear __my_cpu_offset on boot CPU early to avoid boot hang. At least now percpu variable is accessed by lockdep before setup_arch(), and enabling CONFIG_LOCK_STAT or CONFIG_DEBUG_LOCKDEP can trigger kernel hang. Signed-off-by: Ming Lei <tom.leiming@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> (cherry picked from commit 9394c1c65e61eb6f4c1c99f342b49e451ec337b6)
* ENGR00300157: ARM: dts: imx6sl-evk-common: correct the pad setting of ↵Robin Gong2014-04-16
| | | | | | | | | EPDC_PWRCTRL3 align with the same setting with v3.0.35, otherwise, cause 'POR' reset if EPDC daughter board attached sometimes. Signed-off-by: Robin Gong <b38343@freescale.com>
* ARM: 7811/1: locks: use early clobber in arch_spin_trylockWill Deacon2014-04-16
| | | | | | | | | | | | | commit afa31d8eb86fc2f25083e675d57ac8173a98f999 upstream. The res variable is written before we've finished with the input operands (namely the lock address), so ensure that we mark it as `early clobber' to avoid unintended register sharing. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Wang Weidong <wangweidong1@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: 7812/1: rwlocks: retry trylock operation if strex fails on free lockWill Deacon2014-04-16
| | | | | | | | | | | | | | | | commit 00efaa0250939dc148e2d3104fb3c18395d24a2d upstream. Commit 15e7e5c1ebf5 ("ARM: 7749/1: spinlock: retry trylock operation if strex fails on free lock") modifying our arch_spin_trylock to retry the acquisition if the lock appeared uncontended, but the strex failed. This patch does the same for rwlocks, which were missed by the original patch. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Li Zefan <lizefan@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: 7749/1: spinlock: retry trylock operation if strex fails on free lockWill Deacon2014-04-16
| | | | | | | | | | | | | | | | commit 15e7e5c1ebf556cd620c9b091e121091ac760f6d upstream. An exclusive store instruction may fail for reasons other than lock contention (e.g. a cache eviction during the critical section) so, in line with other architectures using similar exclusive instructions (alpha, mips, powerpc), retry the trylock operation if the lock appears to be free but the strex reported failure. Reported-by: Tony Thompson <anthony.thompson@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Li Zefan <lizefan@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: 7957/1: add DSB after icache flush in __flush_icache_all()Vinayak Kale2014-04-16
| | | | | | | | | | | commit 39544ac9df20f73e49fc6b9ac19ff533388c82c0 upstream. Add DSB after icache flush to complete the cache maintenance operation. Signed-off-by: Vinayak Kale <vkale@apm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: 7953/1: mm: ensure TLB invalidation is complete before enabling MMUWill Deacon2014-04-16
| | | | | | | | | | | | | | | | | | | commit bae0ca2bc550d1ec6a118fb8f2696f18c4da3d8e upstream. During __v{6,7}_setup, we invalidate the TLBs since we are about to enable the MMU on return to head.S. Unfortunately, without a subsequent dsb instruction, the invalidation is not guaranteed to have completed by the time we write to the sctlr, potentially exposing us to junk/stale translations cached in the TLB. This patch reworks the init functions so that the dsb used to ensure completion of cache/predictor maintenance is also used to ensure completion of the TLB invalidation. Reported-by: Albin Tonnerre <Albin.Tonnerre@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ENGR00306165: ARM: dts: imx6q/dl: Modify the mag3110 interrupt flagLuwei Zhou2014-04-16
| | | | | | This patch modify the sensor mag3110 interrupt flag to rising edege. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00306133-2: ARM: dts: imx6sx-sdb: Add isl29023 dts supportLuwei Zhou2014-04-16
| | | | | | | This patch add isl29023 sensor device tree support on i.MX6SX-SDB platform. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00306134-2: ARM: dts: imx6sx-sdb: Add mag3110 dts supportLuwei Zhou2014-04-16
| | | | | | | This patch add mag3110 sensor device tree support on i.MX6SX-SDB platform. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00303701-3 ARM: clk: imx6sx: use the 132MHz for the WEIMHuang Shijie2014-04-16
| | | | | | We set the maximum clock frequency for the WEIM module. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00303701-2 ARM: dts: imx6sx-19x19-arm2: enable the WEIMHuang Shijie2014-04-16
| | | | | | enable the 32MB parallel NOR flash. Signed-off-by: Huang Shijie <b32955@freescale.com>
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