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| * | | | | ARM: tegra: solve adr range issue with THUMB2_KERNEL enabledStephen Warren2013-04-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building the kernel with CONFIG_THUMB2_KERNEL enabled, older assemblers may emit the following error: reset-handler.S:78: Error: invalid immediate for address calculation (value = 0x00000004) Using an explicit adr.w instruction will solve this. Newer assemblers do this automatically. Use the W() macro to do this under Thumb mode only. Inspired-by: Joseph Lo <josephl@nvidia.com> Suggested-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | | ARM: tegra: fix relocation truncated error when THUMB2_KERNEL enabledJoseph Lo2013-04-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The conditional branch instruction in Thumb2 only available to short range. The linker will fail when the conditional branch over the range. Then resulting in link error when generating kernel image. e.g.: arch/arm/mach-tegra/reset-handler.S:47:(.text+0xf8e): relocation truncated to fit: R_ARM_THM_JUMP19 against symbol `cpu_resume' defined in .data section in arch/arm/kernel/built-in.o This patch using a Thumb2 instruction IT (if-then) to have a longer branch range. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | | ARM: tegra: fix build error when THUMB2_KERNEL enabledJoseph Lo2013-04-18
| | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fix the build failure when CONFIG_THUBM2_KERNEL enabled. You clould see the error message below: arch/arm/mach-tegra/sleep-tegra30.S:69: Error: shift must be constant -- `orr r12,r12,r4,lsl r3' Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | ARM: tegra: powergate: Don't error out if new state == old stateThierry Reding2013-03-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't treat it as an error if a partition is already in the same power state when a user wants to power it on or off. This allows code to proceed if no state change is required. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | ARM: tegra: Export tegra_powergate_sequence_power_up()Thierry Reding2013-03-29
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function can be used by drivers to enable power to the hardware blocks that they drive. Most of the drivers can be built as a module and therefore require this function to be exported. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | ARM: tegra: fix ignored return value of regulator_enableStephen Warren2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes: arch/arm/mach-tegra/board-harmony-pcie.c: In function ‘harmony_pcie_init’: arch/arm/mach-tegra/board-harmony-pcie.c:65:18: warning: ignoring return value of ‘regulator_enable’, declared with attribute warn_unused_result [-Wunused-result] Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | ARM: tegra: fix the logical detection of power on sequence of warm boot CPUsJoseph Lo2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The warm boot sequence of Tegra30 secondary CPUs should wait for the power ready then removing the clamps. This did not fix any known or unknown issue, but nice to have this fix. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | ARM: tegra: Fix unchecked return valueHiroshi Doyu2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check a return value for tegra_powergate_remove_clamping(). Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | ARM: tegra: don't unlock MMIO access to DBGLARJoseph Lo2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to unlock MMIO access to the DBGLAR all the time. Doing so may even cause problems if a SW bug causes writes to that MMIO region. Cortex-A15 processors do not support the CP14 register write the code currently uses to unlock the DBGLAR; the instruction throws an undefined instruction exceptions. This prevents tegra_secondary_startup() from executing on Tegra114, and hence prevents SMP. Remove the code that unlocks this access. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | ARM: tegra: remove save/restore of CPU diag registerStephen Warren2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this change, {save,restore}_cpu_arch_register() collaborated to maintain the value of the CPU diagnostic register across power cycles. This was required to maintain any CPU errata workaround enable bits in that register. However, now that the Tegra reset vector code always enables all required workarounds, there is no need to save and restore the diagnostic register; it is always explicitly programmed in the required manner. Hence, remove the save/restore logic. This has the advantage that the kernel always directly controls the value of this register every boot, rather than relying on a bootloader or other kernel code having previously written the correct value into it. This makes CPU0 (which was previously saved/restored) and CPUn (which should have been set up by the reset vector) be controlled in exactly the same way, which is easier to debug/find/... In particular, when converting Tegra to a multi-platform kernel, the CPU0 diagnostic register value initially comes from the bootloader. Most Tegra bootloaders don't yet enable all required CPU bug workarounds. The previous commit updates the kernel to do so on any CPU power cycle. However, the save/restore code ends up over-writing the value with the old bootloader-driven value instead of the now more-likely-to-be-correct kernel value! Even irrespective of multi-platform conversion, this change limits the kernel's exposure to any WARs the bootloader didn't enable for CPU0: on the very first LP2 transition (CPU power-saving which power-cycles the CPU), the correct value will be enabled. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | ARM: tegra: add CPU errata WARs to Tegra reset handlerStephen Warren2013-03-11
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU cores in Tegra contain some errata. Workarounds must be applied for these every time a CPU boots. Implement those workarounds directly in the Tegra-specific CPU reset vector. Many of these workarounds duplicate code in the core ARM kernel. However, the core ARM kernel cannot enable those workarounds when building a multi-platform kernel, since they require writing to secure- only registers, and a multi-platform kernel often does not run in secure mode, and also cannot generically/architecturally detect whether it is running in secure mode, and hence cannot either unconditionally or conditionally apply these workarounds. Instead, the workarounds must be applied in architecture-specific reset code, which is able to have more direct knowledge of the secure/normal state. On Tegra, we will be able to detect this using a non-architected register in the future, although we currently assume the kernel runs only in secure mode. Other SoCs may never run the kernel in secure mode, and hence always rely on a secure monitor to enable the workarounds, and hence never implement them in the kernel. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | Merge tag 'pm+acpi-3.10-rc1' of ↵Linus Torvalds2013-04-30
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull power management and ACPI updates from Rafael J Wysocki: - ARM big.LITTLE cpufreq driver from Viresh Kumar. - exynos5440 cpufreq driver from Amit Daniel Kachhap. - cpufreq core cleanup and code consolidation from Viresh Kumar and Stratos Karafotis. - cpufreq scalability improvement from Nathan Zimmer. - AMD "frequency sensitivity feedback" powersave bias for the ondemand cpufreq governor from Jacob Shin. - cpuidle code consolidation and cleanups from Daniel Lezcano. - ARM OMAP cpuidle fixes from Santosh Shilimkar and Daniel Lezcano. - ACPICA fixes and other improvements from Bob Moore, Jung-uk Kim, Lv Zheng, Yinghai Lu, Tang Chen, Colin Ian King, and Linn Crosetto. - ACPI core updates related to hotplug from Toshi Kani, Paul Bolle, Yasuaki Ishimatsu, and Rafael J Wysocki. - Intel Lynxpoint LPSS (Low-Power Subsystem) support improvements from Rafael J Wysocki and Andy Shevchenko. * tag 'pm+acpi-3.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (192 commits) cpufreq: Revert incorrect commit 5800043 cpufreq: MAINTAINERS: Add co-maintainer cpuidle: add maintainer entry ACPI / thermal: do not always return THERMAL_TREND_RAISING for active trip points ARM: s3c64xx: cpuidle: use init/exit common routine cpufreq: pxa2xx: initialize variables ACPI: video: correct acpi_video_bus_add error processing SH: cpuidle: use init/exit common routine ARM: S5pv210: compiling issue, ARM_S5PV210_CPUFREQ needs CONFIG_CPU_FREQ_TABLE=y ACPI: Fix wrong parameter passed to memblock_reserve cpuidle: fix comment format pnp: use %*phC to dump small buffers isapnp: remove debug leftovers ARM: imx: cpuidle: use init/exit common routine ARM: davinci: cpuidle: use init/exit common routine ARM: kirkwood: cpuidle: use init/exit common routine ARM: calxeda: cpuidle: use init/exit common routine ARM: tegra: cpuidle: use init/exit common routine for tegra3 ARM: tegra: cpuidle: use init/exit common routine for tegra2 ARM: OMAP4: cpuidle: use init/exit common routine ...
| * \ \ Merge branch 'pm-cpufreq'Rafael J. Wysocki2013-04-27
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pm-cpufreq: (57 commits) cpufreq: MAINTAINERS: Add co-maintainer cpufreq: pxa2xx: initialize variables ARM: S5pv210: compiling issue, ARM_S5PV210_CPUFREQ needs CONFIG_CPU_FREQ_TABLE=y cpufreq: cpu0: Put cpu parent node after using it cpufreq: ARM big LITTLE: Adapt to latest cpufreq updates cpufreq: ARM big LITTLE: put DT nodes after using them cpufreq: Don't call __cpufreq_governor() for drivers without target() cpufreq: exynos5440: Protect OPP search calls with RCU lock cpufreq: dbx500: Round to closest available freq cpufreq: Call __cpufreq_governor() with correct policy->cpus mask cpufreq / intel_pstate: Optimize intel_pstate_set_policy cpufreq: OMAP: instantiate omap-cpufreq as a platform_driver arm: exynos: Enable OPP library support for exynos5440 cpufreq: exynos: Remove error return even if no soc is found cpufreq: exynos: Add cpufreq driver for exynos5440 cpufreq: AMD "frequency sensitivity feedback" powersave bias for ondemand governor cpufreq: ondemand: allow custom powersave_bias_target handler to be registered cpufreq: convert cpufreq_driver to using RCU cpufreq: powerpc/platforms/cell: move cpufreq driver to drivers/cpufreq cpufreq: sparc: move cpufreq driver to drivers/cpufreq ... Conflicts: MAINTAINERS (with commit a8e39c3 from pm-cpuidle) drivers/cpufreq/cpufreq_governor.h (with commit beb0ff3)
| | * | | cpufreq: tegra: Move driver to drivers/cpufreqViresh Kumar2013-04-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves cpufreq driver of ARM based tegra platform to drivers/cpufreq. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| | * | | cpufreq: Notify all policy->cpus in cpufreq_notify_transition()Viresh Kumar2013-04-02
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | policy->cpus contains all online cpus that have single shared clock line. And their frequencies are always updated together. Many SMP system's cpufreq drivers take care of this in individual drivers but the best place for this code is in cpufreq core. This patch modifies cpufreq_notify_transition() to notify frequency change for all cpus in policy->cpus and hence updates all users of this API. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| * | | ARM: tegra: cpuidle: use init/exit common routine for tegra3Daniel Lezcano2013-04-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the duplicated code and use the cpuidle common code for initialization. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| * | | ARM: tegra: cpuidle: use init/exit common routine for tegra2Daniel Lezcano2013-04-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the duplicated code and use the cpuidle common code for initialization. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| * | | ARM: tegra: cpuidle: use init/exit common routineDaniel Lezcano2013-04-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the duplicated code and use the cpuidle common code for initialization. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| * | | cpuidle: remove en_core_tk_irqen flagDaniel Lezcano2013-04-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The en_core_tk_irqen flag is set in all the cpuidle driver which means it is not necessary to specify this flag. Remove the flag and the code related to it. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Kevin Hilman <khilman@linaro.org> # for mach-omap2/* Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| * | | ARM: tegra: cpuidle: remove useless initializationDaniel Lezcano2013-04-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dev->state_count is initialized automatically by cpuidle_register_device(). When drv->state_count is equal to dev->state_count, no need to init this field, so removing it. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| * | | ARM: tegra2: cpuidle: change driver initializationDaniel Lezcano2013-04-08
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize the idle states directly in the driver structure. That prevents extra structure declaration and memcpy at init time. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* / / arm: tegra: fix Kconfig select clausesFelipe Balbi2013-03-20
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB_ULPI and USB_ULPI_VIEWPORT shouldn't really be selected directly by anyone, but since Tegra still needs some time before turning ulpi viewport into a proper PHY driver, we need to keep the selects in place. This patch just fixes the conditional select so that it will continue to build after merging the latest PHY layer changes. Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* | Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2013-02-21
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM SoC-specific updates from Arnd Bergmann: "This is a larger set of new functionality for the existing SoC families, including: - vt8500 gains support for new CPU cores, notably the Cortex-A9 based wm8850 - prima2 gains support for the "marco" SoC family, its SMP based cousin - tegra gains support for the new Tegra4 (Tegra114) family - socfpga now supports a newer version of the hardware including SMP - i.mx31 and bcm2835 are now using DT probing for their clocks - lots of updates for sh-mobile - OMAP updates for clocks, power management and USB - i.mx6q and tegra now support cpuidle - kirkwood now supports PCIe hot plugging - tegra clock support is updated - tegra USB PHY probing gets implemented diffently" * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (148 commits) ARM: prima2: remove duplicate v7_invalidate_l1 ARM: shmobile: r8a7779: Correct TMU clock support again ARM: prima2: fix __init section for cpu hotplug ARM: OMAP: Consolidate OMAP USB-HS platform data (part 3/3) ARM: OMAP: Consolidate OMAP USB-HS platform data (part 1/3) arm: socfpga: Add SMP support for actual socfpga harware arm: Add v7_invalidate_l1 to cache-v7.S arm: socfpga: Add entries to enable make dtbs socfpga arm: socfpga: Add new device tree source for actual socfpga HW ARM: tegra: sort Kconfig selects for Tegra114 ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114 ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC ARM: tegra: Fix build error for gic update ARM: tegra: remove empty tegra_smp_init_cpus() ARM: shmobile: Register ARM architected timer ARM: MARCO: fix the build issue due to gic-vic-to-irqchip move ARM: shmobile: r8a7779: Correct TMU clock support ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles ARM: mxs: use apbx bus clock to drive the timers on timrotv2 ...
| * \ Merge branch 'socfpga/hw' into next/socOlof Johansson2013-02-11
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From Dinh Nguyen, this is a series of patches introducing support for socfpga hardware (Altera Cyclone5). It also includes a cleanup that moves some of the ARMv7 cache maintenance functions to a common location, since three other platforms aready implemented it separately. * socfpga/hw: arm: socfpga: Add SMP support for actual socfpga harware arm: Add v7_invalidate_l1 to cache-v7.S arm: socfpga: Add entries to enable make dtbs socfpga arm: socfpga: Add new device tree source for actual socfpga HW Trivial conflict in arch/arm/mach-tegra/headsmp.S. Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | arm: Add v7_invalidate_l1 to cache-v7.SDinh Nguyen2013-02-11
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Pavel Machek <pavel@denx.de> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Pavel Machek <pavel@denx.de> Tested-by: Stephen Warren <swarren@nvidia.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Olof Johansson <olof@lixom.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | Merge branch 'tegra/t114' into next/socOlof Johansson2013-02-09
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a couple of fixes sent via email (via Stephen/Hiroshi). * tegra/t114: ARM: tegra: sort Kconfig selects for Tegra114 ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114 ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | ARM: tegra: sort Kconfig selects for Tegra114Stephen Warren2013-02-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig options selected by ARCH_TEGRA_*_SOC were recently sorted. Update the newly added ARCH_TEGRA_114_SOC's select statements to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114Stephen Warren2013-02-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_ARCH_TEGRA_114_SOC doesn't currently enable gpiolib, which causes numerous build problems building a Tegra kernel with only Tegra114 enabled, and not Tegra20 or Tegra30. Enable ARCH_REQUIRE_GPIOLIB to solve this. However, all Tegra will use gpiolib, so select this option from ARCH_TEGRA rather than each individual ARCH_TEGRA_*_SOC, to prevent this problem for any future chips. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOCOlof Johansson2013-02-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the build error when ARCH_TEGRA_114_SOC is enabled and ARCH_TEGRA_3x_SOC is disabled. This provides Tegra114 with its own tegra114_init_early() instead of making use of tegra30_init_early() so that T114 build doesn't depend on T3x anymore. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | ARM: tegra: Fix build error for gic updateHiroshi Doyu2013-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix build error in board-dt-tegra114.c(next-20130204) Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reported-by: Sami Liedes<sliedes@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | ARM: tegra: remove empty tegra_smp_init_cpus()Olof Johansson2013-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on two separate cleanup branches, it's now empty and can be removed. Signed-off-by: Olof Johansson <olof@lixom.net> Cc: Stephen Warren <swarren@wwwdotorg.org>
| * | | Merge tag 'tegra-for-3.9-soc-t114' of ↵Olof Johansson2013-02-05
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stepen Warren: ARM: tegra: add Tegra114 SoC support This pull request adds initial support for the Tegra114 SoC, which integrates a quad-core ARM Cortex-A15 CPU. I'm proud to observe that we posted the initial versions of these patches before the final official announcement of this chip. These patches are enough to boot with a UART-based console, support the Dalmore and Pluto reference/evaluation boards, instantiate the GPIO and pinctrl drivers, and enable a cpuidle state. As yet, no clocks or storage devices are supported, but patches for those will follow shortly. This pull request is based on (most of) the previous pull request with tag tegra-for-3.9-soc-cpuidle, followed by a merge of the previous pull request with tag tegra-for-3.9-scu-base-rework. * tag 'tegra-for-3.9-soc-t114' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (24 commits) ARM: DT: tegra114: add pinmux DT entry ARM: DT: tegra114: add GPIO DT entry ARM: tegra114: select PINCTRL for Tegra114 SoC ARM: tegra: add Tegra114 ARM_CPUIDLE_WFI_STATE support ARM: tegra: Add SMMU entry to Tegra114 DT ARM: tegra: add AHB entry to Tegra114 DT ARM: tegra: Add initial support for Tegra114 SoC. ARM: dt: tegra114: Add new board, Pluto ARM: dt: tegra114: Add new board, Dalmore ARM: dt: tegra114: Add new SoC base, Tegra114 SoC ARM: tegra: fuse: Add chip ID Tegra114 0x35 ARM: OMAP: Make use of available scu_a9_get_base() interface ARM: tegra: Skip scu_enable(scu_base) if not Cortex A9 ARM: Add API to detect SCU base address from CP15 ARM: tegra: Use DT /cpu node to detect number of CPU core ARM: tegra: Add CPU nodes to Tegra30 device tree ARM: tegra: Add CPU nodes to Tegra20 device tree ARM: perf: simplify __hw_perf_event_init err handling ARM: perf: remove unnecessary checks for idx < 0 ARM: perf: handle armpmu_register failing ... Signed-off-by: Olof Johansson <olof@lixom.net> Remove/add conflict in arch/arm/mach-tegra/common.c resolved. Remove/remove conflict in arch/arm/mach-tegra/platsmp.c. Leave the empty stub function for now since removing it in the merge commit is confusing; will be cleaned up in a separate commit. # # It looks like you may be committing a merge. # If this is not correct, please remove the file # .git/MERGE_HEAD # and try again.
| | * | ARM: tegra114: select PINCTRL for Tegra114 SoCLaxman Dewangan2013-01-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Select PINCTRL and PINCTRL_TEGRA114 for enabling Tegra114 pincontrol driver for Tegra114 SoC. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | ARM: tegra: add Tegra114 ARM_CPUIDLE_WFI_STATE supportJoseph Lo2013-01-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding the generic ARM_CPUIDLE_WFI_STATE support for Tegra114. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | ARM: tegra: Add initial support for Tegra114 SoC.Hiroshi Doyu2013-01-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new Tegra 114 SoC support. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | ARM: tegra: fuse: Add chip ID Tegra114 0x35Hiroshi Doyu2013-01-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add tegra_chip_id TEGRA114 0x35 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | Merge branch 'for-3.9/scu-base-rework' into for-3.9/soc-t114Stephen Warren2013-01-28
| | |\ \ | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-tegra/platsmp.c
| | | * | ARM: tegra: Skip scu_enable(scu_base) if not Cortex A9Hiroshi Doyu2013-01-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Skip scu_enable(scu_base) if CPU is not Cortex A9 with SCU. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | | * | ARM: tegra: Use DT /cpu node to detect number of CPU coreHiroshi Doyu2013-01-28
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SCU based detection only works with Cortex-A9 MP and it doesn't support ones with multiple clusters. The only way to detect number of CPU core correctly is with DT /cpu node. Tegra SoCs decided to use DT detection as the only way and to not use SCU based detection at all. Even if DT /cpu node based detection fails, it continues with a single core Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | Merge tag 'tegra-for-3.9-soc-cpuidle' of ↵Olof Johansson2013-02-05
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stephen Warren: ARM: tegra: cpuidle enhancements This pull request implements a new "LP2" cpuidle state for Tegra20, which makes use of the couple cpuidle feature. It is based on (most of) the previous pull request, with tag tegra-for-3.9-soc-usb. * tag 'tegra-for-3.9-soc-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exit clk: tegra20: Implementing CPU low-power function for tegra_cpu_car_ops ARM: tegra20: cpuidle: add powered-down state for secondary CPU ARM: tegra: add pending SGI checking API Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down modeJoseph Lo2013-01-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one core to go into this mode before other core. The coupled cpuidle framework can help to sync the MPCore to coupled state then go into "powered-down" idle mode together. The driver can just assume the MPCore come into "powered-down" mode at the same time. No need to take care if the CPU_0 goes into this mode along and only can put it into safe idle mode (WFI). The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI for waiting CPU0 in the same state. When the CPU0 requests powered-down state, it attempts to put the secondary CPU into reset to prevent it from waking up. Then power down both CPUs together and power off the cpu rail. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exitJoseph Lo2013-01-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The flow controller can help CPU to go into suspend mode (powered-down state). When CPU go into powered-down state, it needs some careful settings before getting into and after leaving. The enter and exit functions do that by configuring appropriate mode for flow controller. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | ARM: tegra20: cpuidle: add powered-down state for secondary CPUJoseph Lo2013-01-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | ARM: tegra: add pending SGI checking APIJoseph Lo2013-01-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it include the power of GIC. That caused the SGI (Software Generated Interrupt) been lost. Because the SGI can't wake up the CPU that in the "powered-down" CPU idle mode. We need to check if there is any pending SGI when go into "powered-down" CPU idle mode. This is important especially when applying the coupled cpuidle framework into "power-down" cpuidle dirver. Because the coupled cpuidle framework may have the chance that misses IPI_SINGLE_FUNC handling sometimes. For the PPI or SPI, something like the legacy peripheral interrupt. It still can be maintained by Tegra legacy interrupt controller. If there is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The CPU can be woken up immediately. So we don't need to take care the same situation for PPI or SPI. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | Merge tag 'tegra-for-3.9-soc-usb' of ↵Olof Johansson2013-02-05
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stephen Warren: ARM: tegra: USB driver cleanup The Tegra USB driver has a number of issues: 1) The PHY driver isn't a true platform device, and doesn't implement the standard USB PHY API. 2) struct device instance numbers were used to make decisions in the driver, rather than being parameterized by DT or platform data. This pull request solves issue (2), and lays the groundwork for solving issue (1). The work on issue (1) involved introducing new DT nodes for the USB PHYs, which in turn interacted with the Tegra common clock framework changes, due to the move of clock lookups into device tree. Hence, these USB driver changes are taken through the Tegra tree with acks from USB maintainers. This pull request is based on the previous pull request, with tag tegra-for-3.9-soc-ccf. * tag 'tegra-for-3.9-soc-usb' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: usb: host: tegra: make use of PHY pointer of HCD ARM: tegra: Add reset GPIO information to PHY DT node usb: host: tegra: don't touch EMC clock usb: add APIs to access host registers from Tegra PHY USB: PHY: tegra: Get rid of instance number to differentiate PHY type USB: PHY: tegra: get rid of instance number to differentiate legacy controller ARM: tegra: add clocks properties to USB PHY nodes ARM: tegra: add DT nodes for Tegra USB PHY usb: phy: remove unused APIs from Tegra PHY. usb: host: tegra: Resetting PORT0 based on information received via DT. ARM: tegra: Add new DT property to USB node. usb: phy: use kzalloc to allocate struct tegra_usb_phy ARM: tegra: remove USB address related macros from iomap.h
| | * | ARM: tegra: remove USB address related macros from iomap.hVenu Byravarasu2013-01-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB register base address and sizes defined in iomap.h are not used in any files other than board-dt-tegra20.c. Hence removed those defines from header file and using the absolute values in board files. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | Merge tag 'tegra-for-3.9-soc-ccf' of ↵Olof Johansson2013-02-05
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stephen Warren: ARM: tegra: Common Clock Framework rework Tegra already supports the common clock framework, but had issues: 1) The clock driver was located in arch/arm/mach-tegra/ rather than drivers/clk/. 2) A single "Tegra clock" type was implemented, rather than separate clock types for PLL, mux, divider, ... type in HW. 3) Clock lookups by device drivers were still driven by device name and connection ID, rather than through device tree. This pull request solves all three issues. This required some DT changes to add clocks properties, and driver changes to request clocks more "correctly". Finally, this rework allows all AUXDATA to be removed from Tegra board files, and various duplicate clock lookup entries to be removed from the driver. This pull request is based on the previous pull request, with tag tegra-for-3.9-cleanup. * tag 'tegra-for-3.9-soc-ccf' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (31 commits) clk: tegra30: remove unused TEGRA_CLK_DUPLICATE()s clk: tegra20: remove unused TEGRA_CLK_DUPLICATE()s ARM: tegra30: remove auxdata ARM: tegra20: remove auxdata ASoC: tegra: remove auxdata staging: nvec: remove use of clk_get_sys ARM: tegra: paz00: add clock information to DT ARM: tegra: add clock properties to Tegra30 DT ARM: tegra: add clock properties to Tegra20 DT spi: tegra: do not use clock name to get clock ARM: tegra: remove legacy clock code ARM: tegra: migrate to new clock code clk: tegra: add clock support for Tegra30 clk: tegra: add clock support for Tegra20 clk: tegra: add Tegra specific clocks ARM: tegra: define Tegra30 CAR binding ARM: tegra: define Tegra20 CAR binding ARM: tegra: move tegra_cpu_car.h to linux/clk/tegra.h ARM: tegra: add function to read chipid ARM: tegra: fix compile error when disable CPU_IDLE ... Signed-off-by: Olof Johansson <olof@lixom.net> Conflicts: arch/arm/mach-tegra/board-dt-tegra20.c arch/arm/mach-tegra/board-dt-tegra30.c arch/arm/mach-tegra/common.c arch/arm/mach-tegra/platsmp.c drivers/clocksource/Makefile
| | * | ARM: tegra30: remove auxdataPrashant Gaikwad2013-01-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove AUXDATA as clocks are initialized from device node. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | ARM: tegra20: remove auxdataPrashant Gaikwad2013-01-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove AUXDATA as clock are initialized from device node. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | ARM: tegra: remove legacy clock codePrashant Gaikwad2013-01-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove all legacy clock code from mach-tegra. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>