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* ENGR00299323-11 ARM: imx: Add i.mx6sx enet clk supportFugang Duan2014-04-16
| | | | | | | | | Add i.mx6sx enet clk support: - Add enet2 refrence clock. - Add PTP clock. - Set enet system AHB clock to 200Mh. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00299323-10 net:fec: add enet AVB Ubuntu Gstreamer demo supportFugang Duan2014-04-16
| | | | | | | | | | | | | | | | | | | | Support Gstreamer AVB demo support. ring1 -> ClassA, ring2 -> ClassB, ring0 -> Best Effort For QoS: ring1 > ring2 > ring0 For bandwidth reverse: 50% bandwidth -> ClassA 33% bandwidth -> ClassB 17% bandwidth -> Best effort queue In general, ClassA run audio, ClassB run video. Since AVB demo use big bandwidth streaming, video cost more than 33Mbps bandwidth, and with Qos limitation: ClassA >= ClassB > Best effort, so we have to change ring2 bandwidth equal to ring1 bandwidth (50%). After validate on FPGA, AVB demo can work fine for audio and video. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00299323-9 net:fec: add enet-avb interrupt coalescence feature supportFugang Duan2014-04-16
| | | | | | | | | | | | | | | Add enet-avb interrupt coalescence feature support. By default, init the interrupt coalescing frame count threshold and timer threshold. Supply the ethtool interfaces as below for user tuning to improve enet performance: rx_max_coalesced_frames rx_coalesce_usecs tx_max_coalesced_frames tx_coalesce_usecs Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00299323-8 net:fec: change FEC alignment to 64 bytes for ARM platformFugang Duan2014-04-16
| | | | | | | | | | Since enet-avb has 64 bytes alignment limitation for rx DMA transfer. The previous enet IP for ARM platform has 16 bytes alignment for tx DMA transfer. 64 is the an integral number of 16, so change alignment to 64 bytes for all ARM platform, which don't impact the performance of previous platform. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00299323-7 net:fec: Add more compatible stringsFugang Duan2014-04-16
| | | | | | Add compatible string "fsl,imx6sx-fec" for i.MX6SX. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00299323-6 net:fec: add enet-avb IP supportFugang Duan2014-04-16
| | | | | | | | | | | | | | | i.MX6SX Enet-AVB support 3 tx queues, 3 rx queues. For tx queues: ring 0 -> best effort ring 1 -> Class A ring 2 -> Class B For rx queues: ring 0 -> best effort ring 1 -> receive VLAN packet with classification match ring 2 -> receive VLAN packet with classification match Add enet-avb IP multiqueue support for the driver. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00299323-5 net:fec: Disable enet-avb MAC instead of reset MACFugang Duan2014-04-16
| | | | | | | | For i.MX6SX enet use AXI bus, reset MAC will make system bus dead if ENET-AXI bus has pending access (AHB bus should not have such issue). So, disable enet with AVB MAC instead of reset MAC itself. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00299323-4 net:fec: add multiqueue supportFugang Duan2014-04-16
| | | | | | | | | | | | | | | | | | | Add multiqueue support, which is compatible with previous single queue driver for FEC/ENET IPs. By default, the tx/rx queue number is 1, user can config the queue number at DTS file like this: fsl,num_tx_queues=<3>; fsl,num_rx_queues=<3>; Ethernet multiqueue mechanism can improve performance in SMP system. For single hw queue, multiqueue can balance cpu loading. For multi hw queues, multiple cores can process network packets in parallel, and refer the article for the detail advantage for multiqueue: http://vger.kernel.org/~davem/davem_nyc09.pdf Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Frank Li<frank.li@freescale.com>
* ENGR00299323-3 net:fec: use multiqueue interface to allocate Ethernet deviceFugang Duan2014-04-16
| | | | | | | Since i.MX6SX enet-AVB IP support multi queues, so use multi queues interface to allocate and set up an Ethernet device. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00299323-2 net:fec: add enet AVB feature macro define for imx6sxFugang Duan2014-04-16
| | | | | | Add enet AVB feature macro define for imx6sx. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00299323-1 net:fec: add enet refrence clockFugang Duan2014-04-16
| | | | | | | | | | | | | | | | | | | i.MX6sx enet has below clocks for user config: clk_ipg: ipg_clk_s, ipg_clk_mac0_s, 66Mhz clk_ahb: enet system clock, it is enet AXI clock for imx6sx. For imx6sx, it alos is the clock source of interrupt coalescing. The clock range: 200Mhz ~ 266Mhz. clk_ref: refrence clock for tx and rx. For imx6sx enet RGMII mode, the refrence clock is 125Mhz coming from internal PLL or external. In i.MX6sx-arm2 board, the clock is from internal PLL. clk_ref is optional, depends on board. clk_enet_out: The clock can be output from internal PLL. It can supply 50Mhz clock for phy. clk_enet_out is optional, depends on chip and board. clk_ptp: 1588 ts clock. It is optional, depends on chip. The patch add clk_ref to distiguish the different clocks. Signed-off-by: Fugang Duan <B38611@freescale.com>
* mtd: m25p80: Use positive logic to check JEDEC IDAxel Lin2014-04-16
| | | | | | | | For slightly better readability. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: delete non-required instances of include <linux/init.h>Paul Gortmaker2014-04-16
| | | | | | | | | | | | | | | None of these files are actually using any __init type directives and hence don't need to include <linux/init.h>. Most are just a left over from __devinit and __cpuinit removal, or simply due to code getting copied from one driver to the next. Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: linux-mtd@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> [Brian: dropped one incorrect hunk] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: Enable Dual SPI read transfers for s25fl256s1 and s25fl512sGeert Uytterhoeven2014-04-16
| | | | | | | | | Spansion s25fl256s1 and s25fl512s support Dual SPI transfers, hence set the M25P80_DUAL_READ flag. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: Add dual read supportGeert Uytterhoeven2014-04-16
| | | | | | | | | | Add support for Dual SPI read transfers, which is supported by some Spansion SPI FLASHes. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: Set rx_nbits for Quad SPI transfersGeert Uytterhoeven2014-04-16
| | | | | | | | | | | | | | | When using the Quad Read opcode, SPI masters still use Single SPI transfers, as spi_transfer.rx_nbits defaults to SPI_NBITS_SINGLE. Use SPI_NBITS_QUAD to fix this. While an earlier version of commit 3487a63955c34ea508bcf4ca5131ddd953876e2d ("drivers: mtd: m25p80: add quad read support") did this correctly, it was forgotten in the version that got merged. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: Enable Quad SPI read transfers for s25fl512sGeert Uytterhoeven2014-04-16
| | | | | | | | | | Spansion s25fl512s supports Quad SPI transfers, hence set the M25P80_QUAD_READ flag. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: assign default read commandBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | | In the following commit (in -next): commit 8552b439aba7f32063755d23f79ca27b4d0a3115 drivers: mtd: m25p80: convert "bool" read check into an enum We converted the boolean 'fast_read' property to become an enum 'flash_read', but at the same time, we changed the conditional path so that it doesn't choose a default value in some cases (technically, we choose the correct default simply by virtue of devm_kzalloc(), which zeroes this out to be a NORMAL read operation, but still...). Fix this by setting a default for the 'else' clause. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Sourav Poddar <sourav.poddar@ti.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: Use OPCODE_QUAD_READ_4B for 4-byte addressingGeert Uytterhoeven2014-04-16
| | | | | | | | | | | | | | commit 3487a63955c34ea508bcf4ca5131ddd953876e2d ("drivers: mtd: m25p80: add quad read support") in -next added both the 3-byte OPCODE_QUAD_READ and the 4-byte OPCODE_QUAD_READ_4B, but incorrectly uses OPCODE_QUAD_READ for both 3-byte and 4-byte addressing. Use OPCODE_QUAD_READ_4B in the 4-byte case to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: add support for m25px16Igor Grinberg2014-04-16
| | | | | | | | Add support for Micron m25px16 spi flash chip. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* drivers: mtd: m25p80: add quad read supportSourav Poddar2014-04-16
| | | | | | | | | | | | | | | | Some flash also support quad read mode. Adding support for quad read mode in m25p80 for Spansion and Macronix flash. [Tweaked by Brian] With this patch, quad-read support will override fast-read and normal-read, if the SPI controller and flash chip both support it. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* drivers: mtd: m25p80: convert "bool" read check into an enumSourav Poddar2014-04-16
| | | | | | | | | | This is a cleanup prior to adding quad read support. This will facilitate easy addition of more read commands check under an enum rather that defining a separate bool for it. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: fixup device removal failure pathBrian Norris2014-04-16
| | | | | | | | Device removal should fail if MTD unregistration fails. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: add support for Macronix mx25l3255eBrian Norris2014-04-16
| | | | | | | | A new 32Mbit SPI NOR flash from Macronix. Nothing special. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: remove 'disabled' device checkBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | | | | It seems like the following commit was never necessary commit 5f949137952020214cd167093dd7be448f21c079 Author: Shaohui Xie <Shaohui.Xie@freescale.com> Date: Fri Oct 14 15:49:00 2011 +0800 mtd: m25p80: don't probe device which has status of 'disabled' because it duplicates the code in of_platform_device_create_pdata() which ensures that 'disabled' nodes are never instantiated. Also, drop the __maybe_unused. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: <devicetree@vger.kernel.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: remove M25PXX_USE_FAST_READ KconfigBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the compile-time option for FAST_READ, since we have run-time support for detecting it. This refactors the logic for enabling fast-read, such that for DT-enabled devices, we honor the "m25p,fast-read" property but for non-DT devices, we default to using FAST_READ whenever the flash device supports it. Normal READ and FAST_READ differ only in the following: * FAST_READ supports SPI higher clock frequencies [1] * number of dummy cycles; FAST_READ requires 8 dummy cycles (whereas READ requires 0) to allow the flash sufficient setup time, even when running at higher clock speeds Thus, for flash chips which support FAST_READ, there is otherwise no limiting reason why we cannot use the FAST_READ opcode instead of READ. It simply allows the SPI controller to run at higher clock rates. So theoretically, nobody should be needing the compile-time option anyway. [1] I have a Spansion S25FL128S datasheet which says: "The maximum operating clock frequency for the READ command is 50 MHz." And: "The maximum operating clock frequency for FAST READ command is 133 MHz." Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: re-align ID entriesBrian Norris2014-04-16
| | | | | | | | No change in the table data. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: remove obsolete FIXMEBrian Norris2014-04-16
| | | | | | | | | The FIXME and NOTE have already been fixed (we have FAST_READ support). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Sourav Poddar <sourav.poddar@ti.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: fix allocation sizeBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | This patch fixes two memory errors: 1. During a probe failure (in mtd_device_parse_register?) the command buffer would not be freed. 2. The command buffer's size is determined based on the 'fast_read' boolean, but the assignment of fast_read is made after this allocation. Thus, the buffer may be allocated "too small". To fix the first, just switch to the devres version of kzalloc. To fix the second, increase MAX_CMD_SIZE unconditionally. It's not worth saving a byte to fiddle around with the conditions here. This problem was reported by Yuhang Wang a while back. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reported-by: Yuhang Wang <wangyuhang2014@gmail.com> Reviewed-by: Sourav Poddar <sourav.poddar@ti.com> Cc: <stable@vger.kernel.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: Add support for Micron N25Q512A memoryPriyanka Jain2014-04-16
| | | | | | | | | | | | | Micron N25Q512A is a spi flash memory with following features: -64MB size, 1.8V, Mulitple I/O, 4KB Sector erase memory. -Memory is organised as 1024(64KB) main sectors. -Each sector is divided into 256 pages. -Register set/Opcodes are similar to other N25Q family products. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: Add support for ESMT F25L32PAFlavio Silveira2014-04-16
| | | | | | | | | | | | | | This flashchip is used in D-Link DIR-610 A1 router board and maybe several others, yet is not kernel upstream. So add support for it according to datasheet [0], making it easier to support other boards using this flashchip in the future. [0] http://www.esmt.com.tw/DB/manager/upload/F25L32PA.pdf Signed-off-by: Flavio Silveira <fggs@terra.com.br> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: Fix 4 byte addressing mode for Micron devices.Elie De Brauwer2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | According to the datasheet for Micron n25q256a (N25Q256A13ESF40F) 4-byte addressing mode should be entered as follows: <quote> To enter or exit the 4-byte address mode, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. (Note: The WRITE ENABLE command must NOT be executed on the N25Q256A83ESF40x and N25Q256A83E1240x devices.) S# must be driven LOW. The effect of the command is immediate; after the command has been executed, the write enable latch bit is cleared to 0. </quote> Micron's portable way to perform this for all types of Micron flash is to first issue a write enable, then switch the addressing mode followed by a write disable to avoid leaving the flash in a write- able state. Signed-off-by: Elie De Brauwer <eliedebrauwer@email.com> [Brian: reworked a bit] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: chips: Add support for PMC SPI Flash chips in m25p80.cMichel Stempin2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for PMC (now Chingis, part of ISSI) Pm25LV512 (512 Kib), Pm25LV010 (1 Mib) and Pm25LQ032 (32 Mib) SPI Flash chips. This patch addresses two generations of PMC SPI Flash chips: - Pm25LV512 and Pm25LV010: these have 4KiB sectors and 32KiB blocks. The 4KiB sector erase uses a non-standard opcode (0xd7). They do not support JEDEC RDID (0x9f), and so they can only be detected by matching their name string with pre-configured platform data. Because of the cascaded acquisitions, the datasheet is no longer available on the current manufacturer's website, although it is still commonly used in some recent wireless routers (<https://forum.openwrt.org/viewtopic.php?pid=186360#p186360>). The only public datasheet available seems to be on GeoCities: <http://www.geocities.jp/scottle556/pdf/Pm25LV512-010.pdf> - Pm25LQ032: a newer generation flash, with 4KiB sectors and 64KiB blocks. It uses the standard erase and JEDEC read-ID opcodes. Manufacturer's datasheet is here: <http://www.chingistek.com/img/Product_Files/Pm25LQ032C%20datasheet%20v1.6.1.pdf> This patch is resent in order to take into account both Brian Norris remarks and this upstream patch: commit e534ee4f9ca29fdb38eea4b0c53f2154fbd8c1ee Author: Krzysztof Mazur <krzysiek@podlesie.net> Date: Fri Feb 22 15:51:05 2013 +0100 mtd: m25p80: introduce SST_WRITE flag for SST byte programming Not all SST devices implement the SST byte programming command. Some devices (like SST25VF064C) implement only standard m25p80 page write command. Now SPI flash devices that need sst_write() are explicitly marked with new SST_WRITE flag and the decision to use sst_write() is based on this flag instead of manufacturer id. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Michel Stempin <michel.stempin@wanadoo.fr> [Brian: fixed conflict] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: add support for mr25h10Markus Niebel2014-04-16
| | | | | | | | | | | | This adds support for the Everspin mr25h10 MRAM chip to the m25p80 driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: make CONFIG_M25PXX_USE_FAST_READ safe to enableSascha Hauer2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds a flag to struct flash_info indicating that fast_read is not supported. This now gives the following logic when determing whether to enable fastread: If the flash chip does not support fast_read, then disable it. Otherwise: 1) enable fast_read if device node contains m25p,fast-read 2) enable fast_read if forced in Kconfig This makes enabling CONFIG_M25PXX_USE_FAST_READ a safe option since we no longer enable the fast_read option unconditionally. For now fast_read is disabled for the everspin mr25h256 and the catalyst devices. Others may need the flag aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: Pass flags through CAT25_INFO macroSascha Hauer2014-04-16
| | | | | | | | | | | | The flags may have to be overwritten, so add them to the CAT25_INFO macro. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: remove unnecessary ifdefSascha Hauer2014-04-16
| | | | | | | | | | | | of_property_read_bool properly compiles away, no need to ifdef this for non DT builds. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: Micron SPI uses Macronix-style 4-byte addressingBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For SPI NOR flash that are larger than 128Mbit (16MiB), we need 4 bytes of address space to reach the entire flash; however, the original SPI flash protocol used only 3 bytes for the address. So far, the practice for handling this has been either to use new command opcodes that are defined to use 4 bytes for their address, or to use special mode-switching command to configure all traditionally-3-byte-address commands to take 4 bytes instead. Macronix and Spansion developed two incompatible methods for entering/exiting "4-byte address mode." Micron flash uses the Macronix method (OPCODE_{EN4B,EX4B}), not the Spansion method. This patch solves addressing issues on Micron n25q256a and provides the ability to support other future Micron SPI flash >16MiB. Quoting a Micron representative: "Majority of our NOR that needs 4-byte addressing (256Mb or 32MB and higher) enter and exit 4byte through B7h and E9h commands. The N25Q256A7xxx and N25Q512A7xxx parts do not support 4-byte addressing mode via B7h or E9h command." They further clarified that those that don't support the enter/exit opcodes (B7h/E9h) are manufactured specifically to come up by default in 4-byte mode. We don't need to treat those parts any diffently, as they will discard the EN4B opcode as a no-op. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: devices: use dev_get_platdata()Jingoo Han2014-04-16
| | | | | | | | | | Use the wrapper function for retrieving the platform data instead of accessing dev->platform_data directly. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: devices: added the 16MiB winbond deviceGirish K S2014-04-16
| | | | | | | | | | Added a 16MiB winbond devce to the device list erase size = 64KiB and number of blocks = 256. Signed-off-by: Girish K S <ks.giri@samsung.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: correct EN4B/EX4B commentBrian Norris2014-04-16
| | | | | | | Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: utilize dedicated 4-byte addressing commandsBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Traditionally, the command set used by SPI flash only supported a 3-byte address. However, large SPI flash (>= 32MiB, or 256Mib) require 4 bytes to address the entire flash. Most manufacturers have supplied a mode switch (via a "bank register writer", or a "enable 4-byte mode" command), which tells the flash to expect 4 address cycles from now on, instead of 3. This mode remains until power is cut, the reset line is triggered (on packages where present), or a command is sent to reset the flash or to reset the 3-byte addressing mode. As an alternative, some flash manufacturers have developed a new command set that accept a full 4-byte address. They can be used orthogonally to any of the modes; that is, they can be used when the flash is in either 3-byte or 4-byte address mode. Now, there are a number of reasons why the "stateful" 4-byte address mode switch may not be acceptable. For instance, some SoC's perform a dumb boot sequence in which they only send 3-byte read commands to the flash. However, if an unexpected reset occurs, the flash chip cannot be guaranteed to return to its 3-byte mode. Thus, the SoC controller and flash will not understand each other. (One might consider hooking up the aforementioned reset pin to the system reset line so that any system reset will reset the flash to 3-byte mode, but some packages do not provide this pin. And in some other packages, one must choose between having a reset pin and having enough pins for 4-output QSPI support. It is an error prone process choosing a flash that will support a hardware reset pin!) This patch provides support for the new stateless command set, so that we can avoid the problems that come with a stateful addressing mode change. The flash can be left in "3-byte mode" while still accessing the entire flash. Note that Spansion supports this command set on all its large flash (e.g, S25FL512S), and Macronix has begun supporting this command set on some new flash (e.g., MX25L25635F). For the moment, I don't know how to differentiate the Macronix that don't support this command set (e.g., MX25L25635E) from those that do, so this patch only supports Spansion. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: m25p80: use spi_get_drvdata() and spi_set_drvdata()Jingoo Han2014-04-16
| | | | | | | | | | | Use the wrapper functions for getting and setting the driver data using spi_device instead of using dev_{get|set}_drvdata with &spi->dev, so we can directly pass a struct spi_device. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* serial: imx: always wake up the processes in the TX callbackHuang Shijie2014-04-16
| | | | | | | | | | | | | The current code only wakes up the processes when the circle buffer has less data then the WAKEUP_CHARS. But sometimes, the circle buffer may has data more then the WAKEUP_CHARS, in such case, the processes will hang. This patch makes it always wakes up the processes in the TX callback. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ENGR00298631 PXP: remove pxp_hw_init() when do pxp probeFancy Fang2014-04-16
| | | | | | | | Since the pxp registers have been already set to default values after hardware reset, it is not necessary to re-initialize them again. And this can accelerate the system booting procedure. Signed-off-by: Fancy Fang <chen.fang@freescale.com>
* ENGR00298338 PXP: fix hang issue due to read pxp reg when clk disabledFancy Fang2014-04-16
| | | | | | | | The function dump_pxp_reg() may be called when the pxp clock is disabled. So this will cause system hang issue. Now add clock enable/disable pair to this function call. Signed-off-by: Fancy Fang <chen.fang@freescale.com>
* ENGR00298315 PXP: PXP registers should be reset to default after each task ↵Fancy Fang2014-04-16
| | | | | | | | | | finished The PXP registers should be cleared to its default values after each task done to avoid affecting the other later tasks status. And PXP CTRL register provide a SFTRST bit to do this on hardware level. Signed-off-by: Fancy Fang <chen.fang@freescale.com>
* ENGR00298392 pcie: imx pcie ep rc msi demoRichard Zhu2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add one imx pcie ep simple skeleton driver to demo the msi trigger capability in imx6 pcie rc/ep validation system - in order to avoid the modification of common codes, force the msi address to be 0x01ff8000 Test howto: - Enable CONFIG_PCI_MSI=y, when rebuild the rc/ep images - EP side(console command and kernel message): root@sabresd_6dq:/ # memtool 0x1ff8000=0 Writing 32-bit value 0x0 to address 0x01FF8000 root@sabresd_6dq:/ # - RC side(console command and kernel message): root@sabresd_6dq:/ # cat /proc/interrupts | grep MSI 384: 1 0 0 0 PCI-MSI - EP side(console command and kernel message): root@sabresd_6dq:/ # memtool 0x1ff8000=0 Writing 32-bit value 0x0 to address 0x01FF8000 - RC side(console command and kernel message): root@sabresd_6dq:/ # cat /proc/interrupts | grep MSI 384: 2 0 0 0 PCI-MSI Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00298389 pcie: let rc can access mem of epRichard Zhu2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - setup one new outbound memory region at rc side, used to let imx6 pcie rc can access the memory of imx6 pcie ep in imx6 pcie rc ep validation system. - set the default address of the ddr memory to be 0x4000_0000 NOTE: - default address 0x4000_0000 of ep side would be accessed in this demo. Test howto: step1: EP side: 1.1: echo 0x40000000 > /sys/devices/soc0/soc.1/1ffc000.pcie/ep_bar0_addr 1.2: memtool -32 0x40000000 4 E Reading 0x4 count starting at address 0x40000000 0x40000000: 6FE9E9F6 7583FBB9 39EAEFEA FBDCFD78 step2: RC side: memtool -32 0x01000000=58D454DA memtool -32 0x01000004=7332095B step3: EP side: memtool -32 0x40000000 4 E Reading 0x4 count starting at address 0x40000000 0x40000000: 58D454DA 7332095B 39EAEFEA FBDCFD78 Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00298524-6 ARM: imx: enable suspend/resume for i.mx6sxAnson Huang2014-04-16
| | | | | | | | | | | | | | | Enable suspend/resume feature for i.mx6sx 17x17 arm2 board, for dsm mode, as we use dedicated ocram space for low power function(start from 0x8f8000), but ROM code still use previous ocram space(0x900000) for checking jump address, so we need to enable ROMCP of data patch to workaround this issue. This patch only enables the suspend/resume function, will add low power related operation such as DDR IO HZ mode setting later, as there is still some necessary reference manual missing. Signed-off-by: Anson Huang <b20788@freescale.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-19 20:20:03 -0400