aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAge
...
* clk: clk-divider: Export clk_register_divider()Fabio Estevam2014-04-16
| | | | | | | | | | | | clk_register_divider() needs to be exported so that it could be used in a module driver, otherwise we get the following error: ERROR: "clk_register_divider" [sound/soc/mxs/snd-soc-mxs.ko] undefined! Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: also export clk_register_divider_table] Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: divider: add CLK_DIVIDER_HIWORD_MASK flagHaojian Zhuang2014-04-16
| | | | | | | | | | | | | | | | In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as setting divider, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds divider flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: fix new_parent dereference before null checkJames Hogan2014-04-16
| | | | | | | | | | | | | | | | Commit 71472c0 (clk: add support for clock reparent on set_rate) added a dereference of the new_parent pointer in clk_reparent(), but as detected by smatch clk_reparent() later checks whether new_parent is NULL. The dereference was in order to clear the new parent's new_child pointer to avoid duplicate POST_RATE_CHANGE notifications, so clearly isn't necessary if the new parent is NULL, so move it inside the "if (new_parent)" block. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: get matching entry under lock in of_clk_init()Alex Elder2014-04-16
| | | | | | | | | | | | | | | | | | | | Currently of_clk_init() finds a matching device node while holding the device tree spinlock. When a matching device node is found, the lock is dropped and then re-acquired in order to get a reference to the matching device id structure. Acquiring the spinlock twice is unnecessary (and it opens a vulnerable window that could conceivably lead to errors). There already exists an interface for both finding and taking a reference to a device id under lock, so use it. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Christian Daudt <csd@broadcom.com> Reviewed-by: Markus Mayer <markus.mayer@linaro.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: handle NULL struct clk gracefullyMike Turquette2014-04-16
| | | | | | | | | | | At some point changes to clk_set_rate and clk_set_parent introduced a bug whereby NULL struct clk pointers were treated as an error. This is in violation of the API in include/linux/clk.h. Reintroduce graceful handling of NULL clk's by bailing from clk_set_rate and clk_set_parent with return codes of zero. Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: clk-mux: implement remuxing on set_rateJames Hogan2014-04-16
| | | | | | | | | | | | | | | | | Implement clk-mux remuxing if the CLK_SET_RATE_NO_REPARENT flag isn't set. This implements determine_rate for clk-mux to propagate to each parent and to choose the best one (like clk-divider this chooses the parent which provides the fastest rate <= the requested rate). The determine_rate op is implemented as a core helper function so that it can be easily used by more complex clocks which incorporate muxes. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes being reparented during clk_set_rate. To avoid breaking existing platforms, all callers of clk_register_mux() are adjusted to pass the new flag. Platform maintainers are encouraged to remove the flag if they wish to allow mux reparenting on set_rate. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Chao Xie <xiechao.mail@gmail.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Andrew Chew <achew@nvidia.com> Cc: Doug Anderson <dianders@chromium.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Tomasz Figa <t.figa@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: spear-devel@list.st.com Cc: linux-tegra@vger.kernel.org Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> [tegra] Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi] Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq] Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: add support for clock reparent on set_rateJames Hogan2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add core support to allow clock implementations to select the best parent clock when rounding a rate, e.g. the one which can provide the closest clock rate to that requested. This is by way of adding a new clock op, determine_rate(), which is like round_rate() but has an extra parameter to allow the clock implementation to optionally select a different parent clock. The core then takes care of reparenting the clock when setting the rate. The parent change takes place with the help of some new private data members. struct clk::new_parent specifies a clock's new parent (NULL indicates no change), and struct clk::new_child specifies a clock's new child (whose new_parent member points back to it). The purpose of these are to allow correct walking of the future tree for notifications prior to actually reparenting any clocks, specifically to skip child clocks who are being reparented to another clock (they will be notified via the new parent), and to include any new child clock. These pointers are set by clk_calc_subtree(), and the new_child pointer gets cleared when a child is actually reparented to avoid duplicate POST_RATE_CHANGE notifications. Each place where round_rate() is called, determine_rate() is checked first and called in preference. This restructures a few of the call sites to simplify the logic into if/else blocks. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: move some parent related functions upwardsJames Hogan2014-04-16
| | | | | | | | | | | | | | | Move some parent related functions up in clk.c so they can be used by the modifications in the following patch which enables clock reparenting during set_rate. No other changes are made so this patch makes no functional difference in isolation. This is separate from the following patch primarily to ease readability of that patch. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: Disable unused clocks after deferred probing is doneSaravana Kannan2014-04-16
| | | | | | | | | | | With deferred probing, late_initcall() is too soon to declare a clock as unused. Wait for deferred probing to finish before declaring a clock as unused. Since deferred probing is done in late_initcall(), do the unused check to late_initcall_sync. Signed-off-by: Saravana Kannan <skannan@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: Fix race condition between clk_set_parent and clk_enable()Saravana Kannan2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this patch, the following race condition is possible. * clk-A has two parents - clk-X and clk-Y. * All three are disabled and clk-X is current parent. * Thread A: clk_set_parent(clk-A, clk-Y). * Thread A: <snip execution flow> * Thread A: Grabs enable lock. * Thread A: Sees enable count of clk-A is 0, so doesn't enable clk-Y. * Thread A: Updates clk-A SW parent to clk-Y * Thread A: Releases enable lock. * Thread B: clk_enable(clk-A). * Thread B: clk_enable() enables clk-Y, then enabled clk-A and returns. clk-A is now enabled in software, but not clocking in hardware since the hardware parent is still clk-X. The only way to avoid race conditions between clk_set_parent() and clk_enable/disable() is to ensure that clk_enable/disable() calls don't require changes to hardware enable state between changes to software clock topology and hardware clock topology. The options to achieve the above are: 1. Grab the enable lock before changing software/hardware topology and release it afterwards. 2. Keep the clock enabled for the duration of software/hardware topology change so that any additional enable/disable calls don't try to change the hardware state. Once the topology change is complete, the clock can be put back in its original enable state. Option (1) is not an acceptable solution since the set_parent() ops might need to sleep. Therefore, this patch implements option (2). This patch doesn't violate any API semantics. clk_disable() doesn't guarantee that the clock is actually disabled. So, no clients of a clock can assume that a clock is disabled after their last call to clk_disable(). So, enabling the clock during a parent change is not a violation of any API semantics. This also has the nice side effect of simplifying the error handling code. Signed-off-by: Saravana Kannan <skannan@codeaurora.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed up whitespace issue] Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: abstract parent cacheJames Hogan2014-04-16
| | | | | | | | | | | | | Abstract access to the clock parent cache by defining clk_get_parent_by_index(clk, index). This allows access to parent clocks from clock drivers. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: fix typosPeter Meerwald2014-04-16
| | | | | | Signed-off-by: Peter Meerwald <pmeerw@pmeerw.net> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: Always notify whole subtree when reparentingSoren Brinkmann2014-04-16
| | | | | | | | | | | | | | | | | A clock's notifier count only reflects notifiers which are registered directly for that clock. A reparent operation though affects the whole subtree because of a potential rate change. When issuing the pre rate change notifications only the notifier count for the clock to be changed is considered and notifiers for subclocks may never be called. Resulting in clocks in the subtree which have registered notifiers, may receive a POST_- or ABORT_RATE_CHANGE notification, without a PRE_RATE_CHANGE_NOTIFICATION. Therefore always traverse the whole subtree when issueing pre rate change notifications during a reparent operation. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: honor CLK_GET_RATE_NOCACHE in clk_set_ratePeter De Schrijver2014-04-16
| | | | | | | | | | clk_set_rate() uses clk->rate directly. This causes problems if the clock is marked as CLK_GET_RATE_NOCACHE. Hence call clk_get_rate() to get the current rate. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: use clk_get_rate() for debugfsPeter De Schrijver2014-04-16
| | | | | | | | | | debugfs uses the rate field directly. However this ignores the CLK_GET_RATE_NOCACHE flag. Call clk_get_rate() instead. Tested-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300628 net: fec: align rx data buffer size for dma map/unmapFugang Duan2014-04-16
| | | | | | | Align allocated rx data buffer size for dma map/unmap, otherwise kernel print warning when enable DMA_API_DEBUG. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00300625-2 ARM:dts:imx6sx: add enet_out clk to avoid Last bit is not setFugang Duan2014-04-16
| | | | | | | | enet_out clock is the same as ptp clock, driver use the clock to check whether SOC supply clock to phy or not. So add enet_out clk to imx6sx dts file to avoid receive frame "L" bit is not set. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00300625-1 net: fec: avoid imx6sx enet-avb Last bit is not setFugang Duan2014-04-16
| | | | | | | | | | | | | | | When imx6sx-arm2/sdb platform do suspend/resume with nfs rootfs, there have warning like "rcv is not +last", which means the frame BD last bit is not set. The root cause: enet suspend will disable phy clock, phy link down, after resume back, enet MAC redo initial and ready to tx/rx packet, but phy still is not ready which is doing auto-negotiation. So, when enet output clock to phy, or there have regulator control phy power, after phy is ready and then re-init enet MAC. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00300474-2 ARM:dts: Replace phy regulator with gpio control in dtsLuwei Zhou2014-04-16
| | | | | | | Ther is some issue when using regulator contorl phy supply.The patch replace the regulator with gpio direct control. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00300474-1 net: fec: Revert "ENGR00299593-4 net:fec: return ↵Luwei Zhou2014-04-16
| | | | | | | | | | -EPROBE_DEFER when phy regulator isn't initialized" There is some issue when using regulator to contorl phy supply. We will turn to using GPIO pin control phy supply. This reverts fec driver modification in commit a494258a9f24944d710dd375cc12f204deccaa47. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00299593-4 net:fec: return -EPROBE_DEFER when phy regulator isn't ↵Luwei Zhou2014-04-16
| | | | | | | | | | initialized On i.mx6sx-17x17-arm2 board, fec needs to supply phy via max7322 extention gpio. When fec probe, the phy regulator doesn't complete initilization. The fec_probe needs to return -EPROBE_DEFER and kernel will retry fec_probe after a delay. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00299593-3 ARM: imx_v7_defconfig: enable max7322 in default configLuwei Zhou2014-04-16
| | | | | | Enable max7322 extention gpio driver in config Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00299593-2 ARM: dts: imx6sx-17X17-arm2: add max7322 gpio regulator dts ↵Luwei Zhou2014-04-16
| | | | | | | | | | | support FEC on imx6sx-17X17arm2 needs to make PHY work in 1.8v power supply. The 1.8v power supply is controlled by max7322 output0 pin.Enable max7322 dts support and phy regulator on imx6sx-17x17-arm2 platform in this patch. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00299593-1 gpio: max7322: modify the max7322 driver to support device ↵Luwei Zhou2014-04-16
| | | | | | | | | tree interface. The max7322 driver can only support platform data interface. This patch modify drvier to also support device tree interface. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00299180-2 ARM: imx: use dedicated ocram for lpm on i.mx6sxAnson Huang2014-04-16
| | | | | | | On i.MX6SX, there is dedicated ocram for low power mode, dts has different compatible string from mmio-sram, so update it. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00299180-1 ARM: dts: imx6sx: add compatible string for ocram_sAnson Huang2014-04-16
| | | | | | | Add compatible string for ocram_s to separate it from ocram, as this ocram_s is dedicated for low power mode. Signed-off-by: Anson Huang <b20788@freescale.com>
* mtd: m25p80: add support for the Spansion s25fl008k chipKuninori Morimoto2014-04-16
| | | | | | | | Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: print out the right information for JEDEC compliant NANDHuang Shijie2014-04-16
| | | | | | | | Check the chip->jedec_version, and print out the right information for JEDEC compliant NAND. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: parse out the JEDEC compliant NANDHuang Shijie2014-04-16
| | | | | | | | | | This patch adds the parsing code for the JEDEC compliant NAND. Since we need the 0x40 as the column address, this patch also makes the NAND_CMD_PARAM to use the 8-bit address only. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: add a helper to get the supported features for JEDECHuang Shijie2014-04-16
| | | | | | | | Add a helper to get the supported features for JEDEC compliant NAND. Also add a macro JEDEC_FEATURE_16_BIT_BUS. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: add fields for JEDEC in nand_chipHuang Shijie2014-04-16
| | | | | | | | Add the jedec_version field, and add an anonymous union which contains the nand_onfi_params and nand_jedec_params. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: add the data structures for JEDEC parameter pageHuang Shijie2014-04-16
| | | | | | | | Create the nand_jedec_params{} and jedec_ecc_info{} according to the JESD230A (Revision of JESD230, October 2012). Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* ENGR00299749 ARM: dts: imx: add pxp v4l2 output support on imx6sx 17x17 arm2 ↵Robby Cai2014-04-16
| | | | | | | | board Add V4L2 output via PxP support Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00299748-2 ARM: dts: imx: add pxp support for imx6sx 17x17 arm2 boardRobby Cai2014-04-16
| | | | | | | - add pxp resources - add a dummy clock for imx6sl/imx6dl Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00299748-1 imx: pxp: add display_axi_clock handling for imx6sxRobby Cai2014-04-16
| | | | | | | | The display axi clock is a clock gating newly added on imx6sx. It need to be enabled for lcdif/pxp/csi/pcie to work. It should be set as a placeholder on other SoCs. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00299746-5 ARM: dts: imx: add lcdif support on imx6sx 17x17 arm2 boardRobby Cai2014-04-16
| | | | | | | | - add pinmux setting for lcdif - add pwm3 setting for lcdif backlight - add a dummy clock for imx23/imx28/imx60 Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00299746-4 imx: lcdif: change the outstanding requests on any clock cycleRobby Cai2014-04-16
| | | | | | | | | | Refer to the RM: Generally, 4 outstanding requests of length 16 will provide enough performance to drive any standard display resolution. These configuration bits are intended to change the access pattern of the eLCDIF to optimize system bus throughput when other system masters will contend for system memory resources. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00299746-3 imx: lcdif: add disp_axi clock handling for imx6sxRobby Cai2014-04-16
| | | | | | | | | | | The display axi clock is a clock gating newly added on imx6sx. It need to be enabled for lcdif/pxp/csi/pcie to work. It should be set as a placeholder on other SoCs. This patch also simplifies the sanity check for axi and pixel clock. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00299746-2 ARM: imx6sx: correct lcdif clocksRobby Cai2014-04-16
| | | | | | | | | | - correct LCDIF pixel clock's parent selection - correct LCDIF PODF clock's parent - Set LCDIF1_PRE_SEL clock parent to PLL5_VIDEO, and set LCDIF1_SEL clock's parent to LCDIF1_PODF. They are set for pixel clock. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00299746-1 ARM: dts: imx6sx: Add PWM supportRobby Cai2014-04-16
| | | | | | add PWM[1-4] support in imx6sx.dtsi Signed-off-by: Robby Cai <R63905@freescale.com>
* ASoC: fsl-sai: convert to use regmap API for Freeacale SAIXiubo Li2014-04-16
| | | | | | | Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 78957fc349bcf29d415a649601581a993ff25e4d) Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ASoC: fsl-sai: Clean up the codeXiubo Li2014-04-16
| | | | | | | | | Makes the code slightly shorter. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 633ff8f8a4393b4a13b94eddd2613198c32035e6) Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ASoC: fsl_sai: fix the endianess for SAI fifo data.Xiubo Li2014-04-16
| | | | | | | | | Revert the SAI's endianess for fifo data to/from DMA engine. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 72aa62bed3ea30635156fad95f123a0b665072bf) Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ASoC: fsl_sai: Fix one bug for hardware limitation.Xiubo Li2014-04-16
| | | | | | | | | | | | | | | This is maybe one bug or a limitation of the hardware that the {T,R}CR2's Synchronous Mode bits must be set as late as possible, or the SAI device maybe hanged up, and there has not any explaination about this limitation in the SAI Data Sheet. And the {T,R}CR2's Synchronous Mode bits must be set at the same time whether for Tx or Rx stream. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 496a39d9ec238569fac6daceac8f5420c5edc2f1) Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ASoC: fsl_sai: Add disable operation for the corresponding data channel.Xiubo Li2014-04-16
| | | | | | | | | | | Enables/Disables the corresponding data channel for tx/rx operation. A channel must be enabled before its FIFO is accessed, and then disable it when tx/rx is stopped or idle. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit e5d0fa9c3ec59a40e0285d96b65b7f62875acd42) Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ASoC: fsl_sai: Move the global registers setting to _dai_probe()Xiubo Li2014-04-16
| | | | | | | | | | | | | Because we cannot make sure which one of _dai_fmt() and _dai_sysclk() will be firstly called. So move the RCSR/TCSR and TCR1/RCR1's initialization to _dai_probe(), and this can make sure that before any of {T,R}CR{1~5} register to be set the RCSR/TCSR's RE/TE bit has been cleared for the hareware limitation. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit e6dc12d7198eddba2e3e7a13feab5c7edde7ba1d) Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ASoC: fsl_sai: Sort local variable in general wayNicolin Chen2014-04-16
| | | | | | | | | | | | | | | | | | Generally we would write code for local variable like: static new_func() { struct xxx *yyy; ... int ret; } But this driver only follows this pattern for some functions, not all. Thus this patch sorts the local variable in the general way. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Reviewed-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 4e3a99f5b004b30bc604d82e5498700649148e0d)
* ASoC: fsl_sai: Make dev_err information neaterNicolin Chen2014-04-16
| | | | | | | | | | Since using dev_err() there's no need to mention SAI any more, it will print the full name of the driver -- fsl_sai. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Reviewed-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 190af12dad975f2ea7d69d1c5c9d36fec64da767)
* ASoC: fsl_sai: Drop useless ret in startup()Nicolin Chen2014-04-16
| | | | | | | | | We can save this ret to make the code neater. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Reviewed-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 15b29dae6604d2d2daf586429ff12f26272a868a)
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-19 12:20:05 -0400