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* of: set dma_mask to point to coherent_dma_maskRob Herring2014-06-13
| | | | | | | | Platform devices created by DT code don't initialize dma_mask pointer to anything. Set it to coherent_dma_mask by default if the architecture code has not set it. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* net: Add a software TSO helper APIEzequiel Garcia2014-06-13
| | | | | | | | Although the implementation probably needs a lot of work, this initial API allows to implement software TSO in mvneta and mv643xx_eth drivers in a not so intrusive way. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
* ENGR00318207 ARM:imx6x:Busfreq:Fix build warnings in busfreq driver.Ranjani Vaidyanathan2014-06-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following build warnings in busfreq driver: /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq-imx6.c: In function 'imx6_dt_find_ddr_sram': /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq-imx6.c:736:29: warning: assignment makes integer from pointer without a cast [enabled by default] ddr_freq_change_iram_phys = (void *)ddr_iram_addr; ^ CC drivers/base/firmware_class.o /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c: In function 'init_mmdc_ddr3_settings_imx6sx': /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c:404:22: warning: assignment makes pointer from integer without a cast [enabled by default] iram_iomux_settings = ddr_freq_change_iram_base + ddr_code_size; ^ /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c: In function 'init_mmdc_ddr3_settings_imx6q': /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c:539:22: warning: assignment makes pointer from integer without a cast [enabled by default] iram_iomux_settings = ddr_freq_change_iram_base + ddr_code_size; ^ CC arch/arm/mach-imx/busfreq_lpddr2.o /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c: In function 'init_mmdc_lpddr2_settings': /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c:96:2: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement] unsigned long ddr_code_size; ^ /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c:101:3: warning: passing argument 1 of 'memcpy' makes pointer from integer without a cast [enabled by default] mx6_change_lpddr2_freq = (void *)fncpy( Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00317542-2 ARM:dts:imx6x: Allocate 4K of IRAM for DDR freq change code.Ranjani Vaidyanathan2014-06-12
| | | | | | | Allocate 4K of IRAM space for DDR freq change code in the dts files. Also reduce the regular IRAM available for other functions by this amount. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00317542-1 ARM:imx6x: Dynamically calculate the size of low power mode code.Ranjani Vaidyanathan2014-06-12
| | | | | | | | | | | | | This patch adds support for dynamically calculating the size of all low power code (suspend, ddr freq change and low power idle). This allows for easy code changes in the future. This patch also moves the DDR frequency change code from lower 8K of the memory allocated for IRAM page table to regular IRAM. With this the lower 8K of the IRAM page table only contains suspend/resume and low power IDLE code. This gives a little more flexibility to the cdoe size for suspend/resume and low power IDLE. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00317861 ARM: imx: add cpufreq support when VPU running at 352MHzAnson Huang2014-06-11
| | | | | | | | | When VPU 352MHz is supported, PLL2_PFD2 will run at 352MHz instead of 396MHz, CPUFreq driver will use PLL2_PFD2 when it is running at 396MHz setpoint, so when VPU 352MHz is enabled, CPUFreq can be enabled but need to remove the 396MHz setpoint. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00317675-2 ASoC: fsl: cs42xx8: add support for DSP_AShengjiu Wang2014-06-10
| | | | | | Correct the definition of TDM and ONLINE_24 bit Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* ENGR00317675-1 ASoC: fsl: esai: refine esai for tdm supportShengjiu Wang2014-06-10
| | | | | | | Add parameter for slots, and caculate the number of TX/RX pins with slots. Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* ENGR00317636 ASoC: fsl: hdmi: Disable NEON optimizationShengjiu Wang2014-06-10
| | | | | | | | Enable NEON optimization will cause pulseaudio crash in the user space. Which is caused by using the NEON instruction, if only use "VPUSH, VPOP" in the function, crash will be happened also. Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* ENGR00317376-4 pwm: i.MX: Avoid sample FIFO overflow for i.MX PWM version2Liu Ying2014-06-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX PWM version2 is embedded in several i.MX SoCs, such as i.MX27, i.MX51 and i.MX6SL. There is a 4-word(16bit) sample FIFO in this IP. Each FIFO slot determines the duty period of a PWM waveform in one full cycle. The IP spec mentions that we should not write a fourth sample because the FIFO will become full and triggers a FIFO write error (FWE) which will prevent the PWM from starting once it is enabled. In order to avoid any sample FIFO overflow issue, this patch clears all sample FIFO by doing software reset in the configuration hook when the controller is disabled or waits for a full PWM cycle to get a relinquished FIFO slot when the controller is enabled and the FIFO is fully loaded. The FIFO overflow issue can be reproduced by the following commands on the i.MX6SL EVK platform, assuming we use PWM2 for the debug LED which is driven by the pin HSIC_STROBE and the maximal brightness is 255. echo 0 > /sys/class/leds/user/brightness echo 0 > /sys/class/leds/user/brightness echo 0 > /sys/class/leds/user/brightness echo 0 > /sys/class/leds/user/brightness echo 255 > /sys/class/leds/user/brightness Here, FWE happens(PWMSR register reads 0x58) and the LED can not be lighten. Another way to reproduce the FIFO overflow issue is to run this script: while true; do echo 255 > /sys/class/leds/user/brightness; done Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00317376-3 pwm: i.MX: Cleanup indentation for register definitionsLiu Ying2014-06-08
| | | | | | | This patch contains no logic change to cleanup indentation for register definitions only. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00317376-2 pwm: i.MX: Fix the macro MX3_PWMCR_PRESCALER(x) definitionLiu Ying2014-06-08
| | | | | | | | This patch adds missing parentheses around the argument of the macro MX3_PWMCR_PRESCALER(x) to avoid any potential macro expansion issue. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00317376-1 pwm: i.MX: Don't reset PWMv2 when doing configurationLiu Ying2014-06-08
| | | | | | | | | | | | The patch for ENGR00308394 resets PWMv2 every time we do configuration. This may make the PWM period unstable if we only tune duty period continuously, and finally cause unstable PWM backlight light issue happen. Revert "ENGR00308394 pwm: i.MX: Avoid sample fifo overflow for i.MX pwm version2" This reverts commit 545c7383dfba874180b394f8b00b563a6541e158. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00315400 ARM: imx: add lpddr2 busfreq support for i.mx6sxAnson Huang2014-06-04
| | | | | | | | | | Add freq scaling for lpddr2 of i.MX6SX, support 3 setpoints: high -> 400MHz audio -> 100MHz low -> 24MHz Signed-off-by: Anson Huang <b20788@freescale.com>
* mtd: cfi: Remove unnecessary OOM messagesJingoo Han2014-06-04
| | | | | | | | | The site-specific OOM messages are unnecessary, because they duplicate the MM subsystem generic OOM message. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* serial: imx: disable the receiver ready interrupt for imx_stop_rxHuang Shijie2014-06-03
| | | | | | | | | This patch disables the receiver ready interrupt for imx_stop_rx. It reduces the interrupt numbers when the uart is going to close or suspend. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* serial: imx: remove the redundant codeHuang Shijie2014-06-03
| | | | | | | | | | In the imx_startup(), we will reset the uart port which will reset all the FIFOs, including the URXD. So the code to clear the RX FIFO is redundant. Just remove it. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* serial: imx: reset the uart port all the timeHuang Shijie2014-06-03
| | | | | | | | | | | | | | | | | | | | | Current code resets the uart port only when it supports the irda mode. In actually, we also need to reset the uart port in the non-irda mode. A hang was caught in the following case: UART A transmits data to the other end. But the transmission maybe terminated. In some corner case, the TX FIFO maybe not empty. The kernel will hang at the imx_set_termios(): ............................................................ while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) barrier(); ............................................................ This patch resets the uart port all the time in the imx_startup(). And fix the hang. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* serial: imx: Disable new features of autobaud detectionFabio Estevam2014-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bit 7 of UCR3 is described in the i.MX reference manuals (with the exception of i.MX1) as follows: ADNIMP: Autobaud Detection Not Improved-. Disables new features of autobaud detection (See Baud Rate Automatic Detection Protocol, for more details). 0 Autobaud detection new features selected 1 Keep old autobaud detection mechanism The "new features" mechanism occasionally cause the receiver to get out of sync and continuously produce received characters of '\xff'. In order to reproduce the problem: $ stty -F /dev/ttymxc0 19200 - Change the terminal baudrate to 19200 - Type in the console and it should look good - Change the terminal baudrate back to 115200 - Type 'b' in the console, then a stream of garbage characters is seen. Also rename the bit definition as per the reference manual. Tested on mx6q, mx6dl, mx6solo and mx53. Based on a patch from Eric Nelson for U-boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00314581 pcie: enable pcie ep rc on imx6sxRichard Zhu2014-05-26
| | | | | | enable pcie ep rc validation on imx6sx sdb board. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00314570-2 pcie:add pcie power control on imx6sxRichard Zhu2014-05-26
| | | | | | | | | | | | | | | | | | imx6sx pcie has standalone ldo domain, add the power control routines. - pcie pm recovery works when imx6sx pcie is used as rc. - pcie pm recovery works on both rc and ep modes. - l2 mode had been validated on imx6sx sdb(rc) and e1000e (ep) environment. - fastmix and megamix can be turn off and turn on, during system suspend/resume. - hw: - imx6sx sdb board. - intel e1000e nic - xhci pcie2usb device Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00314570-1 arm: add pcie power control on imx6sxRichard Zhu2014-05-26
| | | | | | | imx6sx pcie has standalone ldo domain, add the power control routines on the ldo regulator call back. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00314571 pcie: resolve one compile warning on pcie pmRichard Zhu2014-05-26
| | | | | | resolve one compile warning on pcie pm Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00309838 ARM: imx6sl: gpc: add chip revision check for dispmixRobby Cai2014-05-23
| | | | | | | The dispmix feature works without problem since TO1.2. This patch adds the back-compatibility for older chip. Signed-off-by: Robby Cai <r63905@freescale.com>
* ENGR00313867 media: mxc: ADV7180: Get standard when the chip is lockedLiu Ying2014-05-21
| | | | | | | | | | | | | | | The IN_LOCK bit of the ADV7180 register STATUS_1(0x10) indicates if the chip is locked or not in auto detection mode. We should get valid standard when the chip is locked, otherwise, invalid standard should be returned. This patch checks the IN_LOCK bit when we get standard in auto detection mode. Conflicts: drivers/media/video/mxc/capture/adv7180.c Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit c0d94e51b331002c11ebdfc8a559c8ec878894d6)
* ENGR00314119 [#1183] fixed database mutex multi-lock issueXianzhong2014-05-21
| | | | | | | | | | | | The abnormal flow with the monkey test freeze problem is as below: gckKERNEL_DestroyProcessDB--> aquire mutex --> gckCOMMAND_Detach(gckEVENT_FreeContiguousMemory) --> ___RemoveRecordFromProcessDB --> gckKERNEL_RemoveProcessDB --> aquire the same mutex the fix is to disable mutex lock when perform record destory operations Date: May 19, 2014 Signed-off-by: Xianzhong <b07117@freescale.com> Acked-by: Jason Liu
* ENGR00312563-2 [#1183] remove duplicated mutex protectionXianzhong2014-05-21
| | | | | | | | | counterMutex is not necessary after refine dabase mutex remove counterMutex to avoid duplicated mutex protection Date: May 15, 2014 Signed-off-by: Xianzhong <b07117@freescale.com> Acked-by: Jason Liu
* ENGR00312563-1 [#1183] fixed gpu database mutex issueXianzhong2014-05-21
| | | | | | | | | | | | | | | | | | | | | | | | | system hang in webGL conformance test with the following log galcore daemon D 807430b4 0 105 2 0x00000000 [<807430b4>] (__schedule+0x34c/0x720) from [<807438c8>] (schedule_preempt_disabled+0x14/0x20) [<807438c8>] (schedule_preempt_disabled+0x14/0x20) from [<80742328>] (__mutex_lock_slowpath+0x158/0x21c) [<80742328>] (__mutex_lock_slowpath+0x158/0x21c) from [<80742434>] (mutex_lock+0x48/0x4c) [<80742434>] (mutex_lock+0x48/0x4c) from [<8052aa68>] (gckOS_AcquireMutex+0x64/0x6c) [<8052aa68>] (gckOS_AcquireMutex+0x64/0x6c) from [<80534e0c>] (gckKERNEL_AddProcessDB+0x30/0x37c) [<80534e0c>] (gckKERNEL_AddProcessDB+0x30/0x37c) from [<8052d628>] (gckOS_Broadcast+0xe0/0xe8) [<8052d628>] (gckOS_Broadcast+0xe0/0xe8) from [<80536fa8>] (_TryToIdleGPU+0x124/0x12c) [<80536fa8>] (_TryToIdleGPU+0x124/0x12c) from [<8053887c>] (gckEVENT_Notify+0x520/0x574) [<8053887c>] (gckEVENT_Notify+0x520/0x574) from [<80540468>] (gckHARDWARE_Interrupt+0x60/0x70) [<80540468>] (gckHARDWARE_Interrupt+0x60/0x70) from [<805271cc>] (threadRoutine2D+0x20/0x78) [<805271cc>] (threadRoutine2D+0x20/0x78) from [<80045728>] (kthread+0xa4/0xb0) [<80045728>] (kthread+0xa4/0xb0) from [<8000e158>] (ret_from_fork+0x14/0x3c) this is integration issue introduced by database mutex enhancement, remove duplicated mutex unlock when remove database Date: May 15, 2014 Signed-off-by: Xianzhong <b07117@freescale.com> Acked-by: Jason Liu
* ENGR00313889 ARM DTS: Enable v4l2 capture function for imx6sx lcdif1 dtsSandor Yu2014-05-18
| | | | | | | | | LCDIF1 pin conflict with camera, ov5640 driver is disabled in imx6sx 19x19 arm2 lcdif1 dts file, v4l2 capture function shouldn't disabled in the dts, remove the disable code. Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00313888 vadc: Enable Chroma AGC Control registerSandor Yu2014-05-18
| | | | | | | Add register LMAGC1 and CHAGC1 that missing in i.MX6sx RM. Enable chroma AGC function. Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00309881 ARM:imx6: Disable L1 and L2 when DDR is in self-refresh.Ranjani Vaidyanathan2014-05-16
| | | | | | | | | When switching to page tables in IRAM, we are switching from a cacheable to non-cacheable page table. Based on recommendation from ARM, we need to ensure that branch prediction, L1 data nd L2 are disabled when DDR is put into self-refresh. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00313685-15 ARM: dts: imx: apply ENET IRQ workaround for sabresd boardShawn Guo2014-05-16
| | | | | | | | | | | | | | | This is pretty much an example to demonstrate how the GPIO6 workaround for bug ERR006687 (ENET: Only the ENET wake-up interrupt request can wake the system from Wait mode) should be applied for a board. Basically it requires a setup of MX6QDL_PAD_GPIO_6__ENET_IRQ in pinctrl entry, and an overwrite on the property interrupts-extended to replace the ENET GIC IRQ with GPIO1_6. Since the pad GPIO6 is used by I2C3 on the board, we have to create sabresd-enetirq.dts with I2C3 disabled to enable this workaround. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00313685-14 net: fec: check workaround for FEC_QUIRK_BUG_WAITMODEShawn Guo2014-05-16
| | | | | | | | | | | | For bug ERR006687 (ENET: Only the ENET wake-up interrupt request can wake the system from Wait mode.), some board designs may choose to work around it by routing the ENET interrupts to pad GPIO6, and the resulting GPIO interrupt will wake the system from Wait mode. The patch adds a check for such workaround and skip the pm_qos_add_request(..., 0) call if the workaround is applied. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00313685-13 ARM: dts: imx6qdl: use interrupts-extended for fecTroy Kisky2014-05-16
| | | | | | | | | | | | | | | | commit 454cf8f54d9918c8017f2eee7fb0138927ef2afd upstream. We need to be able to override interrupts in board file to workaround a hardware bug for ethernet interrupts waking the processor by using interrupts-extended. So, use interrupts-extended here as well. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/boot/dts/imx6qdl.dtsi
* ENGR00313685-12 ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQTroy Kisky2014-05-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit d8c765e0d1ddbd5032c2491c82cc9660c2f0e7f2 upstream. From "Chip Errata for the i.MX 6Dual/6Quad" ERR006687 ENET: Only the ENET wake-up interrupt request can wake the system from Wait mode. The ENET block generates many interrupts. Only one of these interrupt lines is connected to the General Power Controller (GPC) block, but a logical OR of all of the ENET interrupts is connected to the General Interrupt Controller (GIC). When the system enters Wait mode, a normal RX Done or TX Done does not wake up the system because the GPC cannot see this interrupt. This impacts performance of the ENET block because its interrupts are serviced only when the chip exits Wait mode due to an interrupt from some other wake-up source. Adding MX6QDL_PAD_GPIO_6__ENET_IRQ is the 1st step to workaround this problem. The input reg is set to 0x3c to set IOMUX_OBSRV_MUX1 to ENET_IRQ. The mux reg value is 0x11, so that the observable mux is routed to this pin and to the gpio controller(sion bit). These magic values come from Ranjani Vaidyanathan's patch: "ENGR00257847-1 MX6Q/DL-Fix Ethernet performance issue when WAIT mode is active" Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> CC: Ranjani Vaidyanathan <ra5478@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00313685-11 of/irq: Fix potential buffer overflowGrant Likely2014-05-16
| | | | | | | | | | | | | | | commit 355e62f5ad12b005c862838156262eb2df2f8dff upstream. Commit 2361613206e6, "of/irq: Refactor interrupt-map parsing" introduced a potential buffer overflow bug because it doesn't do sufficient range checking on the input data. This patch adds the appropriate checking and buffer size adjustments. If the bounds are out of range then warn loudly. MAX_PHANDLE_ARGS should be sufficient. If it is not then the value can be increased. Signed-off-by: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00313685-10 of/irq: Fix bug in interrupt parsing refactor.Grant Likely2014-05-16
| | | | | | | | | | | | | | | | commit 78119fd1068cc068f6112a57a5f6de0e5b20245a upstream. Commit 2361613206e6, "of/irq: Refactor interrupt-map parsing" introduced a bug. The irq parsing will fail for some nodes that don't have a reg property. It is fixed by deferring the check for reg until it is actually needed. Also adjust the testcase data to catch the bug. Signed-off-by: Grant Likely <grant.likely@linaro.org> Tested-by: Stephen Warren <swarren@nvidia.com> Tested-by: Ming Lei <tom.leiming@gmail.com> Tested-by: Stephen Warren <swarren@nvidia.com> Cc: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00313685-9 of/irq: create interrupts-extended propertyGrant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | | | commit 79d9701559a9f3e9b2021fbd292f5e70ad75f686 upstream. The standard interrupts property in device tree can only handle interrupts coming from a single interrupt parent. If a device is wired to multiple interrupt controllers, then it needs to be attached to a node with an interrupt-map property to demux the interrupt specifiers which is confusing. It would be a lot easier if there was a form of the interrupts property that allows for a separate interrupt phandle for each interrupt specifier. This patch does exactly that by creating a new interrupts-extended property which reuses the phandle+arguments pattern used by GPIOs and other core bindings. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Kumar Gala <galak@codeaurora.org> [grant.likely: removed versatile platform hunks into separate patch] Cc: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00313685-8 microblaze/pci: Drop PowerPC-ism from irq parsingGrant Likely2014-05-16
| | | | | | | | | | | | | commit f27446c3ad5b6d3b5b28ec0176e23d3ceca595d8 upstream. The Microblaze PCI code copied the PowerPC irq handling, but powerpc needs to handle broken device trees that are not present on Microblaze. This patch removes the powerpc special case and replaces it with a direct of_irq_parse_and_map_pci() call. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00313685-7 of/irq: Create of_irq_parse_and_map_pci() to consolidate arch ↵Grant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | code. commit 16b84e5a505c790538e534ad8dfda9c288691e40 upstream. Several architectures open code effectively the same code block for finding and mapping PCI irqs. This patch consolidates it down to a single function. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/mach-integrator/pci_v3.c arch/mips/pci/pci-rt3883.c
* ENGR00313685-6 of: Add testcases for interrupt parsingGrant Likely2014-05-16
| | | | | | | | | | commit a9f10ca76d784023fc45f01f025b54e9960f4ec1 upstream. This patch extends the DT selftest code with some test cases for the interrupt parsing functions. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00313685-5 of: Add helper for printing an of_phandle_args structureGrant Likely2014-05-16
| | | | | | | | | | | | | commit 624cfca534f9b1ffb1326617b4e973a3d5ecff4a upstream. It is sometimes useful for debug to get the contents of an of_phandle_args structure out into the kernel log. Signed-off-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: drivers/of/base.c
* ENGR00313685-4 of/irq: Refactor interrupt-map parsingGrant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 2361613206e66ce59cc0e08efa8d98ec15b84ed1 upstream. All the users of of_irq_parse_raw pass in a raw interrupt specifier from the device tree and expect it to be returned (possibly modified) in an of_phandle_args structure. However, the primary function of of_irq_parse_raw() is to check for translations due to the presence of one or more interrupt-map properties. The actual placing of the data into an of_phandle_args structure is trivial. If it is refactored to accept an of_phandle_args structure directly, then it becomes possible to consume of_phandle_args from other sources. This is important for an upcoming patch that allows a device to be connected to more than one interrupt parent. It also simplifies the code a bit. The biggest complication with this patch is that the old version works on the interrupt specifiers in __be32 form, but the of_phandle_args structure is intended to carry it in the cpu-native version. A bit of churn was required to make this work. In the end it results in tighter code, so the churn is worth it. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: drivers/of/irq.c
* ENGR00313685-3 of/irq: simplify args to irq_create_of_mappingGrant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | | | commit e6d30ab1e7d1281784672c0fc2ffa385cfb7279e upstream. All the callers of irq_create_of_mapping() pass the contents of a struct of_phandle_args structure to the function. Since all the callers already have an of_phandle_args pointer, why not pass it directly to irq_create_of_mapping()? Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/mach-integrator/pci_v3.c arch/mips/pci/pci-rt3883.c kernel/irq/irqdomain.c
* ENGR00313685-2 of/irq: Replace of_irq with of_phandle_argsGrant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | commit 530210c7814e83564c7ca7bca8192515042c0b63 upstream. struct of_irq and struct of_phandle_args are exactly the same structure. This patch makes the kernel use of_phandle_args everywhere. This in itself isn't a big deal, but it makes some follow-on patches simpler. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/mach-integrator/pci_v3.c arch/mips/pci/pci-rt3883.c include/linux/of_irq.h
* ENGR00313685-1 of/irq: Rename of_irq_map_* functions to of_irq_parse_*Grant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 0c02c8007ea5554d028f99fd3e29fc201fdeeab3 upstream. The OF irq handling code has been overloading the term 'map' to refer to both parsing the data in the device tree and mapping it to the internal linux irq system. This is probably because the device tree does have the concept of an 'interrupt-map' function for translating interrupt references from one node to another, but 'map' is still confusing when the primary purpose of some of the functions are to parse the DT data. This patch renames all the of_irq_map_* functions to of_irq_parse_* which makes it clear that there is a difference between the parsing phase and the mapping phase. Kernel code can make use of just the parsing or just the mapping support as needed by the subsystem. The patch was generated mechanically with a handful of sed commands. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/mach-integrator/pci_v3.c arch/mips/pci/pci-rt3883.c drivers/of/irq.c
* ENGR00313508-03 ARM: dts: imx6sx: add enet magic pattern supportFugang Duan2014-05-15
| | | | | | Add enet magic pattern support for imx6sx arm2 platforms. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00313508-02 net: fec: add sleep mode supportFugang Duan2014-05-15
| | | | | | | | | When imx6sx is in stop mode, enet sleep mode is entered, the magic pattern can wake up imx6sx system. Use ethtool to enable/disable wol magic pattern wake up. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00313508-01 ARM: imx6sx: add enet sleep mode supportFugang Duan2014-05-15
| | | | | | Add enet sleep mode support for imx6sx arm2 platforms. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00313535-2 ASoC: fsl: Register two kcontrol for asrc p2pShengjiu Wang2014-05-15
| | | | | | | Register p2p width amd p2p rate tow kcontrol for asrc p2p, use can get/change these parameter with amixer. Signed-off-by: Shengjiu Wang <b02247@freescale.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-15 05:57:36 -0400