aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAge
...
* of: Add helper for getting the maximum alias index for a stemSascha Hauer2014-06-24
| | | | | | | | | | of_alias_max_index will return the maximum number for which an alias of a given stem exists. This is useful for frameworks whishing to reserve a number of device slots from dynamic allocation. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> (cherry picked from commit 18ae7362e9822993436c1a544e49cfd58fa175b2)
* ENGR00314144 mxc: mlb: Rename the mxc_mlb150 to mxc_mlb.luweizhou2014-06-24
| | | | | | | | | Since i.MX6SX doesn't supports MLB150 , it is not strictly explicit to name driver module as mxc_mlb150.ko. Rename it to mxc_mlb.ko.It would be more common. Signed-off-by: Luwei Zhou <b45643@freescale.com> (cherry picked from commit dbe1a350e2f61e827501fd322951b9ea255461a5)
* ENGR00319416 pcie: random link down issue after warm-rstRichard Zhu2014-06-23
| | | | | | | | | | | | | | | | | There are about 0.02% percentage on some imx6q/dl/solo hw boards, random pcie link down when warm-reset is used. Make sure to clear the ref_ssp_en bit16 of gpr1 before warm-rst, and set ref_ssp_en after the pcie clks are stable to workaround it. rootcause: * gpr regisers wouldn't be reset by warm-rst, while the ref_ssp_en is required to be reset by pcie. (work-around in u-boot) * ref_ssp_en should be set after pcie clks are stable. (work-around in kernel) Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00319582 iMX6SX: qspi code change to support DSMAllen Xu2014-06-23
| | | | | | add suspend/resume functions and reset qspi controller when resume. Signed-off-by: Allen Xu <b45815@freescale.com>
* ENGR00319480 ARM: dts: imx6sx: add enet as mege_fast wakeup sourceFugang Duan2014-06-20
| | | | | | | | For imx6sx 17x17/19x19 arm2 board, add enet as mege_fast wakeup source. For imx6sx sdb board, it don't support wake on lan, so it cannot support enet as mega_fast wake up source. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00319480 net: fec: support DSM with M/F mix offFugang Duan2014-06-20
| | | | | | | To support DSM with M/F mix off, driver need to call phy_stop before suspend, call phy_start after resume. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00319455-4 imx_v7_defconfig: enable canfd by defaultDong Aisheng2014-06-20
| | | | | | | | enable canfd by default. The defconfig is generated by make ARCH=arm savedefconfig which got the uneeded CONFIG_USB_PHY removed. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00319455-3 dts: imx6sx-sdb: add canfd supportDong Aisheng2014-06-20
| | | | | | Introduce a new dtb imx6sx-sdb-canfd.dtb due to pin conflict with flexcan. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00319455-2 imx6sx: enable can transceiver by default for canfdDong Aisheng2014-06-20
| | | | | | | | Switch on the transceiver by default for board with canfd enabled since canfd driver does not handle it. Two CAN instances share the same switch. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00319455-1 can: m_can: add Bosch M_CAN controller supportDong Aisheng2014-06-20
| | | | | | | | | | | | | | | | | | | | The patch adds the basic CAN TX/RX function support for Bosch M_CAN controller. For TX, only one dedicated tx buffer is used for sending data. For RX, RXFIFO 0 is used for receiving data to avoid overflow. Rx FIFO 1 and Rx Buffers are not used currently, as well as Tx Event FIFO. Due to the message ram can be shared by multi m_can instances and the fifo element is configurable which is SoC dependant, the design is to parse the message ram related configuration data from device tree rather than hardcode define it in driver which can make the message ram using fully transparently to M_CAN controller driver, then we can gain better driver maintainability and future features upgrade. M_CAN also supports CANFD protocol features like data payload up to 64 bytes and bitrate switch at runtime, however, this patch still does not add the support for these features. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* net: fec: Don't clear IPV6 header checksum field when IP accelerator enableFugang Duan2014-06-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 96c50caa5148 (net: fec: Enable IP header hardware checksum) enable HW IP header checksum for IPV4 and IPV6, which causes IPV6 TCP/UDP cannot work. (The issue is reported by Russell King) For FEC IP header checksum function: Insert IP header checksum. This "IINS" bit is written by the user. If set, IP accelerator calculates the IP header checksum and overwrites the IINS corresponding header field with the calculated value. The checksum field must be cleared by user, otherwise the checksum always is 0xFFFF. So the previous patch clear IP header checksum field regardless of IP frame type. In fact, IP HW detect the packet as IPV6 type, even if the "IINS" bit is set, the IP accelerator is not triggered to calculates IPV6 header checksum because IPV6 frame format don't have checksum. So this results in the IPV6 frame being corrupted. The patch just add software detect the current packet type, if it is IPV6 frame, it don't clear IP header checksum field. Cc: Russell King <linux@arm.linux.org.uk> Reported-and-tested-by: Russell King <linux@arm.linux.org.uk> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* i2c: imx: fix the i2c bus hang issue when do repeat restartFugang Duan2014-06-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Test i2c device Maxim max44009, datasheet is located at: http://www.maximintegrated.com/datasheet/index.mvp/id/7175 The max44009 support repeat operation like: read -> repeat restart -> read/write The current i2c imx host controller driver don't support this operation that causes i2c bus hang due to "MTX" is cleared in .i2c_imx_read(). If "read" is the last message there have no problem, so the current driver supports all SMbus operation like: write -> repeat restart -> read/write IMX i2c controller for master receiver has some limitation: - If it is the last byte for one operation, it must generate STOP signal before read I2DR to prevent controller from generating another clock cycle. - If it is the last byte in the read, and then do repeat restart, it must set "MTX" before read I2DR to prevent controller from generating another extra clock cycle. The patch is to fix the issue. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* ENGR00318773-11 ARM: imx6qdl: Remove incorrect clock sourcesNicolin Chen2014-06-19
| | | | | | | | | The clock sources from ASRC, ESAI and MLB are not actually from CCM but outside PAD inputs. So we these clock sources over here are totally wrong and should be fixed. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00318773-10 ASoC: imx-audmux: Add driver suspend and resume to support ↵Nicolin Chen2014-06-19
| | | | | | | | | | | | MEGA Fast For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of modules during system suspend and resume procedure. Thus, AUDMUX needs to save all the values of registers before the system suspend and restore them after the system resume. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00318773-9 ASoC: fsl_ssi: Add driver suspend and resume to support MEGA FastNicolin Chen2014-06-19
| | | | | | | | | | For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of modules during system suspend and resume procedure. Thus, SSI needs to save all the values of registers before the system suspend and restore them after the system resume. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00318773-8 ASoC: fsl_spdif: Add driver suspend and resume to support ↵Nicolin Chen2014-06-19
| | | | | | | | | | | | MEGA Fast For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of modules during system suspend and resume procedure. Thus, SPDIF needs to save all the values of registers before the system suspend and restore them after the system resume. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00318773-7 ASoC: fsl_esai: Add driver suspend and resume to support MEGA ↵Nicolin Chen2014-06-19
| | | | | | | | | | | | Fast For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of modules during system suspend and resume procedure. Thus, ESAI needs to save all the values of registers before the system suspend and restore them after the system resume. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00318773-6 ASoC: fsl_sai: Add driver suspend and resume to support MEGA FastNicolin Chen2014-06-19
| | | | | | | | | | For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of modules during system suspend and resume procedure. Thus, SAI needs to save all the values of registers before the system suspend and restore them after the system resume. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00318773-5 ASoC: dmaengine: Merge trigger RESUME to START and SUSPEND to ↵Nicolin Chen2014-06-19
| | | | | | | | | | | | STOP The SDMA driver doesn't support DMA_PAUSE and DMA_RESUME commands. So this patch use TRIGGER_START for TRIGGER_RESUME and TRIGGER_SUSPEND for TRIGGER_STOP as a work around so that Audio can normally stop and restart its corresponding DMA channels. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
* ENGR00318773-4 mxc: asrc: Add driver suspend and resume to support MEGA FastNicolin Chen2014-06-19
| | | | | | | | | | For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of modules during system suspend and resume procedure. Thus, ASRC needs to save all the values of registers before the system suspend and restore them after the system resume. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00318773-3 mxc: asrc: Simplify buffer processing functionNicolin Chen2014-06-19
| | | | | | | We actually do nothing to process input buffer. Thus simplify it. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00318773-2 mxc: asrc: Abstract a helper function for duplicated ↵Nicolin Chen2014-06-19
| | | | | | | | | | | wait_for_compeltion code After dropping the extra task for last period buffer fetching, we have a total symmetrical wait_for_compeltion here so it's better to abstract a function to make the driver neat. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00318773-1 mxc: asrc: Don't use the extra work thread to handle the last ↵Nicolin Chen2014-06-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | period data The original design: -> Input DMA task -> complete() | -> Output DMA task -> complete() | | | -> Last period polling work thread -> complete() | Main thread --------------> wait_for_completion() of Input and last period It's too complicated and worthless to use an extra work thread for last period data. So this patch just switches the flow into a simpler approach: -> Input DMA task -> complete() | -> Output DMA task -> complete() | Main thread --------------> wait_for_completion() of In/Output -> Last period polling Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* regmap: cache: Handle stride > 1 in sync_block_raw_flushDylan Reid2014-06-19
| | | | | | | | | | | | | | | regcache_sync_block_raw_flush takes the address of the base register and the address of one past the last register to write to. "count" is the number of registers in the range, not the number of bytes, it should be (end addr - start addr) / stride. Without accounting for strides greater than one, registers past the end might be synced or the writeable_reg callback at the beginning of _regmap_raw_write will fail and nothing will be written. Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 78ba73eecd2256790926859849801c0446766c0a) Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ASoC: pcm: Fix incorrect condition check for case SNDRV_PCM_TRIGGER_SUSPENDNicolin Chen2014-06-19
| | | | | | | | | The regular state before we execute SNDRV_PCM_TRIGGER_SUSPEND should be SNDRV_PCM_TRIGGER_START, not SNDRV_PCM_TRIGGER_STOP. Thus fix it. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 868a6ca84ee7e547ae01a5e04e232e4a392c50b8)
* ENGR00319166: regulator: anatop: correct vddpu regulator status in ↵Robin Gong2014-06-19
| | | | | | | | | | | | | | | | | | ldo-bypass mode In case ldo-bypass mode, we will use 'pureg_dummy' in stead of 'vddpu'.The voltage setting is 0x1f(ldo-mode) and the non-zero value means 'vddpu' enabled status. Regulator common framwork will turn off the unused regulator which keep enabled status. That will set the PU mode from ldo-bypass to power off, and may make gpu/vpu driver hang etc. You can also see the below abnormal message during boot: [ 3.000182] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4 [ 3.010577] VGEN3: disabling [ 3.015116] VGEN2: disabling [ 3.019659] VGEN1: disabling [ 3.023598] vddpu: disabling Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00318965 dma: sdma: swap LWML and HWML of INFO if LWML > HWMLRobin Gong2014-06-19
| | | | | | | | Correct r0, r1 and INFO parames if LWML > HWML in DEV_TO_DEV case. Below link raise up the issue: https://community.freescale.com/message/410174?et=watches.email.thread#410174 Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00318936-2 input: keyboard: imx: remove usless release interrupt enabled ↵Robin Gong2014-06-19
| | | | | | | | | | code Remove useless code for release interrupt enabled, because we check status by timer rather than release interrupt. Remove the code which may disable depress interrupt. Also make sure enable depress interrupt in suspend function. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00318936-1 input: keyboard: imx: add pm_stay_awake and pm_relaxRobin Gong2014-06-19
| | | | | | | | | | There is a small window after system suspend but timer scan function didn't finish timely, in this case, system enter suspend without kpp interrupt enabled and failed to resume back if key depressed.We add pm_stay_awake and pm_relax to make sure system suspend flow abort in this case. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00318995 V4L2_PXP: no overlay can be seen in the pxp_v4l2 test caseFancy Fang2014-06-18
| | | | | | | The "layer_nr" field in struct pxp_config_data is modified by the memset unconsciously. So this field should not reset. Signed-off-by: Fancy Fang <chen.fang@freescale.com>
* ENGR00318938-4 serial: imx: add support for no_console_suspendHuang Shijie2014-06-18
| | | | | | this patch adds the support for kernel cmdline "no_console_suspend". Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00318938-3 serial: imx: change the wait even to interruptiableHuang Shijie2014-06-18
| | | | | | | | | | | The wait_event() makes the application hang for ever in the following case: [1] the hardware flow control is enabled. [2] the other end (or the remote end) is terminated, and the TX is still waiting for the hardware flow control signal to become asserted. This patch fixes it by changing the wait_event to wait_event_interruptible. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00318938-2 serial: imx: terminate the RX DMA when the UART is suspendingHuang Shijie2014-06-18
| | | | | | | When the uart port is suspending, the RX data is useless. So in this case, we can terminate the RX DMA right now. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00318938-1 serial: imx: add UART save/restore during DSM enter/exitAnson Huang2014-06-18
| | | | | | | | When Mega/Fast mix is off, UART controller will lost power, so need to add save/restore to make it work after resume. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00318259-2 ARM: imx: support mega fast domain power off in DSMAnson Huang2014-06-17
| | | | | | | | | | Add mega fast domain power off feature in DSM, it can save about 0.72mW power; If there is any module in Mega/Fast domain enabled as wakeup source, then Mega/Fast domain's power will be kept on in DSM. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00318259-1 ARM: dts: imx6sx: add mege_fast wakeup source infoAnson Huang2014-06-17
| | | | | | | | Add Mega/Fast domain's wakeup source info for kernel, if there is wakeup source in Mega/Fast domain enabled, then this domain's power can NOT be disabled in DSM. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00318392 ARM:imx6x: Save/restore SCU and some CP15 registers across ↵Ranjani Vaidyanathan2014-06-13
| | | | | | | | | | | | | | | suspend/resume This patch ensures that the SCU and certain A9 CP15 registers state are maintained across a suspend/resume cycle: 1. Need to ensure that SCU standby bit is set again after suspend/resume cycle, else the system will never WAIT mode after a suspend/resume cycle. This bit should be enabled on all SMP systems immaterial of whether CPUIDLE is enabled or not. 2. Several A9 errata workarounds involve setting bits in the ARM diagnostic register. Save/restore this register across a suspend/resume cycle. 3. Save and restore the A9 power control register also. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00316536 vadc: Remove register setting that not define in specificationSandor Yu2014-06-13
| | | | | | Remove register setting that not define in specification. Signed-off-by: Sandor Yu <R01008@freescale.com>
* net: fec: Add software TSO supportFugang Duan2014-06-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add software TSO support for FEC. This feature allows to improve outbound throughput performance. Tested on imx6dl sabresd board, running iperf tcp tests shows: - 16.2% improvement comparing with FEC SG patch - 82% improvement comparing with NO SG & TSO patch $ ethtool -K eth0 tso on $ iperf -c 10.192.242.167 -t 3 & [ 3] local 10.192.242.108 port 35388 connected with 10.192.242.167 port 5001 [ ID] Interval Transfer Bandwidth [ 3] 0.0- 3.0 sec 181 MBytes 506 Mbits/sec During the testing, CPU loading is 30%. Since imx6dl FEC Bandwidth is limited to SOC system bus bandwidth, the performance with SW TSO is a milestone. CC: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> CC: Eric Dumazet <eric.dumazet@gmail.com> CC: David Laight <David.Laight@ACULAB.COM> CC: Li Frank <B20596@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net> (cherry-pick and merge from linux-net:79f339125ea31)
* net: fec: Add Scatter/gather supportFugang Duan2014-06-13
| | | | | | | | | | | | | | | | | | | | | | | | | Add Scatter/gather support for FEC. This feature allows to improve outbound throughput performance. Tested on imx6dl sabresd board: Running iperf tests shows a 55.4% improvement. $ ethtool -K eth0 sg off $ iperf -c 10.192.242.167 -t 3 & [ 3] local 10.192.242.108 port 52618 connected with 10.192.242.167 port 5001 [ ID] Interval Transfer Bandwidth [ 3] 0.0- 3.0 sec 99.5 MBytes 278 Mbits/sec $ ethtool -K eth0 sg on $ iperf -c 10.192.242.167 -t 3 & [ 3] local 10.192.242.108 port 52617 connected with 10.192.242.167 port 5001 [ ID] Interval Transfer Bandwidth [ 3] 0.0- 3.0 sec 154 MBytes 432 Mbits/sec CC: Li Frank <B20596@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net> (cherry-pick and merge form linux-net: 6e909283cb3)
* net: fec: Enable IP header hardware checksumFugang Duan2014-06-13
| | | | | | | | | | | | | | | | IP header checksum is calcalated by network layer in default. To support software TSO, it is better to use HW calculate the IP header checksum. FEC hw checksum feature request the checksum field in frame is zero, otherwise the calculative CRC is not correct. For segmentated TCP packet, HW calculate the IP header checksum again, it doesn't bring any impact. For SW TSO, HW calculated checksum bring better performance. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: fec: Factorize feature settingFugang Duan2014-06-13
| | | | | | | | In order to enhance the code readable, let's factorize the feature list. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: fec: Factorize the .xmit transmit functionFugang Duan2014-06-13
| | | | | | | | | | | Make the code more readable and easy to support other features like SG, TSO, moving the common transmit function to one api. And the patch also factorize the getting BD index to it own function. CC: David Laight <David.Laight@ACULAB.COM> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* of: set dma_mask to point to coherent_dma_maskRob Herring2014-06-13
| | | | | | | | Platform devices created by DT code don't initialize dma_mask pointer to anything. Set it to coherent_dma_mask by default if the architecture code has not set it. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* net: Add a software TSO helper APIEzequiel Garcia2014-06-13
| | | | | | | | Although the implementation probably needs a lot of work, this initial API allows to implement software TSO in mvneta and mv643xx_eth drivers in a not so intrusive way. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
* ENGR00318207 ARM:imx6x:Busfreq:Fix build warnings in busfreq driver.Ranjani Vaidyanathan2014-06-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following build warnings in busfreq driver: /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq-imx6.c: In function 'imx6_dt_find_ddr_sram': /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq-imx6.c:736:29: warning: assignment makes integer from pointer without a cast [enabled by default] ddr_freq_change_iram_phys = (void *)ddr_iram_addr; ^ CC drivers/base/firmware_class.o /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c: In function 'init_mmdc_ddr3_settings_imx6sx': /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c:404:22: warning: assignment makes pointer from integer without a cast [enabled by default] iram_iomux_settings = ddr_freq_change_iram_base + ddr_code_size; ^ /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c: In function 'init_mmdc_ddr3_settings_imx6q': /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c:539:22: warning: assignment makes pointer from integer without a cast [enabled by default] iram_iomux_settings = ddr_freq_change_iram_base + ddr_code_size; ^ CC arch/arm/mach-imx/busfreq_lpddr2.o /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c: In function 'init_mmdc_lpddr2_settings': /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c:96:2: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement] unsigned long ddr_code_size; ^ /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c:101:3: warning: passing argument 1 of 'memcpy' makes pointer from integer without a cast [enabled by default] mx6_change_lpddr2_freq = (void *)fncpy( Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00317542-2 ARM:dts:imx6x: Allocate 4K of IRAM for DDR freq change code.Ranjani Vaidyanathan2014-06-12
| | | | | | | Allocate 4K of IRAM space for DDR freq change code in the dts files. Also reduce the regular IRAM available for other functions by this amount. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00317542-1 ARM:imx6x: Dynamically calculate the size of low power mode code.Ranjani Vaidyanathan2014-06-12
| | | | | | | | | | | | | This patch adds support for dynamically calculating the size of all low power code (suspend, ddr freq change and low power idle). This allows for easy code changes in the future. This patch also moves the DDR frequency change code from lower 8K of the memory allocated for IRAM page table to regular IRAM. With this the lower 8K of the IRAM page table only contains suspend/resume and low power IDLE code. This gives a little more flexibility to the cdoe size for suspend/resume and low power IDLE. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00317861 ARM: imx: add cpufreq support when VPU running at 352MHzAnson Huang2014-06-11
| | | | | | | | | When VPU 352MHz is supported, PLL2_PFD2 will run at 352MHz instead of 396MHz, CPUFreq driver will use PLL2_PFD2 when it is running at 396MHz setpoint, so when VPU 352MHz is enabled, CPUFreq can be enabled but need to remove the 396MHz setpoint. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00317675-2 ASoC: fsl: cs42xx8: add support for DSP_AShengjiu Wang2014-06-10
| | | | | | Correct the definition of TDM and ONLINE_24 bit Signed-off-by: Shengjiu Wang <b02247@freescale.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-14 10:35:04 -0400