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Diffstat (limited to 'sound/soc/codecs/wm0010.c')
-rw-r--r--sound/soc/codecs/wm0010.c944
1 files changed, 944 insertions, 0 deletions
diff --git a/sound/soc/codecs/wm0010.c b/sound/soc/codecs/wm0010.c
new file mode 100644
index 000000000000..f8d6c31db870
--- /dev/null
+++ b/sound/soc/codecs/wm0010.c
@@ -0,0 +1,944 @@
1/*
2 * wm0010.c -- WM0010 DSP Driver
3 *
4 * Copyright 2012 Wolfson Microelectronics PLC.
5 *
6 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8 * Scott Ling <sl@opensource.wolfsonmicro.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/irqreturn.h>
18#include <linux/init.h>
19#include <linux/spi/spi.h>
20#include <linux/firmware.h>
21#include <linux/delay.h>
22#include <linux/fs.h>
23#include <linux/miscdevice.h>
24#include <linux/gpio.h>
25#include <linux/regulator/consumer.h>
26#include <linux/mutex.h>
27#include <linux/workqueue.h>
28
29#include <sound/soc.h>
30#include <sound/wm0010.h>
31
32#define DEVICE_ID_WM0010 10
33
34enum dfw_cmd {
35 DFW_CMD_FUSE = 0x01,
36 DFW_CMD_CODE_HDR,
37 DFW_CMD_CODE_DATA,
38 DFW_CMD_PLL,
39 DFW_CMD_INFO = 0xff
40};
41
42struct dfw_binrec {
43 u8 command;
44 u32 length:24;
45 u32 address;
46 uint8_t data[0];
47} __packed;
48
49struct dfw_pllrec {
50 u8 command;
51 u32 length:24;
52 u32 address;
53 u32 clkctrl1;
54 u32 clkctrl2;
55 u32 clkctrl3;
56 u32 ldetctrl;
57 u32 uart_div;
58 u32 spi_div;
59} __packed;
60
61static struct pll_clock_map {
62 int max_sysclk;
63 int max_pll_spi_speed;
64 u32 pll_clkctrl1;
65} pll_clock_map[] = { /* Dividers */
66 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */
67 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */
68 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */
69 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */
70 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */
71 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */
72};
73
74enum wm0010_state {
75 WM0010_POWER_OFF,
76 WM0010_OUT_OF_RESET,
77 WM0010_BOOTROM,
78 WM0010_STAGE2,
79 WM0010_FIRMWARE,
80};
81
82struct wm0010_priv {
83 struct snd_soc_codec *codec;
84
85 struct mutex lock;
86 struct device *dev;
87
88 struct wm0010_pdata pdata;
89
90 int gpio_reset;
91 int gpio_reset_value;
92
93 struct regulator_bulk_data core_supplies[2];
94 struct regulator *dbvdd;
95
96 int sysclk;
97
98 enum wm0010_state state;
99 bool boot_failed;
100 int boot_done;
101 bool ready;
102 bool pll_running;
103 int max_spi_freq;
104 int board_max_spi_speed;
105 u32 pll_clkctrl1;
106
107 spinlock_t irq_lock;
108 int irq;
109
110 struct completion boot_completion;
111};
112
113struct wm0010_spi_msg {
114 struct spi_message m;
115 struct spi_transfer t;
116 u8 *tx_buf;
117 u8 *rx_buf;
118 size_t len;
119};
120
121static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = {
122SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0),
123};
124
125static const struct snd_soc_dapm_route wm0010_dapm_routes[] = {
126 { "SDI2 Capture", NULL, "SDI1 Playback" },
127 { "SDI1 Capture", NULL, "SDI2 Playback" },
128
129 { "SDI1 Capture", NULL, "CLKIN" },
130 { "SDI2 Capture", NULL, "CLKIN" },
131 { "SDI1 Playback", NULL, "CLKIN" },
132 { "SDI2 Playback", NULL, "CLKIN" },
133};
134
135static const char *wm0010_state_to_str(enum wm0010_state state)
136{
137 const char *state_to_str[] = {
138 "Power off",
139 "Out of reset",
140 "Boot ROM",
141 "Stage2",
142 "Firmware"
143 };
144
145 if (state < 0 || state >= ARRAY_SIZE(state_to_str))
146 return "null";
147 return state_to_str[state];
148}
149
150/* Called with wm0010->lock held */
151static void wm0010_halt(struct snd_soc_codec *codec)
152{
153 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
154 unsigned long flags;
155 enum wm0010_state state;
156
157 /* Fetch the wm0010 state */
158 spin_lock_irqsave(&wm0010->irq_lock, flags);
159 state = wm0010->state;
160 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
161
162 switch (state) {
163 case WM0010_POWER_OFF:
164 /* If there's nothing to do, bail out */
165 return;
166 case WM0010_OUT_OF_RESET:
167 case WM0010_BOOTROM:
168 case WM0010_STAGE2:
169 case WM0010_FIRMWARE:
170 /* Remember to put chip back into reset */
171 gpio_set_value(wm0010->gpio_reset, wm0010->gpio_reset_value);
172 /* Disable the regulators */
173 regulator_disable(wm0010->dbvdd);
174 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
175 wm0010->core_supplies);
176 break;
177 }
178
179 spin_lock_irqsave(&wm0010->irq_lock, flags);
180 wm0010->state = WM0010_POWER_OFF;
181 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
182}
183
184struct wm0010_boot_xfer {
185 struct list_head list;
186 struct snd_soc_codec *codec;
187 struct completion *done;
188 struct spi_message m;
189 struct spi_transfer t;
190};
191
192/* Called with wm0010->lock held */
193static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010)
194{
195 enum wm0010_state state;
196 unsigned long flags;
197
198 spin_lock_irqsave(&wm0010->irq_lock, flags);
199 state = wm0010->state;
200 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
201
202 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n",
203 wm0010_state_to_str(state), wm0010_state_to_str(state + 1));
204
205 wm0010->boot_failed = true;
206}
207
208static void wm0010_boot_xfer_complete(void *data)
209{
210 struct wm0010_boot_xfer *xfer = data;
211 struct snd_soc_codec *codec = xfer->codec;
212 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
213 u32 *out32 = xfer->t.rx_buf;
214 int i;
215
216 if (xfer->m.status != 0) {
217 dev_err(codec->dev, "SPI transfer failed: %d\n",
218 xfer->m.status);
219 wm0010_mark_boot_failure(wm0010);
220 if (xfer->done)
221 complete(xfer->done);
222 return;
223 }
224
225 for (i = 0; i < xfer->t.len / 4; i++) {
226 dev_dbg(codec->dev, "%d: %04x\n", i, out32[i]);
227
228 switch (be32_to_cpu(out32[i])) {
229 case 0xe0e0e0e0:
230 dev_err(codec->dev,
231 "%d: ROM error reported in stage 2\n", i);
232 wm0010_mark_boot_failure(wm0010);
233 break;
234
235 case 0x55555555:
236 if (wm0010->boot_done == 0)
237 break;
238 dev_err(codec->dev,
239 "%d: ROM bootloader running in stage 2\n", i);
240 wm0010_mark_boot_failure(wm0010);
241 break;
242
243 case 0x0fed0000:
244 dev_dbg(codec->dev, "Stage2 loader running\n");
245 break;
246
247 case 0x0fed0007:
248 dev_dbg(codec->dev, "CODE_HDR packet received\n");
249 break;
250
251 case 0x0fed0008:
252 dev_dbg(codec->dev, "CODE_DATA packet received\n");
253 break;
254
255 case 0x0fed0009:
256 dev_dbg(codec->dev, "Download complete\n");
257 break;
258
259 case 0x0fed000c:
260 dev_dbg(codec->dev, "Application start\n");
261 break;
262
263 case 0x0fed000e:
264 dev_dbg(codec->dev, "PLL packet received\n");
265 wm0010->pll_running = true;
266 break;
267
268 case 0x0fed0025:
269 dev_err(codec->dev, "Device reports image too long\n");
270 wm0010_mark_boot_failure(wm0010);
271 break;
272
273 case 0x0fed002c:
274 dev_err(codec->dev, "Device reports bad SPI packet\n");
275 wm0010_mark_boot_failure(wm0010);
276 break;
277
278 case 0x0fed0031:
279 dev_err(codec->dev, "Device reports SPI read overflow\n");
280 wm0010_mark_boot_failure(wm0010);
281 break;
282
283 case 0x0fed0032:
284 dev_err(codec->dev, "Device reports SPI underclock\n");
285 wm0010_mark_boot_failure(wm0010);
286 break;
287
288 case 0x0fed0033:
289 dev_err(codec->dev, "Device reports bad header packet\n");
290 wm0010_mark_boot_failure(wm0010);
291 break;
292
293 case 0x0fed0034:
294 dev_err(codec->dev, "Device reports invalid packet type\n");
295 wm0010_mark_boot_failure(wm0010);
296 break;
297
298 case 0x0fed0035:
299 dev_err(codec->dev, "Device reports data before header error\n");
300 wm0010_mark_boot_failure(wm0010);
301 break;
302
303 case 0x0fed0038:
304 dev_err(codec->dev, "Device reports invalid PLL packet\n");
305 break;
306
307 case 0x0fed003a:
308 dev_err(codec->dev, "Device reports packet alignment error\n");
309 wm0010_mark_boot_failure(wm0010);
310 break;
311
312 default:
313 dev_err(codec->dev, "Unrecognised return 0x%x\n",
314 be32_to_cpu(out32[i]));
315 wm0010_mark_boot_failure(wm0010);
316 break;
317 }
318
319 if (wm0010->boot_failed)
320 break;
321 }
322
323 wm0010->boot_done++;
324 if (xfer->done)
325 complete(xfer->done);
326}
327
328static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len)
329{
330 int i;
331
332 for (i = 0; i < len / 8; i++)
333 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i]));
334}
335
336static int wm0010_boot(struct snd_soc_codec *codec)
337{
338 struct spi_device *spi = to_spi_device(codec->dev);
339 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
340 unsigned long flags;
341 struct list_head xfer_list;
342 struct wm0010_boot_xfer *xfer;
343 int ret;
344 struct completion done;
345 const struct firmware *fw;
346 const struct dfw_binrec *rec;
347 struct spi_message m;
348 struct spi_transfer t;
349 struct dfw_pllrec pll_rec;
350 u32 *img, *p;
351 u64 *img_swap;
352 u8 *out;
353 u32 len, offset;
354 int i;
355
356 spin_lock_irqsave(&wm0010->irq_lock, flags);
357 if (wm0010->state != WM0010_POWER_OFF)
358 dev_warn(wm0010->dev, "DSP already powered up!\n");
359 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
360
361 if (wm0010->sysclk > 26000000) {
362 dev_err(codec->dev, "Max DSP clock frequency is 26MHz\n");
363 ret = -ECANCELED;
364 goto err;
365 }
366
367 INIT_LIST_HEAD(&xfer_list);
368
369 mutex_lock(&wm0010->lock);
370 wm0010->pll_running = false;
371
372 dev_dbg(codec->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
373
374 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
375 wm0010->core_supplies);
376 if (ret != 0) {
377 dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
378 ret);
379 mutex_unlock(&wm0010->lock);
380 goto err;
381 }
382
383 ret = regulator_enable(wm0010->dbvdd);
384 if (ret != 0) {
385 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
386 goto err_core;
387 }
388
389 /* Release reset */
390 gpio_set_value(wm0010->gpio_reset, !wm0010->gpio_reset_value);
391 spin_lock_irqsave(&wm0010->irq_lock, flags);
392 wm0010->state = WM0010_OUT_OF_RESET;
393 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
394
395 /* First the bootloader */
396 ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev);
397 if (ret != 0) {
398 dev_err(codec->dev, "Failed to request stage2 loader: %d\n",
399 ret);
400 goto abort;
401 }
402
403 if (!wait_for_completion_timeout(&wm0010->boot_completion,
404 msecs_to_jiffies(10)))
405 dev_err(codec->dev, "Failed to get interrupt from DSP\n");
406
407 spin_lock_irqsave(&wm0010->irq_lock, flags);
408 wm0010->state = WM0010_BOOTROM;
409 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
410
411 dev_dbg(codec->dev, "Downloading %zu byte stage 2 loader\n", fw->size);
412
413 /* Copy to local buffer first as vmalloc causes problems for dma */
414 img = kzalloc(fw->size, GFP_KERNEL);
415 if (!img) {
416 dev_err(codec->dev, "Failed to allocate image buffer\n");
417 goto abort;
418 }
419
420 out = kzalloc(fw->size, GFP_KERNEL);
421 if (!out) {
422 dev_err(codec->dev, "Failed to allocate output buffer\n");
423 goto abort;
424 }
425
426 memcpy(img, &fw->data[0], fw->size);
427
428 spi_message_init(&m);
429 memset(&t, 0, sizeof(t));
430 t.rx_buf = out;
431 t.tx_buf = img;
432 t.len = fw->size;
433 t.bits_per_word = 8;
434 t.speed_hz = wm0010->sysclk / 10;
435 spi_message_add_tail(&t, &m);
436
437 dev_dbg(codec->dev, "Starting initial download at %dHz\n",
438 t.speed_hz);
439
440 ret = spi_sync(spi, &m);
441 if (ret != 0) {
442 dev_err(codec->dev, "Initial download failed: %d\n", ret);
443 goto abort;
444 }
445
446 /* Look for errors from the boot ROM */
447 for (i = 0; i < fw->size; i++) {
448 if (out[i] != 0x55) {
449 ret = -EBUSY;
450 dev_err(codec->dev, "Boot ROM error: %x in %d\n",
451 out[i], i);
452 wm0010_mark_boot_failure(wm0010);
453 goto abort;
454 }
455 }
456
457 release_firmware(fw);
458 kfree(img);
459 kfree(out);
460
461 if (!wait_for_completion_timeout(&wm0010->boot_completion,
462 msecs_to_jiffies(10)))
463 dev_err(codec->dev, "Failed to get interrupt from DSP loader.\n");
464
465 spin_lock_irqsave(&wm0010->irq_lock, flags);
466 wm0010->state = WM0010_STAGE2;
467 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
468
469 /* Only initialise PLL if max_spi_freq initialised */
470 if (wm0010->max_spi_freq) {
471
472 /* Initialise a PLL record */
473 memset(&pll_rec, 0, sizeof(pll_rec));
474 pll_rec.command = DFW_CMD_PLL;
475 pll_rec.length = (sizeof(pll_rec) - 8);
476
477 /* On wm0010 only the CLKCTRL1 value is used */
478 pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
479
480 len = pll_rec.length + 8;
481 out = kzalloc(len, GFP_KERNEL);
482 if (!out) {
483 dev_err(codec->dev,
484 "Failed to allocate RX buffer\n");
485 goto abort;
486 }
487
488 img_swap = kzalloc(len, GFP_KERNEL);
489 if (!img_swap) {
490 dev_err(codec->dev,
491 "Failed to allocate image buffer\n");
492 goto abort;
493 }
494
495 /* We need to re-order for 0010 */
496 byte_swap_64((u64 *)&pll_rec, img_swap, len);
497
498 spi_message_init(&m);
499 memset(&t, 0, sizeof(t));
500 t.rx_buf = out;
501 t.tx_buf = img_swap;
502 t.len = len;
503 t.bits_per_word = 8;
504 t.speed_hz = wm0010->sysclk / 6;
505 spi_message_add_tail(&t, &m);
506
507 ret = spi_sync(spi, &m);
508 if (ret != 0) {
509 dev_err(codec->dev, "First PLL write failed: %d\n", ret);
510 goto abort;
511 }
512
513 /* Use a second send of the message to get the return status */
514 ret = spi_sync(spi, &m);
515 if (ret != 0) {
516 dev_err(codec->dev, "Second PLL write failed: %d\n", ret);
517 goto abort;
518 }
519
520 p = (u32 *)out;
521
522 /* Look for PLL active code from the DSP */
523 for (i = 0; i < len / 4; i++) {
524 if (*p == 0x0e00ed0f) {
525 dev_dbg(codec->dev, "PLL packet received\n");
526 wm0010->pll_running = true;
527 break;
528 }
529 p++;
530 }
531
532 kfree(img_swap);
533 kfree(out);
534 } else
535 dev_dbg(codec->dev, "Not enabling DSP PLL.");
536
537 ret = request_firmware(&fw, "wm0010.dfw", codec->dev);
538 if (ret != 0) {
539 dev_err(codec->dev, "Failed to request application: %d\n",
540 ret);
541 goto abort;
542 }
543
544 rec = (const struct dfw_binrec *)fw->data;
545 offset = 0;
546 wm0010->boot_done = 0;
547 wm0010->boot_failed = false;
548 BUG_ON(!list_empty(&xfer_list));
549 init_completion(&done);
550
551 /* First record should be INFO */
552 if (rec->command != DFW_CMD_INFO) {
553 dev_err(codec->dev, "First record not INFO\r\n");
554 goto abort;
555 }
556
557 /* Check it's a 0010 file */
558 if (rec->data[0] != DEVICE_ID_WM0010) {
559 dev_err(codec->dev, "Not a WM0010 firmware file.\r\n");
560 goto abort;
561 }
562
563 /* Skip the info record as we don't need to send it */
564 offset += ((rec->length) + 8);
565 rec = (void *)&rec->data[rec->length];
566
567 while (offset < fw->size) {
568 dev_dbg(codec->dev,
569 "Packet: command %d, data length = 0x%x\r\n",
570 rec->command, rec->length);
571 len = rec->length + 8;
572
573 out = kzalloc(len, GFP_KERNEL);
574 if (!out) {
575 dev_err(codec->dev,
576 "Failed to allocate RX buffer\n");
577 goto abort;
578 }
579
580 img_swap = kzalloc(len, GFP_KERNEL);
581 if (!img_swap) {
582 dev_err(codec->dev,
583 "Failed to allocate image buffer\n");
584 goto abort;
585 }
586
587 /* We need to re-order for 0010 */
588 byte_swap_64((u64 *)&rec->command, img_swap, len);
589
590 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
591 if (!xfer) {
592 dev_err(codec->dev, "Failed to allocate xfer\n");
593 goto abort;
594 }
595
596 xfer->codec = codec;
597 list_add_tail(&xfer->list, &xfer_list);
598
599 spi_message_init(&xfer->m);
600 xfer->m.complete = wm0010_boot_xfer_complete;
601 xfer->m.context = xfer;
602 xfer->t.tx_buf = img_swap;
603 xfer->t.rx_buf = out;
604 xfer->t.len = len;
605 xfer->t.bits_per_word = 8;
606
607 if (!wm0010->pll_running) {
608 xfer->t.speed_hz = wm0010->sysclk / 6;
609 } else {
610 xfer->t.speed_hz = wm0010->max_spi_freq;
611
612 if (wm0010->board_max_spi_speed &&
613 (wm0010->board_max_spi_speed < wm0010->max_spi_freq))
614 xfer->t.speed_hz = wm0010->board_max_spi_speed;
615 }
616
617 /* Store max usable spi frequency for later use */
618 wm0010->max_spi_freq = xfer->t.speed_hz;
619
620 spi_message_add_tail(&xfer->t, &xfer->m);
621
622 offset += ((rec->length) + 8);
623 rec = (void *)&rec->data[rec->length];
624
625 if (offset >= fw->size) {
626 dev_dbg(codec->dev, "All transfers scheduled\n");
627 xfer->done = &done;
628 }
629
630 ret = spi_async(spi, &xfer->m);
631 if (ret != 0) {
632 dev_err(codec->dev, "Write failed: %d\n", ret);
633 goto abort;
634 }
635
636 if (wm0010->boot_failed)
637 goto abort;
638 }
639
640 wait_for_completion(&done);
641
642 spin_lock_irqsave(&wm0010->irq_lock, flags);
643 wm0010->state = WM0010_FIRMWARE;
644 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
645
646 mutex_unlock(&wm0010->lock);
647
648 release_firmware(fw);
649
650 while (!list_empty(&xfer_list)) {
651 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer,
652 list);
653 kfree(xfer->t.rx_buf);
654 kfree(xfer->t.tx_buf);
655 list_del(&xfer->list);
656 kfree(xfer);
657 }
658
659 return 0;
660
661abort:
662 /* Put the chip back into reset */
663 wm0010_halt(codec);
664 mutex_unlock(&wm0010->lock);
665 return ret;
666
667err_core:
668 mutex_unlock(&wm0010->lock);
669 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
670 wm0010->core_supplies);
671err:
672 return ret;
673}
674
675static int wm0010_set_bias_level(struct snd_soc_codec *codec,
676 enum snd_soc_bias_level level)
677{
678 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
679
680 switch (level) {
681 case SND_SOC_BIAS_ON:
682 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
683 wm0010_boot(codec);
684 break;
685 case SND_SOC_BIAS_PREPARE:
686 break;
687 case SND_SOC_BIAS_STANDBY:
688 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) {
689 mutex_lock(&wm0010->lock);
690 wm0010_halt(codec);
691 mutex_unlock(&wm0010->lock);
692 }
693 break;
694 case SND_SOC_BIAS_OFF:
695 break;
696 }
697
698 codec->dapm.bias_level = level;
699
700 return 0;
701}
702
703static int wm0010_set_sysclk(struct snd_soc_codec *codec, int source,
704 int clk_id, unsigned int freq, int dir)
705{
706 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
707 unsigned int i;
708
709 wm0010->sysclk = freq;
710
711 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) {
712 wm0010->max_spi_freq = 0;
713 } else {
714 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++)
715 if (freq >= pll_clock_map[i].max_sysclk)
716 break;
717
718 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed;
719 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1;
720 }
721
722 return 0;
723}
724
725static int wm0010_probe(struct snd_soc_codec *codec);
726
727static struct snd_soc_codec_driver soc_codec_dev_wm0010 = {
728 .probe = wm0010_probe,
729 .set_bias_level = wm0010_set_bias_level,
730 .set_sysclk = wm0010_set_sysclk,
731 .idle_bias_off = true,
732
733 .dapm_widgets = wm0010_dapm_widgets,
734 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets),
735 .dapm_routes = wm0010_dapm_routes,
736 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes),
737};
738
739#define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
740#define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
741 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
742 SNDRV_PCM_FMTBIT_S32_LE)
743
744static struct snd_soc_dai_driver wm0010_dai[] = {
745 {
746 .name = "wm0010-sdi1",
747 .playback = {
748 .stream_name = "SDI1 Playback",
749 .channels_min = 1,
750 .channels_max = 2,
751 .rates = WM0010_RATES,
752 .formats = WM0010_FORMATS,
753 },
754 .capture = {
755 .stream_name = "SDI1 Capture",
756 .channels_min = 1,
757 .channels_max = 2,
758 .rates = WM0010_RATES,
759 .formats = WM0010_FORMATS,
760 },
761 },
762 {
763 .name = "wm0010-sdi2",
764 .playback = {
765 .stream_name = "SDI2 Playback",
766 .channels_min = 1,
767 .channels_max = 2,
768 .rates = WM0010_RATES,
769 .formats = WM0010_FORMATS,
770 },
771 .capture = {
772 .stream_name = "SDI2 Capture",
773 .channels_min = 1,
774 .channels_max = 2,
775 .rates = WM0010_RATES,
776 .formats = WM0010_FORMATS,
777 },
778 },
779};
780
781static irqreturn_t wm0010_irq(int irq, void *data)
782{
783 struct wm0010_priv *wm0010 = data;
784
785 switch (wm0010->state) {
786 case WM0010_POWER_OFF:
787 case WM0010_OUT_OF_RESET:
788 case WM0010_BOOTROM:
789 case WM0010_STAGE2:
790 spin_lock(&wm0010->irq_lock);
791 complete(&wm0010->boot_completion);
792 spin_unlock(&wm0010->irq_lock);
793 return IRQ_HANDLED;
794 default:
795 return IRQ_NONE;
796 }
797
798 return IRQ_NONE;
799}
800
801static int wm0010_probe(struct snd_soc_codec *codec)
802{
803 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
804
805 wm0010->codec = codec;
806
807 return 0;
808}
809
810static int __devinit wm0010_spi_probe(struct spi_device *spi)
811{
812 unsigned long flags;
813 unsigned long gpio_flags;
814 int ret;
815 int trigger;
816 int irq;
817 struct wm0010_priv *wm0010;
818
819 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010),
820 GFP_KERNEL);
821 if (!wm0010)
822 return -ENOMEM;
823
824 mutex_init(&wm0010->lock);
825 spin_lock_init(&wm0010->irq_lock);
826
827 spi_set_drvdata(spi, wm0010);
828 wm0010->dev = &spi->dev;
829
830 if (dev_get_platdata(&spi->dev))
831 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev),
832 sizeof(wm0010->pdata));
833
834 init_completion(&wm0010->boot_completion);
835
836 wm0010->core_supplies[0].supply = "AVDD";
837 wm0010->core_supplies[1].supply = "DCVDD";
838 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies),
839 wm0010->core_supplies);
840 if (ret != 0) {
841 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n",
842 ret);
843 return ret;
844 }
845
846 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD");
847 if (IS_ERR(wm0010->dbvdd)) {
848 ret = PTR_ERR(wm0010->dbvdd);
849 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret);
850 return ret;
851 }
852
853 if (wm0010->pdata.gpio_reset) {
854 wm0010->gpio_reset = wm0010->pdata.gpio_reset;
855
856 if (wm0010->pdata.reset_active_high)
857 wm0010->gpio_reset_value = 1;
858 else
859 wm0010->gpio_reset_value = 0;
860
861 if (wm0010->gpio_reset_value)
862 gpio_flags = GPIOF_OUT_INIT_HIGH;
863 else
864 gpio_flags = GPIOF_OUT_INIT_LOW;
865
866 ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset,
867 gpio_flags, "wm0010 reset");
868 if (ret < 0) {
869 dev_err(wm0010->dev,
870 "Failed to request GPIO for DSP reset: %d\n",
871 ret);
872 return ret;
873 }
874 } else {
875 dev_err(wm0010->dev, "No reset GPIO configured\n");
876 return -EINVAL;
877 }
878
879 irq = spi->irq;
880 if (wm0010->pdata.irq_flags)
881 trigger = wm0010->pdata.irq_flags;
882 else
883 trigger = IRQF_TRIGGER_FALLING;
884 trigger |= IRQF_ONESHOT;
885
886 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger | IRQF_ONESHOT,
887 "wm0010", wm0010);
888 if (ret) {
889 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n",
890 irq, ret);
891 return ret;
892 }
893 wm0010->irq = irq;
894
895 if (spi->max_speed_hz)
896 wm0010->board_max_spi_speed = spi->max_speed_hz;
897 else
898 wm0010->board_max_spi_speed = 0;
899
900 spin_lock_irqsave(&wm0010->irq_lock, flags);
901 wm0010->state = WM0010_POWER_OFF;
902 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
903
904 ret = snd_soc_register_codec(&spi->dev,
905 &soc_codec_dev_wm0010, wm0010_dai,
906 ARRAY_SIZE(wm0010_dai));
907 if (ret < 0)
908 return ret;
909
910 return 0;
911}
912
913static int __devexit wm0010_spi_remove(struct spi_device *spi)
914{
915 struct wm0010_priv *wm0010 = spi_get_drvdata(spi);
916
917 snd_soc_unregister_codec(&spi->dev);
918
919 if (wm0010->gpio_reset) {
920 /* Remember to put chip back into reset */
921 gpio_set_value(wm0010->gpio_reset, wm0010->gpio_reset_value);
922 }
923
924 if (wm0010->irq)
925 free_irq(wm0010->irq, wm0010);
926
927 return 0;
928}
929
930static struct spi_driver wm0010_spi_driver = {
931 .driver = {
932 .name = "wm0010",
933 .bus = &spi_bus_type,
934 .owner = THIS_MODULE,
935 },
936 .probe = wm0010_spi_probe,
937 .remove = __devexit_p(wm0010_spi_remove),
938};
939
940module_spi_driver(wm0010_spi_driver);
941
942MODULE_DESCRIPTION("ASoC WM0010 driver");
943MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
944MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 02:42:27 -0500