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-rw-r--r--net/dsa/mv88e6123_61_65.c447
1 files changed, 0 insertions, 447 deletions
diff --git a/net/dsa/mv88e6123_61_65.c b/net/dsa/mv88e6123_61_65.c
deleted file mode 100644
index 52faaa21a4d9..000000000000
--- a/net/dsa/mv88e6123_61_65.c
+++ /dev/null
@@ -1,447 +0,0 @@
1/*
2 * net/dsa/mv88e6123_61_65.c - Marvell 88e6123/6161/6165 switch chip support
3 * Copyright (c) 2008-2009 Marvell Semiconductor
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11#include <linux/list.h>
12#include <linux/netdevice.h>
13#include <linux/phy.h>
14#include "dsa_priv.h"
15#include "mv88e6xxx.h"
16
17static char *mv88e6123_61_65_probe(struct mii_bus *bus, int sw_addr)
18{
19 int ret;
20
21 ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
22 if (ret >= 0) {
23 ret &= 0xfff0;
24 if (ret == 0x1210)
25 return "Marvell 88E6123";
26 if (ret == 0x1610)
27 return "Marvell 88E6161";
28 if (ret == 0x1650)
29 return "Marvell 88E6165";
30 }
31
32 return NULL;
33}
34
35static int mv88e6123_61_65_switch_reset(struct dsa_switch *ds)
36{
37 int i;
38 int ret;
39
40 /*
41 * Set all ports to the disabled state.
42 */
43 for (i = 0; i < 8; i++) {
44 ret = REG_READ(REG_PORT(i), 0x04);
45 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
46 }
47
48 /*
49 * Wait for transmit queues to drain.
50 */
51 msleep(2);
52
53 /*
54 * Reset the switch.
55 */
56 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
57
58 /*
59 * Wait up to one second for reset to complete.
60 */
61 for (i = 0; i < 1000; i++) {
62 ret = REG_READ(REG_GLOBAL, 0x00);
63 if ((ret & 0xc800) == 0xc800)
64 break;
65
66 msleep(1);
67 }
68 if (i == 1000)
69 return -ETIMEDOUT;
70
71 return 0;
72}
73
74static int mv88e6123_61_65_setup_global(struct dsa_switch *ds)
75{
76 int ret;
77 int i;
78
79 /*
80 * Disable the PHY polling unit (since there won't be any
81 * external PHYs to poll), don't discard packets with
82 * excessive collisions, and mask all interrupt sources.
83 */
84 REG_WRITE(REG_GLOBAL, 0x04, 0x0000);
85
86 /*
87 * Set the default address aging time to 5 minutes, and
88 * enable address learn messages to be sent to all message
89 * ports.
90 */
91 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
92
93 /*
94 * Configure the priority mapping registers.
95 */
96 ret = mv88e6xxx_config_prio(ds);
97 if (ret < 0)
98 return ret;
99
100 /*
101 * Configure the upstream port, and configure the upstream
102 * port as the port to which ingress and egress monitor frames
103 * are to be sent.
104 */
105 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110));
106
107 /*
108 * Disable remote management for now, and set the switch's
109 * DSA device number.
110 */
111 REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);
112
113 /*
114 * Send all frames with destination addresses matching
115 * 01:80:c2:00:00:2x to the CPU port.
116 */
117 REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);
118
119 /*
120 * Send all frames with destination addresses matching
121 * 01:80:c2:00:00:0x to the CPU port.
122 */
123 REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
124
125 /*
126 * Disable the loopback filter, disable flow control
127 * messages, disable flood broadcast override, disable
128 * removing of provider tags, disable ATU age violation
129 * interrupts, disable tag flow control, force flow
130 * control priority to the highest, and send all special
131 * multicast frames to the CPU at the highest priority.
132 */
133 REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
134
135 /*
136 * Program the DSA routing table.
137 */
138 for (i = 0; i < 32; i++) {
139 int nexthop;
140
141 nexthop = 0x1f;
142 if (i != ds->index && i < ds->dst->pd->nr_chips)
143 nexthop = ds->pd->rtable[i] & 0x1f;
144
145 REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
146 }
147
148 /*
149 * Clear all trunk masks.
150 */
151 for (i = 0; i < 8; i++)
152 REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff);
153
154 /*
155 * Clear all trunk mappings.
156 */
157 for (i = 0; i < 16; i++)
158 REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));
159
160 /*
161 * Disable ingress rate limiting by resetting all ingress
162 * rate limit registers to their initial state.
163 */
164 for (i = 0; i < 6; i++)
165 REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8));
166
167 /*
168 * Initialise cross-chip port VLAN table to reset defaults.
169 */
170 REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);
171
172 /*
173 * Clear the priority override table.
174 */
175 for (i = 0; i < 16; i++)
176 REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8));
177
178 /* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */
179
180 return 0;
181}
182
183static int mv88e6123_61_65_setup_port(struct dsa_switch *ds, int p)
184{
185 int addr = REG_PORT(p);
186 u16 val;
187
188 /*
189 * MAC Forcing register: don't force link, speed, duplex
190 * or flow control state to any particular values on physical
191 * ports, but force the CPU port and all DSA ports to 1000 Mb/s
192 * full duplex.
193 */
194 if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
195 REG_WRITE(addr, 0x01, 0x003e);
196 else
197 REG_WRITE(addr, 0x01, 0x0003);
198
199 /*
200 * Do not limit the period of time that this port can be
201 * paused for by the remote end or the period of time that
202 * this port can pause the remote end.
203 */
204 REG_WRITE(addr, 0x02, 0x0000);
205
206 /*
207 * Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
208 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
209 * tunneling, determine priority by looking at 802.1p and IP
210 * priority fields (IP prio has precedence), and set STP state
211 * to Forwarding.
212 *
213 * If this is the CPU link, use DSA or EDSA tagging depending
214 * on which tagging mode was configured.
215 *
216 * If this is a link to another switch, use DSA tagging mode.
217 *
218 * If this is the upstream port for this switch, enable
219 * forwarding of unknown unicasts and multicasts.
220 */
221 val = 0x0433;
222 if (dsa_is_cpu_port(ds, p)) {
223 if (ds->dst->tag_protocol == htons(ETH_P_EDSA))
224 val |= 0x3300;
225 else
226 val |= 0x0100;
227 }
228 if (ds->dsa_port_mask & (1 << p))
229 val |= 0x0100;
230 if (p == dsa_upstream_port(ds))
231 val |= 0x000c;
232 REG_WRITE(addr, 0x04, val);
233
234 /*
235 * Port Control 1: disable trunking. Also, if this is the
236 * CPU port, enable learn messages to be sent to this port.
237 */
238 REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
239
240 /*
241 * Port based VLAN map: give each port its own address
242 * database, allow the CPU port to talk to each of the 'real'
243 * ports, and allow each of the 'real' ports to only talk to
244 * the upstream port.
245 */
246 val = (p & 0xf) << 12;
247 if (dsa_is_cpu_port(ds, p))
248 val |= ds->phys_port_mask;
249 else
250 val |= 1 << dsa_upstream_port(ds);
251 REG_WRITE(addr, 0x06, val);
252
253 /*
254 * Default VLAN ID and priority: don't set a default VLAN
255 * ID, and set the default packet priority to zero.
256 */
257 REG_WRITE(addr, 0x07, 0x0000);
258
259 /*
260 * Port Control 2: don't force a good FCS, set the maximum
261 * frame size to 10240 bytes, don't let the switch add or
262 * strip 802.1q tags, don't discard tagged or untagged frames
263 * on this port, do a destination address lookup on all
264 * received packets as usual, disable ARP mirroring and don't
265 * send a copy of all transmitted/received frames on this port
266 * to the CPU.
267 */
268 REG_WRITE(addr, 0x08, 0x2080);
269
270 /*
271 * Egress rate control: disable egress rate control.
272 */
273 REG_WRITE(addr, 0x09, 0x0001);
274
275 /*
276 * Egress rate control 2: disable egress rate control.
277 */
278 REG_WRITE(addr, 0x0a, 0x0000);
279
280 /*
281 * Port Association Vector: when learning source addresses
282 * of packets, add the address to the address database using
283 * a port bitmap that has only the bit for this port set and
284 * the other bits clear.
285 */
286 REG_WRITE(addr, 0x0b, 1 << p);
287
288 /*
289 * Port ATU control: disable limiting the number of address
290 * database entries that this port is allowed to use.
291 */
292 REG_WRITE(addr, 0x0c, 0x0000);
293
294 /*
295 * Priorit Override: disable DA, SA and VTU priority override.
296 */
297 REG_WRITE(addr, 0x0d, 0x0000);
298
299 /*
300 * Port Ethertype: use the Ethertype DSA Ethertype value.
301 */
302 REG_WRITE(addr, 0x0f, ETH_P_EDSA);
303
304 /*
305 * Tag Remap: use an identity 802.1p prio -> switch prio
306 * mapping.
307 */
308 REG_WRITE(addr, 0x18, 0x3210);
309
310 /*
311 * Tag Remap 2: use an identity 802.1p prio -> switch prio
312 * mapping.
313 */
314 REG_WRITE(addr, 0x19, 0x7654);
315
316 return 0;
317}
318
319static int mv88e6123_61_65_setup(struct dsa_switch *ds)
320{
321 struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
322 int i;
323 int ret;
324
325 mutex_init(&ps->smi_mutex);
326 mutex_init(&ps->stats_mutex);
327
328 ret = mv88e6123_61_65_switch_reset(ds);
329 if (ret < 0)
330 return ret;
331
332 /* @@@ initialise vtu and atu */
333
334 ret = mv88e6123_61_65_setup_global(ds);
335 if (ret < 0)
336 return ret;
337
338 for (i = 0; i < 6; i++) {
339 ret = mv88e6123_61_65_setup_port(ds, i);
340 if (ret < 0)
341 return ret;
342 }
343
344 return 0;
345}
346
347static int mv88e6123_61_65_port_to_phy_addr(int port)
348{
349 if (port >= 0 && port <= 4)
350 return port;
351 return -1;
352}
353
354static int
355mv88e6123_61_65_phy_read(struct dsa_switch *ds, int port, int regnum)
356{
357 int addr = mv88e6123_61_65_port_to_phy_addr(port);
358 return mv88e6xxx_phy_read(ds, addr, regnum);
359}
360
361static int
362mv88e6123_61_65_phy_write(struct dsa_switch *ds,
363 int port, int regnum, u16 val)
364{
365 int addr = mv88e6123_61_65_port_to_phy_addr(port);
366 return mv88e6xxx_phy_write(ds, addr, regnum, val);
367}
368
369static struct mv88e6xxx_hw_stat mv88e6123_61_65_hw_stats[] = {
370 { "in_good_octets", 8, 0x00, },
371 { "in_bad_octets", 4, 0x02, },
372 { "in_unicast", 4, 0x04, },
373 { "in_broadcasts", 4, 0x06, },
374 { "in_multicasts", 4, 0x07, },
375 { "in_pause", 4, 0x16, },
376 { "in_undersize", 4, 0x18, },
377 { "in_fragments", 4, 0x19, },
378 { "in_oversize", 4, 0x1a, },
379 { "in_jabber", 4, 0x1b, },
380 { "in_rx_error", 4, 0x1c, },
381 { "in_fcs_error", 4, 0x1d, },
382 { "out_octets", 8, 0x0e, },
383 { "out_unicast", 4, 0x10, },
384 { "out_broadcasts", 4, 0x13, },
385 { "out_multicasts", 4, 0x12, },
386 { "out_pause", 4, 0x15, },
387 { "excessive", 4, 0x11, },
388 { "collisions", 4, 0x1e, },
389 { "deferred", 4, 0x05, },
390 { "single", 4, 0x14, },
391 { "multiple", 4, 0x17, },
392 { "out_fcs_error", 4, 0x03, },
393 { "late", 4, 0x1f, },
394 { "hist_64bytes", 4, 0x08, },
395 { "hist_65_127bytes", 4, 0x09, },
396 { "hist_128_255bytes", 4, 0x0a, },
397 { "hist_256_511bytes", 4, 0x0b, },
398 { "hist_512_1023bytes", 4, 0x0c, },
399 { "hist_1024_max_bytes", 4, 0x0d, },
400};
401
402static void
403mv88e6123_61_65_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
404{
405 mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6123_61_65_hw_stats),
406 mv88e6123_61_65_hw_stats, port, data);
407}
408
409static void
410mv88e6123_61_65_get_ethtool_stats(struct dsa_switch *ds,
411 int port, uint64_t *data)
412{
413 mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6123_61_65_hw_stats),
414 mv88e6123_61_65_hw_stats, port, data);
415}
416
417static int mv88e6123_61_65_get_sset_count(struct dsa_switch *ds)
418{
419 return ARRAY_SIZE(mv88e6123_61_65_hw_stats);
420}
421
422static struct dsa_switch_driver mv88e6123_61_65_switch_driver = {
423 .tag_protocol = cpu_to_be16(ETH_P_EDSA),
424 .priv_size = sizeof(struct mv88e6xxx_priv_state),
425 .probe = mv88e6123_61_65_probe,
426 .setup = mv88e6123_61_65_setup,
427 .set_addr = mv88e6xxx_set_addr_indirect,
428 .phy_read = mv88e6123_61_65_phy_read,
429 .phy_write = mv88e6123_61_65_phy_write,
430 .poll_link = mv88e6xxx_poll_link,
431 .get_strings = mv88e6123_61_65_get_strings,
432 .get_ethtool_stats = mv88e6123_61_65_get_ethtool_stats,
433 .get_sset_count = mv88e6123_61_65_get_sset_count,
434};
435
436static int __init mv88e6123_61_65_init(void)
437{
438 register_switch_driver(&mv88e6123_61_65_switch_driver);
439 return 0;
440}
441module_init(mv88e6123_61_65_init);
442
443static void __exit mv88e6123_61_65_cleanup(void)
444{
445 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
446}
447module_exit(mv88e6123_61_65_cleanup);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 09:03:46 -0500