litmus-rt-imx6.git - LITMUS^RT and MC^2 V1 support for the i.MX6 processor family.

diff options

Diffstat (limited to 'kernel/auditsc.c')

-rw-r--r--

1 files changed, 4 insertions, 10 deletions

  * Add a name to the list of audit names for this context.
  * Called from fs/namei.c:getname().
  */
-void audit_getname(const char *name)
+void __audit_getname(const char *name)
 {
         struct audit_context *context = current->audit_context;
-        if (!context || IS_ERR(name) || !name)
+        if (IS_ERR(name) || !name)
                 return;
         if (!context->in_syscall) {
  *
  * Returns 0 for success or NULL context or < 0 on error.
  */
-int audit_ipc_obj(struct kern_ipc_perm *ipcp)
+int __audit_ipc_obj(struct kern_ipc_perm *ipcp)
 {
         struct audit_aux_data_ipcctl *ax;
         struct audit_context *context = current->audit_context;
-        if (likely(!context))
-                return 0;
         ax = kmalloc(sizeof(*ax), GFP_ATOMIC);
         if (!ax)
                 return -ENOMEM;
  *
  * Returns 0 for success or NULL context or < 0 on error.
  */
-int audit_ipc_set_perm(unsigned long qbytes, uid_t uid, gid_t gid, mode_t mode)
+int __audit_ipc_set_perm(unsigned long qbytes, uid_t uid, gid_t gid, mode_t mode)
 {
         struct audit_aux_data_ipcctl *ax;
         struct audit_context *context = current->audit_context;
-        if (likely(!context))
-                return 0;
         ax = kmalloc(sizeof(*ax), GFP_ATOMIC);
         if (!ax)
                 return -ENOMEM;

/* * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> * * Based on the 64360 driver from: * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> * Rabeeh Khoury <rabeeh@marvell.com> * * Copyright (C) 2003 PMC-Sierra, Inc., * written by Manish Lachwani * * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> * * Copyright (C) 2004-2006 MontaVista Software, Inc. * Dale Farnsworth <dale@farnsworth.org> * * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> * <sjhill@realitydiluted.com> * * Copyright (C) 2007-2008 Marvell Semiconductor * Lennert Buytenhek <buytenh@marvell.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <linux/init.h> #include <linux/dma-mapping.h> #include <linux/in.h> #include <linux/tcp.h> #include <linux/udp.h> #include <linux/etherdevice.h> #include <linux/delay.h> #include <linux/ethtool.h> #include <linux/platform_device.h> #include <linux/module.h> #include <linux/kernel.h> #include <linux/spinlock.h> #include <linux/workqueue.h> #include <linux/mii.h> #include <linux/mv643xx_eth.h> #include <asm/io.h> #include <asm/types.h> #include <asm/system.h> static char mv643xx_eth_driver_name[] = "mv643xx_eth"; static char mv643xx_eth_driver_version[] = "1.0"; #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX #define MV643XX_ETH_NAPI #define MV643XX_ETH_TX_FAST_REFILL #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) #else #define MAX_DESCS_PER_SKB 1 #endif /* * Registers shared between all ports. */ #define PHY_ADDR 0x0000 #define SMI_REG 0x0004 #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) #define WINDOW_BAR_ENABLE 0x0290 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) /* * Per-port registers. */ #define PORT_CONFIG(p) (0x0400 + ((p) << 10)) #define UNICAST_PROMISCUOUS_MODE 0x00000001 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10)) #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) #define SDMA_CONFIG(p) (0x041c + ((p) << 10)) #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10)) #define PORT_STATUS(p) (0x0444 + ((p) << 10)) #define TX_FIFO_EMPTY 0x00000400 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10)) #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10)) #define TX_BW_RATE(p) (0x0450 + ((p) << 10)) #define TX_BW_MTU(p) (0x0458 + ((p) << 10)) #define TX_BW_BURST(p) (0x045c + ((p) << 10)) #define INT_CAUSE(p) (0x0460 + ((p) << 10)) #define INT_TX_END 0x07f80000 #define INT_RX 0x0007fbfc #define INT_EXT 0x00000002 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10)) #define INT_EXT_LINK 0x00100000 #define INT_EXT_PHY 0x00010000 #define INT_EXT_TX_ERROR_0 0x00000100 #define INT_EXT_TX_0 0x00000001 #define INT_EXT_TX 0x0000ffff #define INT_MASK(p) (0x0468 + ((p) << 10)) #define INT_MASK_EXT(p) (0x046c + ((p) << 10)) #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10)) #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10)) #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10)) #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10)) #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10)) #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4)) #define RXQ_COMMAND(p) (0x0680 + ((p) << 10)) #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2)) #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4)) #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4)) #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4)) #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) /* * SDMA configuration register. */ #define RX_BURST_SIZE_4_64BIT (2 << 1) #define BLM_RX_NO_SWAP (1 << 4) #define BLM_TX_NO_SWAP (1 << 5) #define TX_BURST_SIZE_4_64BIT (2 << 22) #if defined(__BIG_ENDIAN) #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ RX_BURST_SIZE_4_64BIT | \ TX_BURST_SIZE_4_64BIT #elif defined(__LITTLE_ENDIAN) #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ RX_BURST_SIZE_4_64BIT | \ BLM_RX_NO_SWAP | \ BLM_TX_NO_SWAP | \ TX_BURST_SIZE_4_64BIT #else #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined #endif /* * Port serial control register. */ #define SET_MII_SPEED_TO_100 (1 << 24) #define SET_GMII_SPEED_TO_1000 (1 << 23) #define SET_FULL_DUPLEX_MODE (1 << 21) #define MAX_RX_PACKET_1522BYTE (1 << 17) #define MAX_RX_PACKET_9700BYTE (5 << 17) #define MAX_RX_PACKET_MASK (7 << 17) #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) #define DO_NOT_FORCE_LINK_FAIL (1 << 10) #define SERIAL_PORT_CONTROL_RESERVED (1 << 9) #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2) #define FORCE_LINK_PASS (1 << 1) #define SERIAL_PORT_ENABLE (1 << 0) #define DEFAULT_RX_QUEUE_SIZE 400 #define DEFAULT_TX_QUEUE_SIZE 800 /* * RX/TX descriptors. */ #if defined(__BIG_ENDIAN) struct rx_desc { u16 byte_cnt; /* Descriptor buffer byte count */ u16 buf_size; /* Buffer size */ u32 cmd_sts; /* Descriptor command status */ u32 next_desc_ptr; /* Next descriptor pointer */ u32 buf_ptr; /* Descriptor buffer pointer */ }; struct tx_desc { u16 byte_cnt; /* buffer byte count */ u16 l4i_chk; /* CPU provided TCP checksum */ u32 cmd_sts; /* Command/status field */ u32 next_desc_ptr; /* Pointer to next descriptor */ u32 buf_ptr; /* pointer to buffer for this descriptor*/ }; #elif defined(__LITTLE_ENDIAN) struct rx_desc { u32 cmd_sts; /* Descriptor command status */ u16 buf_size; /* Buffer size */ u16 byte_cnt; /* Descriptor buffer byte count */ u32 buf_ptr; /* Descriptor buffer pointer */ u32 next_desc_ptr; /* Next descriptor pointer */ }; struct tx_desc { u32 cmd_sts; /* Command/status field */ u16 l4i_chk; /* CPU provided TCP checksum */ u16 byte_cnt; /* buffer byte count */ u32 buf_ptr; /* pointer to buffer for this descriptor*/ u32 next_desc_ptr; /* Pointer to next descriptor */ }; #else #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined #endif /* RX & TX descriptor command */ #define BUFFER_OWNED_BY_DMA 0x80000000 /* RX & TX descriptor status */ #define ERROR_SUMMARY 0x00000001 /* RX descriptor status */ #define LAYER_4_CHECKSUM_OK 0x40000000 #define RX_ENABLE_INTERRUPT 0x20000000 #define RX_FIRST_DESC 0x08000000 #define RX_LAST_DESC 0x04000000 /* TX descriptor command */ #define TX_ENABLE_INTERRUPT 0x00800000 #define GEN_CRC 0x00400000 #define TX_FIRST_DESC 0x00200000 #define TX_LAST_DESC 0x00100000 #define ZERO_PADDING 0x00080000 #define GEN_IP_V4_CHECKSUM 0x00040000 #define GEN_TCP_UDP_CHECKSUM 0x00020000 #define UDP_FRAME 0x00010000 #define TX_IHL_SHIFT 11 /* global *******************************************************************/ struct mv643xx_eth_shared_private { /* * Ethernet controller base address. */ void __iomem *base; /* * Protects access to SMI_REG, which is shared between ports. */ spinlock_t phy_lock; /* * Per-port MBUS window access register value. */ u32 win_protect; /* * Hardware-specific parameters. */ unsigned int t_clk; int extended_rx_coal_limit; int tx_bw_control_moved; }; /* per-port *****************************************************************/ struct mib_counters { u64 good_octets_received; u32 bad_octets_received; u32 internal_mac_transmit_err; u32 good_frames_received; u32 bad_frames_received; u32 broadcast_frames_received; u32 multicast_frames_received; u32 frames_64_octets; u32 frames_65_to_127_octets; u32 frames_128_to_255_octets; u32 frames_256_to_511_octets; u32 frames_512_to_1023_octets; u32 frames_1024_to_max_octets; u64 good_octets_sent; u32 good_frames_sent; u32 excessive_collision; u32 multicast_frames_sent; u32 broadcast_frames_sent; u32 unrec_mac_control_received; u32 fc_sent; u32 good_fc_received; u32 bad_fc_received; u32 undersize_received; u32 fragments_received; u32 oversize_received; u32 jabber_received; u32 mac_receive_error; u32 bad_crc_event; u32 collision; u32 late_collision; }; struct rx_queue { int index; int rx_ring_size; int rx_desc_count; int rx_curr_desc; int rx_used_desc; struct rx_desc *rx_desc_area; dma_addr_t rx_desc_dma; int rx_desc_area_size; struct sk_buff **rx_skb; struct timer_list rx_oom; }; struct tx_queue { int index; int tx_ring_size; int tx_desc_count; int tx_curr_desc; int tx_used_desc; struct tx_desc *tx_desc_area; dma_addr_t tx_desc_dma; int tx_desc_area_size; struct sk_buff **tx_skb; }; struct mv643xx_eth_private { struct mv643xx_eth_shared_private *shared; int port_num; struct net_device *dev; struct mv643xx_eth_shared_private *shared_smi; int phy_addr; spinlock_t lock; struct mib_counters mib_counters; struct work_struct tx_timeout_task; struct mii_if_info mii; /* * RX state. */ int default_rx_ring_size; unsigned long rx_desc_sram_addr; int rx_desc_sram_size; u8 rxq_mask; int rxq_primary; struct napi_struct napi; struct rx_queue rxq[8]; /* * TX state. */ int default_tx_ring_size; unsigned long tx_desc_sram_addr; int tx_desc_sram_size; u8 txq_mask; int txq_primary; struct tx_queue txq[8]; #ifdef MV643XX_ETH_TX_FAST_REFILL int tx_clean_threshold; #endif }; /* port register accessors **************************************************/ static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) { return readl(mp->shared->base + offset); } static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) { writel(data, mp->shared->base + offset); } /* rxq/txq helper functions *************************************************/ static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) { return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); } static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) { return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); } static void rxq_enable(struct rx_queue *rxq) { struct mv643xx_eth_private *mp = rxq_to_mp(rxq); wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index); } static void rxq_disable(struct rx_queue *rxq) { struct mv643xx_eth_private *mp = rxq_to_mp(rxq); u8 mask = 1 << rxq->index; wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8); while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask) udelay(10); } static void txq_enable(struct tx_queue *txq) { struct mv643xx_eth_private *mp = txq_to_mp(txq); wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index); } static void txq_disable(struct tx_queue *txq) { struct mv643xx_eth_private *mp = txq_to_mp(txq); u8 mask = 1 << txq->index; wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8); while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask) udelay(10); } static void __txq_maybe_wake(struct tx_queue *txq) { struct mv643xx_eth_private *mp = txq_to_mp(txq); /* * netif_{stop,wake}_queue() flow control only applies to * the primary queue. */ BUG_ON(txq->index != mp->txq_primary); if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB) netif_wake_queue(mp->dev); } /* rx ***********************************************************************/ static void txq_reclaim(struct tx_queue *txq, int force); static void rxq_refill(struct rx_queue *rxq) { struct mv643xx_eth_private *mp = rxq_to_mp(rxq); unsigned long flags; spin_lock_irqsave(&mp->lock, flags); while (rxq->rx_desc_count < rxq->rx_ring_size) { int skb_size; struct sk_buff *skb; int unaligned; int rx; /* * Reserve 2+14 bytes for an ethernet header (the * hardware automatically prepends 2 bytes of dummy * data to each received packet), 4 bytes for a VLAN * header, and 4 bytes for the trailing FCS -- 24 * bytes total. */ skb_size = mp->dev->mtu + 24; skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1); if (skb == NULL) break; unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); if (unaligned) skb_reserve(skb, dma_get_cache_alignment() - unaligned); rxq->rx_desc_count++; rx = rxq->rx_used_desc; rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size; rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data, skb_size, DMA_FROM_DEVICE); rxq->rx_desc_area[rx].buf_size = skb_size; rxq->rx_skb[rx] = skb; wmb(); rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT; wmb(); /* * The hardware automatically prepends 2 bytes of * dummy data to each received packet, so that the * IP header ends up 16-byte aligned. */ skb_reserve(skb, 2); } if (rxq->rx_desc_count != rxq->rx_ring_size) { rxq->rx_oom.expires = jiffies + (HZ / 10); add_timer(&rxq->rx_oom); } spin_unlock_irqrestore(&mp->lock, flags); } static inline void rxq_refill_timer_wrapper(unsigned long data) { rxq_refill((struct rx_queue *)data); } static int rxq_process(struct rx_queue *rxq, int budget) { struct mv643xx_eth_private *mp = rxq_to_mp(rxq); struct net_device_stats *stats = &mp->dev->stats; int rx; rx = 0; while (rx < budget) { struct rx_desc *rx_desc; unsigned int cmd_sts; struct sk_buff *skb; unsigned long flags; spin_lock_irqsave(&mp->lock, flags); rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; cmd_sts = rx_desc->cmd_sts; if (cmd_sts & BUFFER_OWNED_BY_DMA) { spin_unlock_irqrestore(&mp->lock, flags); break; } rmb(); skb = rxq->rx_skb[rxq->rx_curr_desc]; rxq->rx_skb[rxq->rx_curr_desc] = NULL; rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size; spin_unlock_irqrestore(&mp->lock, flags); dma_unmap_single(NULL, rx_desc->buf_ptr + 2, mp->dev->mtu + 24, DMA_FROM_DEVICE); rxq->rx_desc_count--; rx++; /* * Update statistics. * * Note that the descriptor byte count includes 2 dummy * bytes automatically inserted by the hardware at the * start of the packet (which we don't count), and a 4 * byte CRC at the end of the packet (which we do count). */ stats->rx_packets++; stats->rx_bytes += rx_desc->byte_cnt - 2; /* * In case we received a packet without first / last bits * on, or the error summary bit is set, the packet needs * to be dropped. */ if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != (RX_FIRST_DESC | RX_LAST_DESC)) || (cmd_sts & ERROR_SUMMARY)) { stats->rx_dropped++; if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != (RX_FIRST_DESC | RX_LAST_DESC)) { if (net_ratelimit()) dev_printk(KERN_ERR, &mp->dev->dev, "received packet spanning " "multiple descriptors\n"); } if (cmd_sts & ERROR_SUMMARY) stats->rx_errors++; dev_kfree_skb_irq(skb); } else { /* * The -4 is for the CRC in the trailer of the * received packet */ skb_put(skb, rx_desc->byte_cnt - 2 - 4); if (cmd_sts & LAYER_4_CHECKSUM_OK) { skb->ip_summed = CHECKSUM_UNNECESSARY; skb->csum = htons( (cmd_sts & 0x0007fff8) >> 3); } skb->protocol = eth_type_trans(skb, mp->dev); #ifdef MV643XX_ETH_NAPI netif_receive_skb(skb); #else netif_rx(skb); #endif } mp->dev->last_rx = jiffies; } rxq_refill(rxq); return rx; } #ifdef MV643XX_ETH_NAPI static int mv643xx_eth_poll(struct napi_struct *napi, int budget) { struct mv643xx_eth_private *mp; int rx; int i; mp = container_of(napi, struct mv643xx_eth_private, napi); #ifdef MV643XX_ETH_TX_FAST_REFILL if (++mp->tx_clean_threshold > 5) { mp->tx_clean_threshold = 0; for (i = 0; i < 8; i++) if (mp->txq_mask & (1 << i)) txq_reclaim(mp->txq + i, 0); } #endif rx = 0; for (i = 7; rx < budget && i >= 0; i--) if (mp->rxq_mask & (1 << i)) rx += rxq_process(mp->rxq + i, budget - rx); if (rx < budget) { netif_rx_complete(mp->dev, napi); wrl(mp, INT_CAUSE(mp->port_num), 0); wrl(mp, INT_CAUSE_EXT(mp->port_num), 0); wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT); } return rx; } #endif /* tx ***********************************************************************/ static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) { int frag; for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; if (fragp->size <= 8 && fragp->page_offset & 7) return 1; } return 0; } static int txq_alloc_desc_index(struct tx_queue *txq) { int tx_desc_curr; BUG_ON(txq->tx_desc_count >= txq->tx_ring_size); tx_desc_curr = txq->tx_curr_desc; txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size; BUG_ON(txq->tx_curr_desc == txq->tx_used_desc); return tx_desc_curr; } static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) { int nr_frags = skb_shinfo(skb)->nr_frags; int frag; for (frag = 0; frag < nr_frags; frag++) { skb_frag_t *this_frag; int tx_index; struct tx_desc *desc; this_frag = &skb_shinfo(skb)->frags[frag]; tx_index = txq_alloc_desc_index(txq); desc = &txq->tx_desc_area[tx_index]; /* * The last fragment will generate an interrupt * which will free the skb on TX completion. */ if (frag == nr_frags - 1) { desc->cmd_sts = BUFFER_OWNED_BY_DMA | ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; txq->tx_skb[tx_index] = skb; } else { desc->cmd_sts = BUFFER_OWNED_BY_DMA; txq->tx_skb[tx_index] = NULL; } desc->l4i_chk = 0; desc->byte_cnt = this_frag->size; desc->buf_ptr = dma_map_page(NULL, this_frag->page, this_frag->page_offset, this_frag->size, DMA_TO_DEVICE); } } static inline __be16 sum16_as_be(__sum16 sum) { return (__force __be16)sum; } static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb) { int nr_frags = skb_shinfo(skb)->nr_frags; int tx_index; struct tx_desc *desc; u32 cmd_sts; int length; cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; tx_index = txq_alloc_desc_index(txq); desc = &txq->tx_desc_area[tx_index]; if (nr_frags) { txq_submit_frag_skb(txq, skb); length = skb_headlen(skb); txq->tx_skb[tx_index] = NULL; } else { cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; length = skb->len; txq->tx_skb[tx_index] = skb; } desc->byte_cnt = length; desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); if (skb->ip_summed == CHECKSUM_PARTIAL) { BUG_ON(skb->protocol != htons(ETH_P_IP)); cmd_sts |= GEN_TCP_UDP_CHECKSUM | GEN_IP_V4_CHECKSUM | ip_hdr(skb)->ihl << TX_IHL_SHIFT; switch (ip_hdr(skb)->protocol) { case IPPROTO_UDP: cmd_sts |= UDP_FRAME; desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); break; case IPPROTO_TCP: desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); break; default: BUG(); } } else { /* Errata BTS #50, IHL must be 5 if no HW checksum */ cmd_sts |= 5 << TX_IHL_SHIFT; desc->l4i_chk = 0; } /* ensure all other descriptors are written before first cmd_sts */ wmb(); desc->cmd_sts = cmd_sts; /* ensure all descriptors are written before poking hardware */ wmb(); txq_enable(txq); txq->tx_desc_count += nr_frags + 1; } static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) { struct mv643xx_eth_private *mp = netdev_priv(dev); struct net_device_stats *stats = &dev->stats; struct tx_queue *txq; unsigned long flags; if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { stats->tx_dropped++; dev_printk(KERN_DEBUG, &dev->dev, "failed to linearize skb with tiny " "unaligned fragment\n"); return NETDEV_TX_BUSY; } spin_lock_irqsave(&mp->lock, flags); txq = mp->txq + mp->txq_primary; if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) { spin_unlock_irqrestore(&mp->lock, flags); if (txq->index == mp->txq_primary && net_ratelimit()) dev_printk(KERN_ERR, &dev->dev, "primary tx queue full?!\n"); kfree_skb(skb); return NETDEV_TX_OK; } txq_submit_skb(txq, skb); stats->tx_bytes += skb->len; stats->tx_packets++; dev->trans_start = jiffies; if (txq->index == mp->txq_primary) { int entries_left; entries_left = txq->tx_ring_size - txq->tx_desc_count; if (entries_left < MAX_DESCS_PER_SKB) netif_stop_queue(dev); } spin_unlock_irqrestore(&mp->lock, flags); return NETDEV_TX_OK; } /* tx rate control **********************************************************/ /* * Set total maximum TX rate (shared by all TX queues for this port) * to 'rate' bits per second, with a maximum burst of 'burst' bytes. */ static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) { int token_rate; int mtu; int bucket_size; token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); if (token_rate > 1023) token_rate = 1023; mtu = (mp->dev->mtu + 255) >> 8; if (mtu > 63) mtu = 63; bucket_size = (burst + 255) >> 8; if (bucket_size > 65535) bucket_size = 65535; if (mp->shared->tx_bw_control_moved) { wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate); wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu); wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size); } else { wrl(mp, TX_BW_RATE(mp->port_num), token_rate); wrl(mp, TX_BW_MTU(mp->port_num), mtu); wrl(mp, TX_BW_BURST(mp->port_num), bucket_size); } } static void txq_set_rate(struct tx_queue *txq, int rate, int burst) { struct mv643xx_eth_private *mp = txq_to_mp(txq); int token_rate; int bucket_size; token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); if (token_rate > 1023) token_rate = 1023; bucket_size = (burst + 255) >> 8; if (bucket_size > 65535) bucket_size = 65535; wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14); wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index), (bucket_size << 10) | token_rate); } static void txq_set_fixed_prio_mode(struct tx_queue *txq) { struct mv643xx_eth_private *mp = txq_to_mp(txq); int off; u32 val; /* * Turn on fixed priority mode. */ if (mp->shared->tx_bw_control_moved) off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num); else off = TXQ_FIX_PRIO_CONF(mp->port_num); val = rdl(mp, off); val |= 1 << txq->index; wrl(mp, off, val); } static void txq_set_wrr(struct tx_queue *txq, int weight) { struct mv643xx_eth_private *mp = txq_to_mp(txq); int off; u32 val; /* * Turn off fixed priority mode. */ if (mp->shared->tx_bw_control_moved) off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num); else off = TXQ_FIX_PRIO_CONF(mp->port_num); val = rdl(mp, off); val &= ~(1 << txq->index); wrl(mp, off, val); /* * Configure WRR weight for this queue. */ off = TXQ_BW_WRR_CONF(mp->port_num, txq->index); val = rdl(mp, off); val = (val & ~0xff) | (weight & 0xff); wrl(mp, off, val); } /* mii management interface *************************************************/ #define SMI_BUSY 0x10000000 #define SMI_READ_VALID 0x08000000 #define SMI_OPCODE_READ 0x04000000 #define SMI_OPCODE_WRITE 0x00000000 static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr, unsigned int reg, unsigned int *value) { void __iomem *smi_reg = mp->shared_smi->base + SMI_REG; unsigned long flags; int i; /* the SMI register is a shared resource */ spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); /* wait for the SMI register to become available */ for (i = 0; readl(smi_reg) & SMI_BUSY; i++) { if (i == 1000) { printk("%s: PHY busy timeout\n", mp->dev->name); goto out; } udelay(10); } writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg); /* now wait for the data to be valid */ for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) { if (i == 1000) { printk("%s: PHY read timeout\n", mp->dev->name); goto out; } udelay(10); } *value = readl(smi_reg) & 0xffff; out: spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); } static void smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr, unsigned int reg, unsigned int value) { void __iomem *smi_reg = mp->shared_smi->base + SMI_REG; unsigned long flags; int i; /* the SMI register is a shared resource */ spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); /* wait for the SMI register to become available */ for (i = 0; readl(smi_reg) & SMI_BUSY; i++) { if (i == 1000) { printk("%s: PHY busy timeout\n", mp->dev->name); goto out; } udelay(10); } writel(SMI_OPCODE_WRITE | (reg << 21) | (addr << 16) | (value & 0xffff), smi_reg); out: spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); } /* mib counters *************************************************************/ static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) { return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); } static void mib_counters_clear(struct mv643xx_eth_private *mp) { int i; for (i = 0; i < 0x80; i += 4) mib_read(mp, i); } static void mib_counters_update(struct mv643xx_eth_private *mp) { struct mib_counters *p = &mp->mib_counters; p->good_octets_received += mib_read(mp, 0x00); p->good_octets_received += (u64)mib_read(mp, 0x04) << 32; p->bad_octets_received += mib_read(mp, 0x08); p->internal_mac_transmit_err += mib_read(mp, 0x0c); p->good_frames_received += mib_read(mp, 0x10); p->bad_frames_received += mib_read(mp, 0x14); p->broadcast_frames_received += mib_read(mp, 0x18); p->multicast_frames_received += mib_read(mp, 0x1c); p->frames_64_octets += mib_read(mp, 0x20); p->frames_65_to_127_octets += mib_read(mp, 0x24); p->frames_128_to_255_octets += mib_read(mp, 0x28); p->frames_256_to_511_octets += mib_read(mp, 0x2c); p->frames_512_to_1023_octets += mib_read(mp, 0x30); p->frames_1024_to_max_octets += mib_read(mp, 0x34); p->good_octets_sent += mib_read(mp, 0x38); p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32; p->good_frames_sent += mib_read(mp, 0x40); p->excessive_collision += mib_read(mp, 0x44); p->multicast_frames_sent += mib_read(mp, 0x48); p->broadcast_frames_sent += mib_read(mp, 0x4c); p->unrec_mac_control_received += mib_read(mp, 0x50); p->fc_sent += mib_read(mp, 0x54); p->good_fc_received += mib_read(mp, 0x58); p->bad_fc_received += mib_read(mp, 0x5c); p->undersize_received += mib_read(mp, 0x60); p->fragments_received += mib_read(mp, 0x64); p->oversize_received += mib_read(mp, 0x68); p->jabber_received += mib_read(mp, 0x6c); p->mac_receive_error += mib_read(mp, 0x70); p->bad_crc_event += mib_read(mp, 0x74); p->collision += mib_read(mp, 0x78); p->late_collision += mib_read(mp, 0x7c); } /* ethtool ******************************************************************/ struct mv643xx_eth_stats { char stat_string[ETH_GSTRING_LEN]; int sizeof_stat; int netdev_off; int mp_off; }; #define SSTAT(m) \ { #m, FIELD_SIZEOF(struct net_device_stats, m), \ offsetof(struct net_device, stats.m), -1 } #define MIBSTAT(m) \ { #m, FIELD_SIZEOF(struct mib_counters, m), \ -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { SSTAT(rx_packets), SSTAT(tx_packets), SSTAT(rx_bytes), SSTAT(tx_bytes), SSTAT(rx_errors), SSTAT(tx_errors), SSTAT(rx_dropped), SSTAT(tx_dropped), MIBSTAT(good_octets_received), MIBSTAT(bad_octets_received), MIBSTAT(internal_mac_transmit_err), MIBSTAT(good_frames_received), MIBSTAT(bad_frames_received), MIBSTAT(broadcast_frames_received), MIBSTAT(multicast_frames_received), MIBSTAT(frames_64_octets), MIBSTAT(frames_65_to_127_octets), MIBSTAT(frames_128_to_255_octets), MIBSTAT(frames_256_to_511_octets), MIBSTAT(frames_512_to_1023_octets), MIBSTAT(frames_1024_to_max_octets), MIBSTAT(good_octets_sent), MIBSTAT(good_frames_sent), MIBSTAT(excessive_collision), MIBSTAT(multicast_frames_sent), MIBSTAT(broadcast_frames_sent), MIBSTAT(unrec_mac_control_received), MIBSTAT(fc_sent), MIBSTAT(good_fc_received), MIBSTAT(bad_fc_received), MIBSTAT(undersize_received), MIBSTAT(fragments_received), MIBSTAT(oversize_received), MIBSTAT(jabber_received), MIBSTAT(mac_receive_error), MIBSTAT(bad_crc_event), MIBSTAT(collision), MIBSTAT(late_collision), }; static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { struct mv643xx_eth_private *mp = netdev_priv(dev); int err; spin_lock_irq(&mp->lock); err = mii_ethtool_gset(&mp->mii, cmd); spin_unlock_irq(&mp->lock); /* * The MAC does not support 1000baseT_Half. */ cmd->supported &= ~SUPPORTED_1000baseT_Half; cmd->advertising &= ~ADVERTISED_1000baseT_Half; return err; } static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd) { cmd->supported = SUPPORTED_MII; cmd->advertising = ADVERTISED_MII; cmd->speed = SPEED_1000; cmd->duplex = DUPLEX_FULL; cmd->port = PORT_MII; cmd->phy_address = 0; cmd->transceiver = XCVR_INTERNAL; cmd->autoneg = AUTONEG_DISABLE; cmd->maxtxpkt = 1; cmd->maxrxpkt = 1; return 0; } static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) { struct mv643xx_eth_private *mp = netdev_priv(dev); int err; /* * The MAC does not support 1000baseT_Half. */ cmd->advertising &= ~ADVERTISED_1000baseT_Half; spin_lock_irq(&mp->lock); err = mii_ethtool_sset(&mp->mii, cmd); spin_unlock_irq(&mp->lock); return err; } static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd) { return -EINVAL; } static void mv643xx_eth_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo) { strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32); strncpy(drvinfo->version, mv643xx_eth_driver_version, 32); strncpy(drvinfo->fw_version, "N/A", 32); strncpy(drvinfo->bus_info, "platform", 32); drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats); } static int mv643xx_eth_nway_reset(struct net_device *dev) { struct mv643xx_eth_private *mp = netdev_priv(dev); return mii_nway_restart(&mp->mii); }


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