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-rw-r--r--drivers/gpu/drm/i915/i915_gem.c7
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c109
2 files changed, 55 insertions, 61 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0b99c30bb19c..edd6098743b2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2219,13 +2219,18 @@ i915_gem_flush_ring(struct intel_ring_buffer *ring,
2219{ 2219{
2220 int ret; 2220 int ret;
2221 2221
2222 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2223 return 0;
2224
2222 trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); 2225 trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2223 2226
2224 ret = ring->flush(ring, invalidate_domains, flush_domains); 2227 ret = ring->flush(ring, invalidate_domains, flush_domains);
2225 if (ret) 2228 if (ret)
2226 return ret; 2229 return ret;
2227 2230
2228 i915_gem_process_flushing_list(ring, flush_domains); 2231 if (flush_domains & I915_GEM_GPU_DOMAINS)
2232 i915_gem_process_flushing_list(ring, flush_domains);
2233
2229 return 0; 2234 return 0;
2230} 2235}
2231 2236
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 789c47801ba8..e9e6f71418a4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -65,62 +65,60 @@ render_ring_flush(struct intel_ring_buffer *ring,
65 u32 cmd; 65 u32 cmd;
66 int ret; 66 int ret;
67 67
68 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { 68 /*
69 * read/write caches:
70 *
71 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
72 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
73 * also flushed at 2d versus 3d pipeline switches.
74 *
75 * read-only caches:
76 *
77 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
78 * MI_READ_FLUSH is set, and is always flushed on 965.
79 *
80 * I915_GEM_DOMAIN_COMMAND may not exist?
81 *
82 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
83 * invalidated when MI_EXE_FLUSH is set.
84 *
85 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
86 * invalidated with every MI_FLUSH.
87 *
88 * TLBs:
89 *
90 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
91 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
92 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
93 * are flushed at any MI_FLUSH.
94 */
95
96 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
97 if ((invalidate_domains|flush_domains) &
98 I915_GEM_DOMAIN_RENDER)
99 cmd &= ~MI_NO_WRITE_FLUSH;
100 if (INTEL_INFO(dev)->gen < 4) {
69 /* 101 /*
70 * read/write caches: 102 * On the 965, the sampler cache always gets flushed
71 * 103 * and this bit is reserved.
72 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
73 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
74 * also flushed at 2d versus 3d pipeline switches.
75 *
76 * read-only caches:
77 *
78 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
79 * MI_READ_FLUSH is set, and is always flushed on 965.
80 *
81 * I915_GEM_DOMAIN_COMMAND may not exist?
82 *
83 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
84 * invalidated when MI_EXE_FLUSH is set.
85 *
86 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
87 * invalidated with every MI_FLUSH.
88 *
89 * TLBs:
90 *
91 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
92 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
93 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
94 * are flushed at any MI_FLUSH.
95 */ 104 */
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107 }
108 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
109 cmd |= MI_EXE_FLUSH;
96 110
97 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; 111 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
98 if ((invalidate_domains|flush_domains) & 112 (IS_G4X(dev) || IS_GEN5(dev)))
99 I915_GEM_DOMAIN_RENDER) 113 cmd |= MI_INVALIDATE_ISP;
100 cmd &= ~MI_NO_WRITE_FLUSH;
101 if (INTEL_INFO(dev)->gen < 4) {
102 /*
103 * On the 965, the sampler cache always gets flushed
104 * and this bit is reserved.
105 */
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
108 }
109 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
110 cmd |= MI_EXE_FLUSH;
111
112 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
113 (IS_G4X(dev) || IS_GEN5(dev)))
114 cmd |= MI_INVALIDATE_ISP;
115 114
116 ret = intel_ring_begin(ring, 2); 115 ret = intel_ring_begin(ring, 2);
117 if (ret) 116 if (ret)
118 return ret; 117 return ret;
119 118
120 intel_ring_emit(ring, cmd); 119 intel_ring_emit(ring, cmd);
121 intel_ring_emit(ring, MI_NOOP); 120 intel_ring_emit(ring, MI_NOOP);
122 intel_ring_advance(ring); 121 intel_ring_advance(ring);
123 }
124 122
125 return 0; 123 return 0;
126} 124}
@@ -568,9 +566,6 @@ bsd_ring_flush(struct intel_ring_buffer *ring,
568{ 566{
569 int ret; 567 int ret;
570 568
571 if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
572 return 0;
573
574 ret = intel_ring_begin(ring, 2); 569 ret = intel_ring_begin(ring, 2);
575 if (ret) 570 if (ret)
576 return ret; 571 return ret;
@@ -1056,9 +1051,6 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
1056 uint32_t cmd; 1051 uint32_t cmd;
1057 int ret; 1052 int ret;
1058 1053
1059 if (((invalidate | flush) & I915_GEM_GPU_DOMAINS) == 0)
1060 return 0;
1061
1062 ret = intel_ring_begin(ring, 4); 1054 ret = intel_ring_begin(ring, 4);
1063 if (ret) 1055 if (ret)
1064 return ret; 1056 return ret;
@@ -1230,9 +1222,6 @@ static int blt_ring_flush(struct intel_ring_buffer *ring,
1230 uint32_t cmd; 1222 uint32_t cmd;
1231 int ret; 1223 int ret;
1232 1224
1233 if (((invalidate | flush) & I915_GEM_DOMAIN_RENDER) == 0)
1234 return 0;
1235
1236 ret = blt_ring_begin(ring, 4); 1225 ret = blt_ring_begin(ring, 4);
1237 if (ret) 1226 if (ret)
1238 return ret; 1227 return ret;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 22:49:38 -0500