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path: root/drivers/scsi/bnx2fc/57xx_hsi_bnx2fc.h
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Diffstat (limited to 'drivers/scsi/bnx2fc/57xx_hsi_bnx2fc.h')
-rw-r--r--drivers/scsi/bnx2fc/57xx_hsi_bnx2fc.h1162
1 files changed, 536 insertions, 626 deletions
diff --git a/drivers/scsi/bnx2fc/57xx_hsi_bnx2fc.h b/drivers/scsi/bnx2fc/57xx_hsi_bnx2fc.h
index 97a61b4d81b7..e1f1e3448f98 100644
--- a/drivers/scsi/bnx2fc/57xx_hsi_bnx2fc.h
+++ b/drivers/scsi/bnx2fc/57xx_hsi_bnx2fc.h
@@ -19,6 +19,23 @@ struct b577xx_doorbell_hdr {
19/* 19/*
20 * doorbell message sent to the chip 20 * doorbell message sent to the chip
21 */ 21 */
22struct b577xx_doorbell {
23#if defined(__BIG_ENDIAN)
24 u16 zero_fill2;
25 u8 zero_fill1;
26 struct b577xx_doorbell_hdr header;
27#elif defined(__LITTLE_ENDIAN)
28 struct b577xx_doorbell_hdr header;
29 u8 zero_fill1;
30 u16 zero_fill2;
31#endif
32};
33
34
35
36/*
37 * doorbell message sent to the chip
38 */
22struct b577xx_doorbell_set_prod { 39struct b577xx_doorbell_set_prod {
23#if defined(__BIG_ENDIAN) 40#if defined(__BIG_ENDIAN)
24 u16 prod; 41 u16 prod;
@@ -39,106 +56,63 @@ struct regpair {
39 56
40 57
41/* 58/*
42 * Fixed size structure in order to plant it in Union structure 59 * ABTS info $$KEEP_ENDIANNESS$$
43 */ 60 */
44struct fcoe_abts_rsp_union { 61struct fcoe_abts_info {
45 u32 r_ctl; 62 __le16 aborted_task_id;
46 u32 abts_rsp_payload[7]; 63 __le16 reserved0;
64 __le32 reserved1;
47}; 65};
48 66
49 67
50/* 68/*
51 * 4 regs size 69 * Fixed size structure in order to plant it in Union structure
70 * $$KEEP_ENDIANNESS$$
52 */ 71 */
53struct fcoe_bd_ctx { 72struct fcoe_abts_rsp_union {
54 u32 buf_addr_hi; 73 u8 r_ctl;
55 u32 buf_addr_lo; 74 u8 rsrv[3];
56#if defined(__BIG_ENDIAN) 75 __le32 abts_rsp_payload[7];
57 u16 rsrv0;
58 u16 buf_len;
59#elif defined(__LITTLE_ENDIAN)
60 u16 buf_len;
61 u16 rsrv0;
62#endif
63#if defined(__BIG_ENDIAN)
64 u16 rsrv1;
65 u16 flags;
66#elif defined(__LITTLE_ENDIAN)
67 u16 flags;
68 u16 rsrv1;
69#endif
70}; 76};
71 77
72 78
73struct fcoe_cleanup_flow_info { 79/*
74#if defined(__BIG_ENDIAN) 80 * 4 regs size $$KEEP_ENDIANNESS$$
75 u16 reserved1; 81 */
76 u16 task_id; 82struct fcoe_bd_ctx {
77#elif defined(__LITTLE_ENDIAN) 83 __le32 buf_addr_hi;
78 u16 task_id; 84 __le32 buf_addr_lo;
79 u16 reserved1; 85 __le16 buf_len;
80#endif 86 __le16 rsrv0;
81 u32 reserved2[7]; 87 __le16 flags;
88 __le16 rsrv1;
82}; 89};
83 90
84 91
85struct fcoe_fcp_cmd_payload { 92/*
86 u32 opaque[8]; 93 * FCoE cached sges context $$KEEP_ENDIANNESS$$
87}; 94 */
88 95struct fcoe_cached_sge_ctx {
89struct fcoe_fc_hdr { 96 struct regpair cur_buf_addr;
90#if defined(__BIG_ENDIAN) 97 __le16 cur_buf_rem;
91 u8 cs_ctl; 98 __le16 second_buf_rem;
92 u8 s_id[3]; 99 struct regpair second_buf_addr;
93#elif defined(__LITTLE_ENDIAN)
94 u8 s_id[3];
95 u8 cs_ctl;
96#endif
97#if defined(__BIG_ENDIAN)
98 u8 r_ctl;
99 u8 d_id[3];
100#elif defined(__LITTLE_ENDIAN)
101 u8 d_id[3];
102 u8 r_ctl;
103#endif
104#if defined(__BIG_ENDIAN)
105 u8 seq_id;
106 u8 df_ctl;
107 u16 seq_cnt;
108#elif defined(__LITTLE_ENDIAN)
109 u16 seq_cnt;
110 u8 df_ctl;
111 u8 seq_id;
112#endif
113#if defined(__BIG_ENDIAN)
114 u8 type;
115 u8 f_ctl[3];
116#elif defined(__LITTLE_ENDIAN)
117 u8 f_ctl[3];
118 u8 type;
119#endif
120 u32 parameters;
121#if defined(__BIG_ENDIAN)
122 u16 ox_id;
123 u16 rx_id;
124#elif defined(__LITTLE_ENDIAN)
125 u16 rx_id;
126 u16 ox_id;
127#endif
128}; 100};
129 101
130struct fcoe_fc_frame {
131 struct fcoe_fc_hdr fc_hdr;
132 u32 reserved0[2];
133};
134 102
135union fcoe_cmd_flow_info { 103/*
136 struct fcoe_fcp_cmd_payload fcp_cmd_payload; 104 * Cleanup info $$KEEP_ENDIANNESS$$
137 struct fcoe_fc_frame mp_fc_frame; 105 */
106struct fcoe_cleanup_info {
107 __le16 cleaned_task_id;
108 __le16 rolled_tx_seq_cnt;
109 __le32 rolled_tx_data_offset;
138}; 110};
139 111
140 112
141 113/*
114 * Fcp RSP flags $$KEEP_ENDIANNESS$$
115 */
142struct fcoe_fcp_rsp_flags { 116struct fcoe_fcp_rsp_flags {
143 u8 flags; 117 u8 flags;
144#define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0) 118#define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0)
@@ -155,95 +129,168 @@ struct fcoe_fcp_rsp_flags {
155#define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5 129#define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5
156}; 130};
157 131
158 132/*
133 * Fcp RSP payload $$KEEP_ENDIANNESS$$
134 */
159struct fcoe_fcp_rsp_payload { 135struct fcoe_fcp_rsp_payload {
160 struct regpair reserved0; 136 struct regpair reserved0;
161 u32 fcp_resid; 137 __le32 fcp_resid;
162#if defined(__BIG_ENDIAN)
163 u16 retry_delay_timer;
164 struct fcoe_fcp_rsp_flags fcp_flags;
165 u8 scsi_status_code;
166#elif defined(__LITTLE_ENDIAN)
167 u8 scsi_status_code; 138 u8 scsi_status_code;
168 struct fcoe_fcp_rsp_flags fcp_flags; 139 struct fcoe_fcp_rsp_flags fcp_flags;
169 u16 retry_delay_timer; 140 __le16 retry_delay_timer;
170#endif 141 __le32 fcp_rsp_len;
171 u32 fcp_rsp_len; 142 __le32 fcp_sns_len;
172 u32 fcp_sns_len;
173}; 143};
174 144
175
176/* 145/*
177 * Fixed size structure in order to plant it in Union structure 146 * Fixed size structure in order to plant it in Union structure
147 * $$KEEP_ENDIANNESS$$
178 */ 148 */
179struct fcoe_fcp_rsp_union { 149struct fcoe_fcp_rsp_union {
180 struct fcoe_fcp_rsp_payload payload; 150 struct fcoe_fcp_rsp_payload payload;
181 struct regpair reserved0; 151 struct regpair reserved0;
182}; 152};
183 153
154/*
155 * FC header $$KEEP_ENDIANNESS$$
156 */
157struct fcoe_fc_hdr {
158 u8 s_id[3];
159 u8 cs_ctl;
160 u8 d_id[3];
161 u8 r_ctl;
162 __le16 seq_cnt;
163 u8 df_ctl;
164 u8 seq_id;
165 u8 f_ctl[3];
166 u8 type;
167 __le32 parameters;
168 __le16 rx_id;
169 __le16 ox_id;
170};
184 171
185struct fcoe_fcp_xfr_rdy_payload { 172/*
186 u32 burst_len; 173 * FC header union $$KEEP_ENDIANNESS$$
187 u32 data_ro; 174 */
175struct fcoe_mp_rsp_union {
176 struct fcoe_fc_hdr fc_hdr;
177 __le32 mp_payload_len;
178 __le32 rsrv;
188}; 179};
189 180
190struct fcoe_read_flow_info { 181/*
191 struct fcoe_fc_hdr fc_data_in_hdr; 182 * Completion information $$KEEP_ENDIANNESS$$
192 u32 reserved[2]; 183 */
184union fcoe_comp_flow_info {
185 struct fcoe_fcp_rsp_union fcp_rsp;
186 struct fcoe_abts_rsp_union abts_rsp;
187 struct fcoe_mp_rsp_union mp_rsp;
188 __le32 opaque[8];
193}; 189};
194 190
195struct fcoe_write_flow_info { 191
196 struct fcoe_fc_hdr fc_data_out_hdr; 192/*
197 struct fcoe_fcp_xfr_rdy_payload fcp_xfr_payload; 193 * External ABTS info $$KEEP_ENDIANNESS$$
194 */
195struct fcoe_ext_abts_info {
196 __le32 rsrv0[6];
197 struct fcoe_abts_info ctx;
198}; 198};
199 199
200union fcoe_rsp_flow_info { 200
201 struct fcoe_fcp_rsp_union fcp_rsp; 201/*
202 struct fcoe_abts_rsp_union abts_rsp; 202 * External cleanup info $$KEEP_ENDIANNESS$$
203 */
204struct fcoe_ext_cleanup_info {
205 __le32 rsrv0[6];
206 struct fcoe_cleanup_info ctx;
203}; 207};
204 208
209
205/* 210/*
206 * 32 bytes used for general purposes 211 * Fcoe FW Tx sequence context $$KEEP_ENDIANNESS$$
207 */ 212 */
208union fcoe_general_task_ctx { 213struct fcoe_fw_tx_seq_ctx {
209 union fcoe_cmd_flow_info cmd_info; 214 __le32 data_offset;
210 struct fcoe_read_flow_info read_info; 215 __le16 seq_cnt;
211 struct fcoe_write_flow_info write_info; 216 __le16 rsrv0;
212 union fcoe_rsp_flow_info rsp_info; 217};
213 struct fcoe_cleanup_flow_info cleanup_info; 218
214 u32 comp_info[8]; 219/*
220 * Fcoe external FW Tx sequence context $$KEEP_ENDIANNESS$$
221 */
222struct fcoe_ext_fw_tx_seq_ctx {
223 __le32 rsrv0[6];
224 struct fcoe_fw_tx_seq_ctx ctx;
225};
226
227
228/*
229 * FCoE multiple sges context $$KEEP_ENDIANNESS$$
230 */
231struct fcoe_mul_sges_ctx {
232 struct regpair cur_sge_addr;
233 __le16 cur_sge_off;
234 u8 cur_sge_idx;
235 u8 sgl_size;
236};
237
238/*
239 * FCoE external multiple sges context $$KEEP_ENDIANNESS$$
240 */
241struct fcoe_ext_mul_sges_ctx {
242 struct fcoe_mul_sges_ctx mul_sgl;
243 struct regpair rsrv0;
215}; 244};
216 245
217 246
218/* 247/*
219 * FCoE KCQ CQE parameters 248 * FCP CMD payload $$KEEP_ENDIANNESS$$
249 */
250struct fcoe_fcp_cmd_payload {
251 __le32 opaque[8];
252};
253
254
255
256
257
258/*
259 * Fcp xfr rdy payload $$KEEP_ENDIANNESS$$
260 */
261struct fcoe_fcp_xfr_rdy_payload {
262 __le32 burst_len;
263 __le32 data_ro;
264};
265
266
267/*
268 * FC frame $$KEEP_ENDIANNESS$$
269 */
270struct fcoe_fc_frame {
271 struct fcoe_fc_hdr fc_hdr;
272 __le32 reserved0[2];
273};
274
275
276
277
278/*
279 * FCoE KCQ CQE parameters $$KEEP_ENDIANNESS$$
220 */ 280 */
221union fcoe_kcqe_params { 281union fcoe_kcqe_params {
222 u32 reserved0[4]; 282 __le32 reserved0[4];
223}; 283};
224 284
225/* 285/*
226 * FCoE KCQ CQE 286 * FCoE KCQ CQE $$KEEP_ENDIANNESS$$
227 */ 287 */
228struct fcoe_kcqe { 288struct fcoe_kcqe {
229 u32 fcoe_conn_id; 289 __le32 fcoe_conn_id;
230 u32 completion_status; 290 __le32 completion_status;
231 u32 fcoe_conn_context_id; 291 __le32 fcoe_conn_context_id;
232 union fcoe_kcqe_params params; 292 union fcoe_kcqe_params params;
233#if defined(__BIG_ENDIAN) 293 __le16 qe_self_seq;
234 u8 flags;
235#define FCOE_KCQE_RESERVED0 (0x7<<0)
236#define FCOE_KCQE_RESERVED0_SHIFT 0
237#define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
238#define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
239#define FCOE_KCQE_LAYER_CODE (0x7<<4)
240#define FCOE_KCQE_LAYER_CODE_SHIFT 4
241#define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
242#define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
243 u8 op_code;
244 u16 qe_self_seq;
245#elif defined(__LITTLE_ENDIAN)
246 u16 qe_self_seq;
247 u8 op_code; 294 u8 op_code;
248 u8 flags; 295 u8 flags;
249#define FCOE_KCQE_RESERVED0 (0x7<<0) 296#define FCOE_KCQE_RESERVED0 (0x7<<0)
@@ -254,23 +301,14 @@ struct fcoe_kcqe {
254#define FCOE_KCQE_LAYER_CODE_SHIFT 4 301#define FCOE_KCQE_LAYER_CODE_SHIFT 4
255#define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7) 302#define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
256#define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7 303#define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
257#endif
258}; 304};
259 305
306
307
260/* 308/*
261 * FCoE KWQE header 309 * FCoE KWQE header $$KEEP_ENDIANNESS$$
262 */ 310 */
263struct fcoe_kwqe_header { 311struct fcoe_kwqe_header {
264#if defined(__BIG_ENDIAN)
265 u8 flags;
266#define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
267#define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
268#define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
269#define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
270#define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
271#define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
272 u8 op_code;
273#elif defined(__LITTLE_ENDIAN)
274 u8 op_code; 312 u8 op_code;
275 u8 flags; 313 u8 flags;
276#define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0) 314#define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
@@ -279,50 +317,23 @@ struct fcoe_kwqe_header {
279#define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4 317#define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
280#define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7) 318#define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
281#define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7 319#define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
282#endif
283}; 320};
284 321
285/* 322/*
286 * FCoE firmware init request 1 323 * FCoE firmware init request 1 $$KEEP_ENDIANNESS$$
287 */ 324 */
288struct fcoe_kwqe_init1 { 325struct fcoe_kwqe_init1 {
289#if defined(__BIG_ENDIAN) 326 __le16 num_tasks;
290 struct fcoe_kwqe_header hdr; 327 struct fcoe_kwqe_header hdr;
291 u16 num_tasks; 328 __le32 task_list_pbl_addr_lo;
292#elif defined(__LITTLE_ENDIAN) 329 __le32 task_list_pbl_addr_hi;
293 u16 num_tasks; 330 __le32 dummy_buffer_addr_lo;
294 struct fcoe_kwqe_header hdr; 331 __le32 dummy_buffer_addr_hi;
295#endif 332 __le16 sq_num_wqes;
296 u32 task_list_pbl_addr_lo; 333 __le16 rq_num_wqes;
297 u32 task_list_pbl_addr_hi; 334 __le16 rq_buffer_log_size;
298 u32 dummy_buffer_addr_lo; 335 __le16 cq_num_wqes;
299 u32 dummy_buffer_addr_hi; 336 __le16 mtu;
300#if defined(__BIG_ENDIAN)
301 u16 rq_num_wqes;
302 u16 sq_num_wqes;
303#elif defined(__LITTLE_ENDIAN)
304 u16 sq_num_wqes;
305 u16 rq_num_wqes;
306#endif
307#if defined(__BIG_ENDIAN)
308 u16 cq_num_wqes;
309 u16 rq_buffer_log_size;
310#elif defined(__LITTLE_ENDIAN)
311 u16 rq_buffer_log_size;
312 u16 cq_num_wqes;
313#endif
314#if defined(__BIG_ENDIAN)
315 u8 flags;
316#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
317#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
318#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
319#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
320#define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
321#define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
322 u8 num_sessions_log;
323 u16 mtu;
324#elif defined(__LITTLE_ENDIAN)
325 u16 mtu;
326 u8 num_sessions_log; 337 u8 num_sessions_log;
327 u8 flags; 338 u8 flags;
328#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0) 339#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
@@ -331,113 +342,73 @@ struct fcoe_kwqe_init1 {
331#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4 342#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
332#define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7) 343#define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
333#define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7 344#define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
334#endif
335}; 345};
336 346
337/* 347/*
338 * FCoE firmware init request 2 348 * FCoE firmware init request 2 $$KEEP_ENDIANNESS$$
339 */ 349 */
340struct fcoe_kwqe_init2 { 350struct fcoe_kwqe_init2 {
341#if defined(__BIG_ENDIAN) 351 u8 hsi_major_version;
342 struct fcoe_kwqe_header hdr; 352 u8 hsi_minor_version;
343 u16 reserved0;
344#elif defined(__LITTLE_ENDIAN)
345 u16 reserved0;
346 struct fcoe_kwqe_header hdr; 353 struct fcoe_kwqe_header hdr;
347#endif 354 __le32 hash_tbl_pbl_addr_lo;
348 u32 hash_tbl_pbl_addr_lo; 355 __le32 hash_tbl_pbl_addr_hi;
349 u32 hash_tbl_pbl_addr_hi; 356 __le32 t2_hash_tbl_addr_lo;
350 u32 t2_hash_tbl_addr_lo; 357 __le32 t2_hash_tbl_addr_hi;
351 u32 t2_hash_tbl_addr_hi; 358 __le32 t2_ptr_hash_tbl_addr_lo;
352 u32 t2_ptr_hash_tbl_addr_lo; 359 __le32 t2_ptr_hash_tbl_addr_hi;
353 u32 t2_ptr_hash_tbl_addr_hi; 360 __le32 free_list_count;
354 u32 free_list_count;
355}; 361};
356 362
357/* 363/*
358 * FCoE firmware init request 3 364 * FCoE firmware init request 3 $$KEEP_ENDIANNESS$$
359 */ 365 */
360struct fcoe_kwqe_init3 { 366struct fcoe_kwqe_init3 {
361#if defined(__BIG_ENDIAN) 367 __le16 reserved0;
362 struct fcoe_kwqe_header hdr;
363 u16 reserved0;
364#elif defined(__LITTLE_ENDIAN)
365 u16 reserved0;
366 struct fcoe_kwqe_header hdr; 368 struct fcoe_kwqe_header hdr;
367#endif 369 __le32 error_bit_map_lo;
368 u32 error_bit_map_lo; 370 __le32 error_bit_map_hi;
369 u32 error_bit_map_hi; 371 u8 perf_config;
370#if defined(__BIG_ENDIAN)
371 u8 reserved21[3];
372 u8 cached_session_enable;
373#elif defined(__LITTLE_ENDIAN)
374 u8 cached_session_enable;
375 u8 reserved21[3]; 372 u8 reserved21[3];
376#endif 373 __le32 reserved2[4];
377 u32 reserved2[4];
378}; 374};
379 375
380/* 376/*
381 * FCoE connection offload request 1 377 * FCoE connection offload request 1 $$KEEP_ENDIANNESS$$
382 */ 378 */
383struct fcoe_kwqe_conn_offload1 { 379struct fcoe_kwqe_conn_offload1 {
384#if defined(__BIG_ENDIAN) 380 __le16 fcoe_conn_id;
385 struct fcoe_kwqe_header hdr; 381 struct fcoe_kwqe_header hdr;
386 u16 fcoe_conn_id; 382 __le32 sq_addr_lo;
387#elif defined(__LITTLE_ENDIAN) 383 __le32 sq_addr_hi;
388 u16 fcoe_conn_id; 384 __le32 rq_pbl_addr_lo;
389 struct fcoe_kwqe_header hdr; 385 __le32 rq_pbl_addr_hi;
390#endif 386 __le32 rq_first_pbe_addr_lo;
391 u32 sq_addr_lo; 387 __le32 rq_first_pbe_addr_hi;
392 u32 sq_addr_hi; 388 __le16 rq_prod;
393 u32 rq_pbl_addr_lo; 389 __le16 reserved0;
394 u32 rq_pbl_addr_hi;
395 u32 rq_first_pbe_addr_lo;
396 u32 rq_first_pbe_addr_hi;
397#if defined(__BIG_ENDIAN)
398 u16 reserved0;
399 u16 rq_prod;
400#elif defined(__LITTLE_ENDIAN)
401 u16 rq_prod;
402 u16 reserved0;
403#endif
404}; 390};
405 391
406/* 392/*
407 * FCoE connection offload request 2 393 * FCoE connection offload request 2 $$KEEP_ENDIANNESS$$
408 */ 394 */
409struct fcoe_kwqe_conn_offload2 { 395struct fcoe_kwqe_conn_offload2 {
410#if defined(__BIG_ENDIAN) 396 __le16 tx_max_fc_pay_len;
411 struct fcoe_kwqe_header hdr;
412 u16 tx_max_fc_pay_len;
413#elif defined(__LITTLE_ENDIAN)
414 u16 tx_max_fc_pay_len;
415 struct fcoe_kwqe_header hdr; 397 struct fcoe_kwqe_header hdr;
416#endif 398 __le32 cq_addr_lo;
417 u32 cq_addr_lo; 399 __le32 cq_addr_hi;
418 u32 cq_addr_hi; 400 __le32 xferq_addr_lo;
419 u32 xferq_addr_lo; 401 __le32 xferq_addr_hi;
420 u32 xferq_addr_hi; 402 __le32 conn_db_addr_lo;
421 u32 conn_db_addr_lo; 403 __le32 conn_db_addr_hi;
422 u32 conn_db_addr_hi; 404 __le32 reserved1;
423 u32 reserved1;
424}; 405};
425 406
426/* 407/*
427 * FCoE connection offload request 3 408 * FCoE connection offload request 3 $$KEEP_ENDIANNESS$$
428 */ 409 */
429struct fcoe_kwqe_conn_offload3 { 410struct fcoe_kwqe_conn_offload3 {
430#if defined(__BIG_ENDIAN) 411 __le16 vlan_tag;
431 struct fcoe_kwqe_header hdr;
432 u16 vlan_tag;
433#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
434#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
435#define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
436#define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
437#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
438#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
439#elif defined(__LITTLE_ENDIAN)
440 u16 vlan_tag;
441#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0) 412#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
442#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0 413#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
443#define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12) 414#define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
@@ -445,34 +416,8 @@ struct fcoe_kwqe_conn_offload3 {
445#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13) 416#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
446#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13 417#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
447 struct fcoe_kwqe_header hdr; 418 struct fcoe_kwqe_header hdr;
448#endif
449#if defined(__BIG_ENDIAN)
450 u8 tx_max_conc_seqs_c3;
451 u8 s_id[3];
452#elif defined(__LITTLE_ENDIAN)
453 u8 s_id[3]; 419 u8 s_id[3];
454 u8 tx_max_conc_seqs_c3; 420 u8 tx_max_conc_seqs_c3;
455#endif
456#if defined(__BIG_ENDIAN)
457 u8 flags;
458#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
459#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
460#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
461#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
462#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
463#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
464#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
465#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
466#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
467#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
468#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
469#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
470#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
471#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
472#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
473#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
474 u8 d_id[3];
475#elif defined(__LITTLE_ENDIAN)
476 u8 d_id[3]; 421 u8 d_id[3];
477 u8 flags; 422 u8 flags;
478#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0) 423#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
@@ -491,79 +436,44 @@ struct fcoe_kwqe_conn_offload3 {
491#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6 436#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
492#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7) 437#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
493#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7 438#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
494#endif 439 __le32 reserved;
495 u32 reserved; 440 __le32 confq_first_pbe_addr_lo;
496 u32 confq_first_pbe_addr_lo; 441 __le32 confq_first_pbe_addr_hi;
497 u32 confq_first_pbe_addr_hi; 442 __le16 tx_total_conc_seqs;
498#if defined(__BIG_ENDIAN) 443 __le16 rx_max_fc_pay_len;
499 u16 rx_max_fc_pay_len; 444 __le16 rx_total_conc_seqs;
500 u16 tx_total_conc_seqs;
501#elif defined(__LITTLE_ENDIAN)
502 u16 tx_total_conc_seqs;
503 u16 rx_max_fc_pay_len;
504#endif
505#if defined(__BIG_ENDIAN)
506 u8 rx_open_seqs_exch_c3;
507 u8 rx_max_conc_seqs_c3;
508 u16 rx_total_conc_seqs;
509#elif defined(__LITTLE_ENDIAN)
510 u16 rx_total_conc_seqs;
511 u8 rx_max_conc_seqs_c3; 445 u8 rx_max_conc_seqs_c3;
512 u8 rx_open_seqs_exch_c3; 446 u8 rx_open_seqs_exch_c3;
513#endif
514}; 447};
515 448
516/* 449/*
517 * FCoE connection offload request 4 450 * FCoE connection offload request 4 $$KEEP_ENDIANNESS$$
518 */ 451 */
519struct fcoe_kwqe_conn_offload4 { 452struct fcoe_kwqe_conn_offload4 {
520#if defined(__BIG_ENDIAN)
521 struct fcoe_kwqe_header hdr;
522 u8 reserved2;
523 u8 e_d_tov_timer_val;
524#elif defined(__LITTLE_ENDIAN)
525 u8 e_d_tov_timer_val; 453 u8 e_d_tov_timer_val;
526 u8 reserved2; 454 u8 reserved2;
527 struct fcoe_kwqe_header hdr; 455 struct fcoe_kwqe_header hdr;
528#endif 456 u8 src_mac_addr_lo[2];
529 u8 src_mac_addr_lo32[4]; 457 u8 src_mac_addr_mid[2];
530#if defined(__BIG_ENDIAN) 458 u8 src_mac_addr_hi[2];
531 u8 dst_mac_addr_hi16[2]; 459 u8 dst_mac_addr_hi[2];
532 u8 src_mac_addr_hi16[2]; 460 u8 dst_mac_addr_lo[2];
533#elif defined(__LITTLE_ENDIAN) 461 u8 dst_mac_addr_mid[2];
534 u8 src_mac_addr_hi16[2]; 462 __le32 lcq_addr_lo;
535 u8 dst_mac_addr_hi16[2]; 463 __le32 lcq_addr_hi;
536#endif 464 __le32 confq_pbl_base_addr_lo;
537 u8 dst_mac_addr_lo32[4]; 465 __le32 confq_pbl_base_addr_hi;
538 u32 lcq_addr_lo;
539 u32 lcq_addr_hi;
540 u32 confq_pbl_base_addr_lo;
541 u32 confq_pbl_base_addr_hi;
542}; 466};
543 467
544/* 468/*
545 * FCoE connection enable request 469 * FCoE connection enable request $$KEEP_ENDIANNESS$$
546 */ 470 */
547struct fcoe_kwqe_conn_enable_disable { 471struct fcoe_kwqe_conn_enable_disable {
548#if defined(__BIG_ENDIAN) 472 __le16 reserved0;
549 struct fcoe_kwqe_header hdr;
550 u16 reserved0;
551#elif defined(__LITTLE_ENDIAN)
552 u16 reserved0;
553 struct fcoe_kwqe_header hdr; 473 struct fcoe_kwqe_header hdr;
554#endif 474 u8 src_mac_addr_lo[2];
555 u8 src_mac_addr_lo32[4]; 475 u8 src_mac_addr_mid[2];
556#if defined(__BIG_ENDIAN) 476 u8 src_mac_addr_hi[2];
557 u16 vlan_tag;
558#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
559#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
560#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
561#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
562#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
563#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
564 u8 src_mac_addr_hi16[2];
565#elif defined(__LITTLE_ENDIAN)
566 u8 src_mac_addr_hi16[2];
567 u16 vlan_tag; 477 u16 vlan_tag;
568#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0) 478#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
569#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0 479#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
@@ -571,82 +481,52 @@ struct fcoe_kwqe_conn_enable_disable {
571#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12 481#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
572#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13) 482#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
573#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13 483#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
574#endif 484 u8 dst_mac_addr_lo[2];
575 u8 dst_mac_addr_lo32[4]; 485 u8 dst_mac_addr_mid[2];
576#if defined(__BIG_ENDIAN) 486 u8 dst_mac_addr_hi[2];
577 u16 reserved1; 487 __le16 reserved1;
578 u8 dst_mac_addr_hi16[2];
579#elif defined(__LITTLE_ENDIAN)
580 u8 dst_mac_addr_hi16[2];
581 u16 reserved1;
582#endif
583#if defined(__BIG_ENDIAN)
584 u8 vlan_flag;
585 u8 s_id[3];
586#elif defined(__LITTLE_ENDIAN)
587 u8 s_id[3]; 488 u8 s_id[3];
588 u8 vlan_flag; 489 u8 vlan_flag;
589#endif
590#if defined(__BIG_ENDIAN)
591 u8 reserved3;
592 u8 d_id[3];
593#elif defined(__LITTLE_ENDIAN)
594 u8 d_id[3]; 490 u8 d_id[3];
595 u8 reserved3; 491 u8 reserved3;
596#endif 492 __le32 context_id;
597 u32 context_id; 493 __le32 conn_id;
598 u32 conn_id; 494 __le32 reserved4;
599 u32 reserved4;
600}; 495};
601 496
602/* 497/*
603 * FCoE connection destroy request 498 * FCoE connection destroy request $$KEEP_ENDIANNESS$$
604 */ 499 */
605struct fcoe_kwqe_conn_destroy { 500struct fcoe_kwqe_conn_destroy {
606#if defined(__BIG_ENDIAN) 501 __le16 reserved0;
607 struct fcoe_kwqe_header hdr;
608 u16 reserved0;
609#elif defined(__LITTLE_ENDIAN)
610 u16 reserved0;
611 struct fcoe_kwqe_header hdr; 502 struct fcoe_kwqe_header hdr;
612#endif 503 __le32 context_id;
613 u32 context_id; 504 __le32 conn_id;
614 u32 conn_id; 505 __le32 reserved1[5];
615 u32 reserved1[5];
616}; 506};
617 507
618/* 508/*
619 * FCoe destroy request 509 * FCoe destroy request $$KEEP_ENDIANNESS$$
620 */ 510 */
621struct fcoe_kwqe_destroy { 511struct fcoe_kwqe_destroy {
622#if defined(__BIG_ENDIAN) 512 __le16 reserved0;
623 struct fcoe_kwqe_header hdr;
624 u16 reserved0;
625#elif defined(__LITTLE_ENDIAN)
626 u16 reserved0;
627 struct fcoe_kwqe_header hdr; 513 struct fcoe_kwqe_header hdr;
628#endif 514 __le32 reserved1[7];
629 u32 reserved1[7];
630}; 515};
631 516
632/* 517/*
633 * FCoe statistics request 518 * FCoe statistics request $$KEEP_ENDIANNESS$$
634 */ 519 */
635struct fcoe_kwqe_stat { 520struct fcoe_kwqe_stat {
636#if defined(__BIG_ENDIAN) 521 __le16 reserved0;
637 struct fcoe_kwqe_header hdr; 522 struct fcoe_kwqe_header hdr;
638 u16 reserved0; 523 __le32 stat_params_addr_lo;
639#elif defined(__LITTLE_ENDIAN) 524 __le32 stat_params_addr_hi;
640 u16 reserved0; 525 __le32 reserved1[5];
641 struct fcoe_kwqe_header hdr;
642#endif
643 u32 stat_params_addr_lo;
644 u32 stat_params_addr_hi;
645 u32 reserved1[5];
646}; 526};
647 527
648/* 528/*
649 * FCoE KWQ WQE 529 * FCoE KWQ WQE $$KEEP_ENDIANNESS$$
650 */ 530 */
651union fcoe_kwqe { 531union fcoe_kwqe {
652 struct fcoe_kwqe_init1 init1; 532 struct fcoe_kwqe_init1 init1;
@@ -662,19 +542,42 @@ union fcoe_kwqe {
662 struct fcoe_kwqe_stat statistics; 542 struct fcoe_kwqe_stat statistics;
663}; 543};
664 544
665struct fcoe_mul_sges_ctx { 545
666 struct regpair cur_sge_addr; 546
667#if defined(__BIG_ENDIAN) 547
668 u8 sgl_size; 548
669 u8 cur_sge_idx; 549
670 u16 cur_sge_off; 550
671#elif defined(__LITTLE_ENDIAN) 551
672 u16 cur_sge_off; 552
673 u8 cur_sge_idx; 553
674 u8 sgl_size; 554
675#endif 555
556
557
558
559
560/*
561 * TX SGL context $$KEEP_ENDIANNESS$$
562 */
563union fcoe_sgl_union_ctx {
564 struct fcoe_cached_sge_ctx cached_sge;
565 struct fcoe_ext_mul_sges_ctx sgl;
566 __le32 opaque[5];
676}; 567};
677 568
569/*
570 * Data-In/ELS/BLS information $$KEEP_ENDIANNESS$$
571 */
572struct fcoe_read_flow_info {
573 union fcoe_sgl_union_ctx sgl_ctx;
574 __le32 rsrv0[3];
575};
576
577
578/*
579 * Fcoe stat context $$KEEP_ENDIANNESS$$
580 */
678struct fcoe_s_stat_ctx { 581struct fcoe_s_stat_ctx {
679 u8 flags; 582 u8 flags;
680#define FCOE_S_STAT_CTX_ACTIVE (0x1<<0) 583#define FCOE_S_STAT_CTX_ACTIVE (0x1<<0)
@@ -693,51 +596,34 @@ struct fcoe_s_stat_ctx {
693#define FCOE_S_STAT_CTX_RSRV1_SHIFT 6 596#define FCOE_S_STAT_CTX_RSRV1_SHIFT 6
694}; 597};
695 598
696struct fcoe_seq_ctx { 599/*
697#if defined(__BIG_ENDIAN) 600 * Fcoe rx seq context $$KEEP_ENDIANNESS$$
698 u16 low_seq_cnt; 601 */
699 struct fcoe_s_stat_ctx s_stat; 602struct fcoe_rx_seq_ctx {
700 u8 seq_id;
701#elif defined(__LITTLE_ENDIAN)
702 u8 seq_id; 603 u8 seq_id;
703 struct fcoe_s_stat_ctx s_stat; 604 struct fcoe_s_stat_ctx s_stat;
704 u16 low_seq_cnt; 605 __le16 seq_cnt;
705#endif 606 __le32 low_exp_ro;
706#if defined(__BIG_ENDIAN) 607 __le32 high_exp_ro;
707 u16 err_seq_cnt;
708 u16 high_seq_cnt;
709#elif defined(__LITTLE_ENDIAN)
710 u16 high_seq_cnt;
711 u16 err_seq_cnt;
712#endif
713 u32 low_exp_ro;
714 u32 high_exp_ro;
715}; 608};
716 609
717 610
718struct fcoe_single_sge_ctx { 611/*
719 struct regpair cur_buf_addr; 612 * Fcoe rx_wr union context $$KEEP_ENDIANNESS$$
720#if defined(__BIG_ENDIAN) 613 */
721 u16 reserved0; 614union fcoe_rx_wr_union_ctx {
722 u16 cur_buf_rem; 615 struct fcoe_read_flow_info read_info;
723#elif defined(__LITTLE_ENDIAN) 616 union fcoe_comp_flow_info comp_info;
724 u16 cur_buf_rem; 617 __le32 opaque[8];
725 u16 reserved0;
726#endif
727};
728
729union fcoe_sgl_ctx {
730 struct fcoe_single_sge_ctx single_sge;
731 struct fcoe_mul_sges_ctx mul_sges;
732}; 618};
733 619
734 620
735 621
736/* 622/*
737 * FCoE SQ element 623 * FCoE SQ element $$KEEP_ENDIANNESS$$
738 */ 624 */
739struct fcoe_sqe { 625struct fcoe_sqe {
740 u16 wqe; 626 __le16 wqe;
741#define FCOE_SQE_TASK_ID (0x7FFF<<0) 627#define FCOE_SQE_TASK_ID (0x7FFF<<0)
742#define FCOE_SQE_TASK_ID_SHIFT 0 628#define FCOE_SQE_TASK_ID_SHIFT 0
743#define FCOE_SQE_TOGGLE_BIT (0x1<<15) 629#define FCOE_SQE_TOGGLE_BIT (0x1<<15)
@@ -746,135 +632,141 @@ struct fcoe_sqe {
746 632
747 633
748 634
749struct fcoe_task_ctx_entry_tx_only { 635/*
750 union fcoe_sgl_ctx sgl_ctx; 636 * 14 regs $$KEEP_ENDIANNESS$$
637 */
638struct fcoe_tce_tx_only {
639 union fcoe_sgl_union_ctx sgl_ctx;
640 __le32 rsrv0;
751}; 641};
752 642
753struct fcoe_task_ctx_entry_txwr_rxrd { 643/*
754#if defined(__BIG_ENDIAN) 644 * 32 bytes (8 regs) used for TX only purposes $$KEEP_ENDIANNESS$$
755 u16 verify_tx_seq; 645 */
646union fcoe_tx_wr_rx_rd_union_ctx {
647 struct fcoe_fc_frame tx_frame;
648 struct fcoe_fcp_cmd_payload fcp_cmd;
649 struct fcoe_ext_cleanup_info cleanup;
650 struct fcoe_ext_abts_info abts;
651 struct fcoe_ext_fw_tx_seq_ctx tx_seq;
652 __le32 opaque[8];
653};
654
655/*
656 * tce_tx_wr_rx_rd_const $$KEEP_ENDIANNESS$$
657 */
658struct fcoe_tce_tx_wr_rx_rd_const {
756 u8 init_flags; 659 u8 init_flags;
757#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE (0x7<<0) 660#define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0)
758#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT 0 661#define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0
759#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE (0x1<<3) 662#define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3)
760#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT 3 663#define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT 3
761#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE (0x1<<4) 664#define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4)
762#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT 4 665#define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT 4
763#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE (0x1<<5) 666#define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE (0x3<<5)
764#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT 5 667#define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT 5
765#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5 (0x3<<6) 668#define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7)
766#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5_SHIFT 6 669#define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV_SHIFT 7
767 u8 tx_flags;
768#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE (0xF<<0)
769#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT 0
770#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4 (0xF<<4)
771#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4_SHIFT 4
772#elif defined(__LITTLE_ENDIAN)
773 u8 tx_flags; 670 u8 tx_flags;
774#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE (0xF<<0) 671#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0)
775#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT 0 672#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0
776#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4 (0xF<<4) 673#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1)
777#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4_SHIFT 4 674#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT 1
778 u8 init_flags; 675#define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5)
779#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE (0x7<<0) 676#define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5
780#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT 0 677#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6)
781#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE (0x1<<3) 678#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6
782#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT 3 679#define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2 (0x1<<7)
783#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE (0x1<<4) 680#define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2_SHIFT 7
784#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT 4 681 __le16 rsrv3;
785#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE (0x1<<5) 682 __le32 verify_tx_seq;
786#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT 5
787#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5 (0x3<<6)
788#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5_SHIFT 6
789 u16 verify_tx_seq;
790#endif
791}; 683};
792 684
793/* 685/*
794 * Common section. Both TX and RX processing might write and read from it in 686 * tce_tx_wr_rx_rd $$KEEP_ENDIANNESS$$
795 * different flows
796 */ 687 */
797struct fcoe_task_ctx_entry_tx_rx_cmn { 688struct fcoe_tce_tx_wr_rx_rd {
798 u32 data_2_trns; 689 union fcoe_tx_wr_rx_rd_union_ctx union_ctx;
799 union fcoe_general_task_ctx general; 690 struct fcoe_tce_tx_wr_rx_rd_const const_ctx;
800#if defined(__BIG_ENDIAN)
801 u16 tx_low_seq_cnt;
802 struct fcoe_s_stat_ctx tx_s_stat;
803 u8 tx_seq_id;
804#elif defined(__LITTLE_ENDIAN)
805 u8 tx_seq_id;
806 struct fcoe_s_stat_ctx tx_s_stat;
807 u16 tx_low_seq_cnt;
808#endif
809 u32 common_flags;
810#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID (0xFFFFFF<<0)
811#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT 0
812#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID (0x1<<24)
813#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID_SHIFT 24
814#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT (0x1<<25)
815#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT_SHIFT 25
816#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_XFER (0x1<<26)
817#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_XFER_SHIFT 26
818#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_CONF (0x1<<27)
819#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_CONF_SHIFT 27
820#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME (0x1<<28)
821#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME_SHIFT 28
822#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_RSRV (0x7<<29)
823#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_RSRV_SHIFT 29
824};
825
826struct fcoe_task_ctx_entry_rxwr_txrd {
827#if defined(__BIG_ENDIAN)
828 u16 rx_id;
829 u16 rx_flags;
830#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE (0xF<<0)
831#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT 0
832#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE (0x7<<4)
833#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT 4
834#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ (0x1<<7)
835#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ_SHIFT 7
836#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME (0x1<<8)
837#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME_SHIFT 8
838#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0 (0x7F<<9)
839#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0_SHIFT 9
840#elif defined(__LITTLE_ENDIAN)
841 u16 rx_flags;
842#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE (0xF<<0)
843#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT 0
844#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE (0x7<<4)
845#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT 4
846#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ (0x1<<7)
847#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ_SHIFT 7
848#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME (0x1<<8)
849#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME_SHIFT 8
850#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0 (0x7F<<9)
851#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0_SHIFT 9
852 u16 rx_id;
853#endif
854}; 691};
855 692
856struct fcoe_task_ctx_entry_rx_only { 693/*
857 struct fcoe_seq_ctx seq_ctx; 694 * tce_rx_wr_tx_rd_const $$KEEP_ENDIANNESS$$
858 struct fcoe_seq_ctx ooo_seq_ctx; 695 */
859 u32 rsrv3; 696struct fcoe_tce_rx_wr_tx_rd_const {
860 union fcoe_sgl_ctx sgl_ctx; 697 __le32 data_2_trns;
698 __le32 init_flags;
699#define FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0)
700#define FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0
701#define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24)
702#define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0_SHIFT 24
703};
704
705/*
706 * tce_rx_wr_tx_rd_var $$KEEP_ENDIANNESS$$
707 */
708struct fcoe_tce_rx_wr_tx_rd_var {
709 __le16 rx_flags;
710#define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0)
711#define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0
712#define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4)
713#define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT 4
714#define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7)
715#define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ_SHIFT 7
716#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8)
717#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT 8
718#define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12)
719#define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT 12
720#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13)
721#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT_SHIFT 13
722#define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14)
723#define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2_SHIFT 14
724#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15)
725#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID_SHIFT 15
726 __le16 rx_id;
727 struct fcoe_fcp_xfr_rdy_payload fcp_xfr_rdy;
728};
729
730/*
731 * tce_rx_wr_tx_rd $$KEEP_ENDIANNESS$$
732 */
733struct fcoe_tce_rx_wr_tx_rd {
734 struct fcoe_tce_rx_wr_tx_rd_const const_ctx;
735 struct fcoe_tce_rx_wr_tx_rd_var var_ctx;
736};
737
738/*
739 * tce_rx_only $$KEEP_ENDIANNESS$$
740 */
741struct fcoe_tce_rx_only {
742 struct fcoe_rx_seq_ctx rx_seq_ctx;
743 union fcoe_rx_wr_union_ctx union_ctx;
861}; 744};
862 745
746/*
747 * task_ctx_entry $$KEEP_ENDIANNESS$$
748 */
863struct fcoe_task_ctx_entry { 749struct fcoe_task_ctx_entry {
864 struct fcoe_task_ctx_entry_tx_only tx_wr_only; 750 struct fcoe_tce_tx_only txwr_only;
865 struct fcoe_task_ctx_entry_txwr_rxrd tx_wr_rx_rd; 751 struct fcoe_tce_tx_wr_rx_rd txwr_rxrd;
866 struct fcoe_task_ctx_entry_tx_rx_cmn cmn; 752 struct fcoe_tce_rx_wr_tx_rd rxwr_txrd;
867 struct fcoe_task_ctx_entry_rxwr_txrd rx_wr_tx_rd; 753 struct fcoe_tce_rx_only rxwr_only;
868 struct fcoe_task_ctx_entry_rx_only rx_wr_only;
869 u32 reserved[4];
870}; 754};
871 755
872 756
757
758
759
760
761
762
763
764
873/* 765/*
874 * FCoE XFRQ element 766 * FCoE XFRQ element $$KEEP_ENDIANNESS$$
875 */ 767 */
876struct fcoe_xfrqe { 768struct fcoe_xfrqe {
877 u16 wqe; 769 __le16 wqe;
878#define FCOE_XFRQE_TASK_ID (0x7FFF<<0) 770#define FCOE_XFRQE_TASK_ID (0x7FFF<<0)
879#define FCOE_XFRQE_TASK_ID_SHIFT 0 771#define FCOE_XFRQE_TASK_ID_SHIFT 0
880#define FCOE_XFRQE_TOGGLE_BIT (0x1<<15) 772#define FCOE_XFRQE_TOGGLE_BIT (0x1<<15)
@@ -883,22 +775,31 @@ struct fcoe_xfrqe {
883 775
884 776
885/* 777/*
886 * FCoE CONFQ element 778 * fcoe rx doorbell message sent to the chip $$KEEP_ENDIANNESS$$
779 */
780struct b577xx_fcoe_rx_doorbell {
781 struct b577xx_doorbell_hdr hdr;
782 u8 params;
783#define B577XX_FCOE_RX_DOORBELL_NEGATIVE_ARM (0x1F<<0)
784#define B577XX_FCOE_RX_DOORBELL_NEGATIVE_ARM_SHIFT 0
785#define B577XX_FCOE_RX_DOORBELL_OPCODE (0x7<<5)
786#define B577XX_FCOE_RX_DOORBELL_OPCODE_SHIFT 5
787 __le16 doorbell_cq_cons;
788};
789
790
791/*
792 * FCoE CONFQ element $$KEEP_ENDIANNESS$$
887 */ 793 */
888struct fcoe_confqe { 794struct fcoe_confqe {
889#if defined(__BIG_ENDIAN) 795 __le16 ox_id;
890 u16 rx_id; 796 __le16 rx_id;
891 u16 ox_id; 797 __le32 param;
892#elif defined(__LITTLE_ENDIAN)
893 u16 ox_id;
894 u16 rx_id;
895#endif
896 u32 param;
897}; 798};
898 799
899 800
900/* 801/*
901 * FCoE connection data base 802 * FCoE conection data base
902 */ 803 */
903struct fcoe_conn_db { 804struct fcoe_conn_db {
904#if defined(__BIG_ENDIAN) 805#if defined(__BIG_ENDIAN)
@@ -914,10 +815,10 @@ struct fcoe_conn_db {
914 815
915 816
916/* 817/*
917 * FCoE CQ element 818 * FCoE CQ element $$KEEP_ENDIANNESS$$
918 */ 819 */
919struct fcoe_cqe { 820struct fcoe_cqe {
920 u16 wqe; 821 __le16 wqe;
921#define FCOE_CQE_CQE_INFO (0x3FFF<<0) 822#define FCOE_CQE_CQE_INFO (0x3FFF<<0)
922#define FCOE_CQE_CQE_INFO_SHIFT 0 823#define FCOE_CQE_CQE_INFO_SHIFT 0
923#define FCOE_CQE_CQE_TYPE (0x1<<14) 824#define FCOE_CQE_CQE_TYPE (0x1<<14)
@@ -928,61 +829,46 @@ struct fcoe_cqe {
928 829
929 830
930/* 831/*
931 * FCoE error/warning resporting entry 832 * FCoE error/warning reporting entry $$KEEP_ENDIANNESS$$
833 */
834struct fcoe_partial_err_report_entry {
835 __le32 err_warn_bitmap_lo;
836 __le32 err_warn_bitmap_hi;
837 __le32 tx_buf_off;
838 __le32 rx_buf_off;
839};
840
841/*
842 * FCoE error/warning reporting entry $$KEEP_ENDIANNESS$$
932 */ 843 */
933struct fcoe_err_report_entry { 844struct fcoe_err_report_entry {
934 u32 err_warn_bitmap_lo; 845 struct fcoe_partial_err_report_entry data;
935 u32 err_warn_bitmap_hi;
936 u32 tx_buf_off;
937 u32 rx_buf_off;
938 struct fcoe_fc_hdr fc_hdr; 846 struct fcoe_fc_hdr fc_hdr;
939}; 847};
940 848
941 849
942/* 850/*
943 * FCoE hash table entry (32 bytes) 851 * FCoE hash table entry (32 bytes) $$KEEP_ENDIANNESS$$
944 */ 852 */
945struct fcoe_hash_table_entry { 853struct fcoe_hash_table_entry {
946#if defined(__BIG_ENDIAN)
947 u8 d_id_0;
948 u8 s_id_2;
949 u8 s_id_1;
950 u8 s_id_0;
951#elif defined(__LITTLE_ENDIAN)
952 u8 s_id_0; 854 u8 s_id_0;
953 u8 s_id_1; 855 u8 s_id_1;
954 u8 s_id_2; 856 u8 s_id_2;
955 u8 d_id_0; 857 u8 d_id_0;
956#endif
957#if defined(__BIG_ENDIAN)
958 u16 dst_mac_addr_hi;
959 u8 d_id_2;
960 u8 d_id_1;
961#elif defined(__LITTLE_ENDIAN)
962 u8 d_id_1; 858 u8 d_id_1;
963 u8 d_id_2; 859 u8 d_id_2;
964 u16 dst_mac_addr_hi; 860 __le16 dst_mac_addr_hi;
965#endif 861 __le16 dst_mac_addr_mid;
966 u32 dst_mac_addr_lo; 862 __le16 dst_mac_addr_lo;
967#if defined(__BIG_ENDIAN) 863 __le16 src_mac_addr_hi;
968 u16 vlan_id; 864 __le16 vlan_id;
969 u16 src_mac_addr_hi; 865 __le16 src_mac_addr_lo;
970#elif defined(__LITTLE_ENDIAN) 866 __le16 src_mac_addr_mid;
971 u16 src_mac_addr_hi;
972 u16 vlan_id;
973#endif
974 u32 src_mac_addr_lo;
975#if defined(__BIG_ENDIAN)
976 u16 reserved1;
977 u8 reserved0;
978 u8 vlan_flag;
979#elif defined(__LITTLE_ENDIAN)
980 u8 vlan_flag; 867 u8 vlan_flag;
981 u8 reserved0; 868 u8 reserved0;
982 u16 reserved1; 869 __le16 reserved1;
983#endif 870 __le32 reserved2;
984 u32 reserved2; 871 __le32 field_id;
985 u32 field_id;
986#define FCOE_HASH_TABLE_ENTRY_CID (0xFFFFFF<<0) 872#define FCOE_HASH_TABLE_ENTRY_CID (0xFFFFFF<<0)
987#define FCOE_HASH_TABLE_ENTRY_CID_SHIFT 0 873#define FCOE_HASH_TABLE_ENTRY_CID_SHIFT 0
988#define FCOE_HASH_TABLE_ENTRY_RESERVED3 (0x7F<<24) 874#define FCOE_HASH_TABLE_ENTRY_RESERVED3 (0x7F<<24)
@@ -991,11 +877,27 @@ struct fcoe_hash_table_entry {
991#define FCOE_HASH_TABLE_ENTRY_VALID_SHIFT 31 877#define FCOE_HASH_TABLE_ENTRY_VALID_SHIFT 31
992}; 878};
993 879
880
994/* 881/*
995 * FCoE pending work request CQE 882 * FCoE LCQ element $$KEEP_ENDIANNESS$$
883 */
884struct fcoe_lcqe {
885 __le32 wqe;
886#define FCOE_LCQE_TASK_ID (0xFFFF<<0)
887#define FCOE_LCQE_TASK_ID_SHIFT 0
888#define FCOE_LCQE_LCQE_TYPE (0xFF<<16)
889#define FCOE_LCQE_LCQE_TYPE_SHIFT 16
890#define FCOE_LCQE_RESERVED (0xFF<<24)
891#define FCOE_LCQE_RESERVED_SHIFT 24
892};
893
894
895
896/*
897 * FCoE pending work request CQE $$KEEP_ENDIANNESS$$
996 */ 898 */
997struct fcoe_pend_wq_cqe { 899struct fcoe_pend_wq_cqe {
998 u16 wqe; 900 __le16 wqe;
999#define FCOE_PEND_WQ_CQE_TASK_ID (0x3FFF<<0) 901#define FCOE_PEND_WQ_CQE_TASK_ID (0x3FFF<<0)
1000#define FCOE_PEND_WQ_CQE_TASK_ID_SHIFT 0 902#define FCOE_PEND_WQ_CQE_TASK_ID_SHIFT 0
1001#define FCOE_PEND_WQ_CQE_CQE_TYPE (0x1<<14) 903#define FCOE_PEND_WQ_CQE_CQE_TYPE (0x1<<14)
@@ -1006,53 +908,61 @@ struct fcoe_pend_wq_cqe {
1006 908
1007 909
1008/* 910/*
1009 * FCoE RX statistics parameters section#0 911 * FCoE RX statistics parameters section#0 $$KEEP_ENDIANNESS$$
1010 */ 912 */
1011struct fcoe_rx_stat_params_section0 { 913struct fcoe_rx_stat_params_section0 {
1012 u32 fcoe_ver_cnt; 914 __le32 fcoe_rx_pkt_cnt;
1013 u32 fcoe_rx_pkt_cnt; 915 __le32 fcoe_rx_byte_cnt;
1014 u32 fcoe_rx_byte_cnt;
1015 u32 fcoe_rx_drop_pkt_cnt;
1016}; 916};
1017 917
1018 918
1019/* 919/*
1020 * FCoE RX statistics parameters section#1 920 * FCoE RX statistics parameters section#1 $$KEEP_ENDIANNESS$$
1021 */ 921 */
1022struct fcoe_rx_stat_params_section1 { 922struct fcoe_rx_stat_params_section1 {
1023 u32 fc_crc_cnt; 923 __le32 fcoe_ver_cnt;
1024 u32 eofa_del_cnt; 924 __le32 fcoe_rx_drop_pkt_cnt;
1025 u32 miss_frame_cnt; 925};
1026 u32 seq_timeout_cnt; 926
1027 u32 drop_seq_cnt; 927
1028 u32 fcoe_rx_drop_pkt_cnt; 928/*
1029 u32 fcp_rx_pkt_cnt; 929 * FCoE RX statistics parameters section#2 $$KEEP_ENDIANNESS$$
1030 u32 reserved0; 930 */
931struct fcoe_rx_stat_params_section2 {
932 __le32 fc_crc_cnt;
933 __le32 eofa_del_cnt;
934 __le32 miss_frame_cnt;
935 __le32 seq_timeout_cnt;
936 __le32 drop_seq_cnt;
937 __le32 fcoe_rx_drop_pkt_cnt;
938 __le32 fcp_rx_pkt_cnt;
939 __le32 reserved0;
1031}; 940};
1032 941
1033 942
1034/* 943/*
1035 * FCoE TX statistics parameters 944 * FCoE TX statistics parameters $$KEEP_ENDIANNESS$$
1036 */ 945 */
1037struct fcoe_tx_stat_params { 946struct fcoe_tx_stat_params {
1038 u32 fcoe_tx_pkt_cnt; 947 __le32 fcoe_tx_pkt_cnt;
1039 u32 fcoe_tx_byte_cnt; 948 __le32 fcoe_tx_byte_cnt;
1040 u32 fcp_tx_pkt_cnt; 949 __le32 fcp_tx_pkt_cnt;
1041 u32 reserved0; 950 __le32 reserved0;
1042}; 951};
1043 952
1044/* 953/*
1045 * FCoE statistics parameters 954 * FCoE statistics parameters $$KEEP_ENDIANNESS$$
1046 */ 955 */
1047struct fcoe_statistics_params { 956struct fcoe_statistics_params {
1048 struct fcoe_tx_stat_params tx_stat; 957 struct fcoe_tx_stat_params tx_stat;
1049 struct fcoe_rx_stat_params_section0 rx_stat0; 958 struct fcoe_rx_stat_params_section0 rx_stat0;
1050 struct fcoe_rx_stat_params_section1 rx_stat1; 959 struct fcoe_rx_stat_params_section1 rx_stat1;
960 struct fcoe_rx_stat_params_section2 rx_stat2;
1051}; 961};
1052 962
1053 963
1054/* 964/*
1055 * FCoE t2 hash table entry (64 bytes) 965 * FCoE t2 hash table entry (64 bytes) $$KEEP_ENDIANNESS$$
1056 */ 966 */
1057struct fcoe_t2_hash_table_entry { 967struct fcoe_t2_hash_table_entry {
1058 struct fcoe_hash_table_entry data; 968 struct fcoe_hash_table_entry data;
@@ -1060,11 +970,13 @@ struct fcoe_t2_hash_table_entry {
1060 struct regpair reserved0[3]; 970 struct regpair reserved0[3];
1061}; 971};
1062 972
973
974
1063/* 975/*
1064 * FCoE unsolicited CQE 976 * FCoE unsolicited CQE $$KEEP_ENDIANNESS$$
1065 */ 977 */
1066struct fcoe_unsolicited_cqe { 978struct fcoe_unsolicited_cqe {
1067 u16 wqe; 979 __le16 wqe;
1068#define FCOE_UNSOLICITED_CQE_SUBTYPE (0x3<<0) 980#define FCOE_UNSOLICITED_CQE_SUBTYPE (0x3<<0)
1069#define FCOE_UNSOLICITED_CQE_SUBTYPE_SHIFT 0 981#define FCOE_UNSOLICITED_CQE_SUBTYPE_SHIFT 0
1070#define FCOE_UNSOLICITED_CQE_PKT_LEN (0xFFF<<2) 982#define FCOE_UNSOLICITED_CQE_PKT_LEN (0xFFF<<2)
@@ -1075,6 +987,4 @@ struct fcoe_unsolicited_cqe {
1075#define FCOE_UNSOLICITED_CQE_TOGGLE_BIT_SHIFT 15 987#define FCOE_UNSOLICITED_CQE_TOGGLE_BIT_SHIFT 15
1076}; 988};
1077 989
1078
1079
1080#endif /* __57XX_FCOE_HSI_LINUX_LE__ */ 990#endif /* __57XX_FCOE_HSI_LINUX_LE__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 18:59:18 -0500