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-rw-r--r--drivers/pci/access.c202
-rw-r--r--drivers/pci/hotplug/Kconfig24
-rw-r--r--drivers/pci/hotplug/Makefile3
-rw-r--r--drivers/pci/hotplug/acpiphp_glue.c46
-rw-r--r--drivers/pci/hotplug/fakephp.c164
-rw-r--r--drivers/pci/hotplug/pciehp_acpi.c6
-rw-r--r--drivers/pci/hotplug/pciehp_core.c28
-rw-r--r--drivers/pci/hotplug/pciehp_hpc.c12
-rw-r--r--drivers/pci/hotplug/pcihp_slot.c20
-rw-r--r--drivers/pci/iov.c6
-rw-r--r--drivers/pci/pci.c356
-rw-r--r--drivers/pci/pcie/aer/aer_inject.c2
-rw-r--r--drivers/pci/pcie/aer/aerdrv.c24
-rw-r--r--drivers/pci/pcie/aer/aerdrv_acpi.c2
-rw-r--r--drivers/pci/pcie/aer/aerdrv_core.c53
-rw-r--r--drivers/pci/pcie/aspm.c119
-rw-r--r--drivers/pci/pcie/pme.c29
-rw-r--r--drivers/pci/pcie/portdrv_bus.c2
-rw-r--r--drivers/pci/pcie/portdrv_core.c34
-rw-r--r--drivers/pci/pcie/portdrv_pci.c17
-rw-r--r--drivers/pci/probe.c28
-rw-r--r--drivers/pci/proc.c19
-rw-r--r--drivers/pci/quirks.c31
-rw-r--r--drivers/pci/remove.c131
-rw-r--r--drivers/pci/rom.c59
-rw-r--r--drivers/pci/search.c63
-rw-r--r--drivers/pci/setup-bus.c81
27 files changed, 565 insertions, 996 deletions
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index ba91a7e17519..3af0478c057b 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -469,3 +469,205 @@ void pci_cfg_access_unlock(struct pci_dev *dev)
469 raw_spin_unlock_irqrestore(&pci_lock, flags); 469 raw_spin_unlock_irqrestore(&pci_lock, flags);
470} 470}
471EXPORT_SYMBOL_GPL(pci_cfg_access_unlock); 471EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
472
473static inline int pcie_cap_version(const struct pci_dev *dev)
474{
475 return dev->pcie_flags_reg & PCI_EXP_FLAGS_VERS;
476}
477
478static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
479{
480 return true;
481}
482
483static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
484{
485 int type = pci_pcie_type(dev);
486
487 return pcie_cap_version(dev) > 1 ||
488 type == PCI_EXP_TYPE_ROOT_PORT ||
489 type == PCI_EXP_TYPE_ENDPOINT ||
490 type == PCI_EXP_TYPE_LEG_END;
491}
492
493static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
494{
495 int type = pci_pcie_type(dev);
496
497 return pcie_cap_version(dev) > 1 ||
498 type == PCI_EXP_TYPE_ROOT_PORT ||
499 (type == PCI_EXP_TYPE_DOWNSTREAM &&
500 dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT);
501}
502
503static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
504{
505 int type = pci_pcie_type(dev);
506
507 return pcie_cap_version(dev) > 1 ||
508 type == PCI_EXP_TYPE_ROOT_PORT ||
509 type == PCI_EXP_TYPE_RC_EC;
510}
511
512static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
513{
514 if (!pci_is_pcie(dev))
515 return false;
516
517 switch (pos) {
518 case PCI_EXP_FLAGS_TYPE:
519 return true;
520 case PCI_EXP_DEVCAP:
521 case PCI_EXP_DEVCTL:
522 case PCI_EXP_DEVSTA:
523 return pcie_cap_has_devctl(dev);
524 case PCI_EXP_LNKCAP:
525 case PCI_EXP_LNKCTL:
526 case PCI_EXP_LNKSTA:
527 return pcie_cap_has_lnkctl(dev);
528 case PCI_EXP_SLTCAP:
529 case PCI_EXP_SLTCTL:
530 case PCI_EXP_SLTSTA:
531 return pcie_cap_has_sltctl(dev);
532 case PCI_EXP_RTCTL:
533 case PCI_EXP_RTCAP:
534 case PCI_EXP_RTSTA:
535 return pcie_cap_has_rtctl(dev);
536 case PCI_EXP_DEVCAP2:
537 case PCI_EXP_DEVCTL2:
538 case PCI_EXP_LNKCAP2:
539 case PCI_EXP_LNKCTL2:
540 case PCI_EXP_LNKSTA2:
541 return pcie_cap_version(dev) > 1;
542 default:
543 return false;
544 }
545}
546
547/*
548 * Note that these accessor functions are only for the "PCI Express
549 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
550 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
551 */
552int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
553{
554 int ret;
555
556 *val = 0;
557 if (pos & 1)
558 return -EINVAL;
559
560 if (pcie_capability_reg_implemented(dev, pos)) {
561 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
562 /*
563 * Reset *val to 0 if pci_read_config_word() fails, it may
564 * have been written as 0xFFFF if hardware error happens
565 * during pci_read_config_word().
566 */
567 if (ret)
568 *val = 0;
569 return ret;
570 }
571
572 /*
573 * For Functions that do not implement the Slot Capabilities,
574 * Slot Status, and Slot Control registers, these spaces must
575 * be hardwired to 0b, with the exception of the Presence Detect
576 * State bit in the Slot Status register of Downstream Ports,
577 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
578 */
579 if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
580 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
581 *val = PCI_EXP_SLTSTA_PDS;
582 }
583
584 return 0;
585}
586EXPORT_SYMBOL(pcie_capability_read_word);
587
588int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
589{
590 int ret;
591
592 *val = 0;
593 if (pos & 3)
594 return -EINVAL;
595
596 if (pcie_capability_reg_implemented(dev, pos)) {
597 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
598 /*
599 * Reset *val to 0 if pci_read_config_dword() fails, it may
600 * have been written as 0xFFFFFFFF if hardware error happens
601 * during pci_read_config_dword().
602 */
603 if (ret)
604 *val = 0;
605 return ret;
606 }
607
608 if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
609 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
610 *val = PCI_EXP_SLTSTA_PDS;
611 }
612
613 return 0;
614}
615EXPORT_SYMBOL(pcie_capability_read_dword);
616
617int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
618{
619 if (pos & 1)
620 return -EINVAL;
621
622 if (!pcie_capability_reg_implemented(dev, pos))
623 return 0;
624
625 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
626}
627EXPORT_SYMBOL(pcie_capability_write_word);
628
629int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
630{
631 if (pos & 3)
632 return -EINVAL;
633
634 if (!pcie_capability_reg_implemented(dev, pos))
635 return 0;
636
637 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
638}
639EXPORT_SYMBOL(pcie_capability_write_dword);
640
641int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
642 u16 clear, u16 set)
643{
644 int ret;
645 u16 val;
646
647 ret = pcie_capability_read_word(dev, pos, &val);
648 if (!ret) {
649 val &= ~clear;
650 val |= set;
651 ret = pcie_capability_write_word(dev, pos, val);
652 }
653
654 return ret;
655}
656EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
657
658int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
659 u32 clear, u32 set)
660{
661 int ret;
662 u32 val;
663
664 ret = pcie_capability_read_dword(dev, pos, &val);
665 if (!ret) {
666 val &= ~clear;
667 val |= set;
668 ret = pcie_capability_write_dword(dev, pos, val);
669 }
670
671 return ret;
672}
673EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
diff --git a/drivers/pci/hotplug/Kconfig b/drivers/pci/hotplug/Kconfig
index 66f29bc00be4..b0e46dede1a9 100644
--- a/drivers/pci/hotplug/Kconfig
+++ b/drivers/pci/hotplug/Kconfig
@@ -17,28 +17,6 @@ menuconfig HOTPLUG_PCI
17 17
18if HOTPLUG_PCI 18if HOTPLUG_PCI
19 19
20config HOTPLUG_PCI_FAKE
21 tristate "Fake PCI Hotplug driver"
22 help
23 Say Y here if you want to use the fake PCI hotplug driver. It can
24 be used to simulate PCI hotplug events if even if your system is
25 not PCI hotplug capable.
26
27 This driver will "emulate" removing PCI devices from the system.
28 If the "power" file is written to with "0" then the specified PCI
29 device will be completely removed from the kernel.
30
31 WARNING, this does NOT turn off the power to the PCI device.
32 This is a "logical" removal, not a physical or electrical
33 removal.
34
35 Use this module at your own risk. You have been warned!
36
37 To compile this driver as a module, choose M here: the
38 module will be called fakephp.
39
40 When in doubt, say N.
41
42config HOTPLUG_PCI_COMPAQ 20config HOTPLUG_PCI_COMPAQ
43 tristate "Compaq PCI Hotplug driver" 21 tristate "Compaq PCI Hotplug driver"
44 depends on X86 && PCI_BIOS 22 depends on X86 && PCI_BIOS
@@ -143,7 +121,7 @@ config HOTPLUG_PCI_SHPC
143 121
144config HOTPLUG_PCI_RPA 122config HOTPLUG_PCI_RPA
145 tristate "RPA PCI Hotplug driver" 123 tristate "RPA PCI Hotplug driver"
146 depends on PPC_PSERIES && EEH && !HOTPLUG_PCI_FAKE 124 depends on PPC_PSERIES && EEH
147 help 125 help
148 Say Y here if you have a RPA system that supports PCI Hotplug. 126 Say Y here if you have a RPA system that supports PCI Hotplug.
149 127
diff --git a/drivers/pci/hotplug/Makefile b/drivers/pci/hotplug/Makefile
index 6cd9f3c9887d..c459cd4e39c2 100644
--- a/drivers/pci/hotplug/Makefile
+++ b/drivers/pci/hotplug/Makefile
@@ -23,9 +23,6 @@ obj-$(CONFIG_HOTPLUG_PCI_ACPI) += acpiphp.o
23 23
24obj-$(CONFIG_HOTPLUG_PCI_ACPI_IBM) += acpiphp_ibm.o 24obj-$(CONFIG_HOTPLUG_PCI_ACPI_IBM) += acpiphp_ibm.o
25 25
26# Link this last so it doesn't claim devices that have a real hotplug driver
27obj-$(CONFIG_HOTPLUG_PCI_FAKE) += fakephp.o
28
29pci_hotplug-objs := pci_hotplug_core.o pcihp_slot.o 26pci_hotplug-objs := pci_hotplug_core.o pcihp_slot.o
30 27
31ifdef CONFIG_HOTPLUG_PCI_CPCI 28ifdef CONFIG_HOTPLUG_PCI_CPCI
diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
index ad6fd6695495..7be4ca5e1f4c 100644
--- a/drivers/pci/hotplug/acpiphp_glue.c
+++ b/drivers/pci/hotplug/acpiphp_glue.c
@@ -869,17 +869,6 @@ static int __ref enable_device(struct acpiphp_slot *slot)
869 return retval; 869 return retval;
870} 870}
871 871
872static void disable_bridges(struct pci_bus *bus)
873{
874 struct pci_dev *dev;
875 list_for_each_entry(dev, &bus->devices, bus_list) {
876 if (dev->subordinate) {
877 disable_bridges(dev->subordinate);
878 pci_disable_device(dev);
879 }
880 }
881}
882
883/* return first device in slot, acquiring a reference on it */ 872/* return first device in slot, acquiring a reference on it */
884static struct pci_dev *dev_in_slot(struct acpiphp_slot *slot) 873static struct pci_dev *dev_in_slot(struct acpiphp_slot *slot)
885{ 874{
@@ -931,12 +920,7 @@ static int disable_device(struct acpiphp_slot *slot)
931 * here. 920 * here.
932 */ 921 */
933 while ((pdev = dev_in_slot(slot))) { 922 while ((pdev = dev_in_slot(slot))) {
934 pci_stop_bus_device(pdev); 923 pci_stop_and_remove_bus_device(pdev);
935 if (pdev->subordinate) {
936 disable_bridges(pdev->subordinate);
937 pci_disable_device(pdev);
938 }
939 __pci_remove_bus_device(pdev);
940 pci_dev_put(pdev); 924 pci_dev_put(pdev);
941 } 925 }
942 926
@@ -1477,34 +1461,6 @@ int __init acpiphp_get_num_slots(void)
1477} 1461}
1478 1462
1479 1463
1480#if 0
1481/**
1482 * acpiphp_for_each_slot - call function for each slot
1483 * @fn: callback function
1484 * @data: context to be passed to callback function
1485 */
1486static int acpiphp_for_each_slot(acpiphp_callback fn, void *data)
1487{
1488 struct list_head *node;
1489 struct acpiphp_bridge *bridge;
1490 struct acpiphp_slot *slot;
1491 int retval = 0;
1492
1493 list_for_each (node, &bridge_list) {
1494 bridge = (struct acpiphp_bridge *)node;
1495 for (slot = bridge->slots; slot; slot = slot->next) {
1496 retval = fn(slot, data);
1497 if (!retval)
1498 goto err_exit;
1499 }
1500 }
1501
1502 err_exit:
1503 return retval;
1504}
1505#endif
1506
1507
1508/** 1464/**
1509 * acpiphp_enable_slot - power on slot 1465 * acpiphp_enable_slot - power on slot
1510 * @slot: ACPI PHP slot 1466 * @slot: ACPI PHP slot
diff --git a/drivers/pci/hotplug/fakephp.c b/drivers/pci/hotplug/fakephp.c
deleted file mode 100644
index a019c9a712be..000000000000
--- a/drivers/pci/hotplug/fakephp.c
+++ /dev/null
@@ -1,164 +0,0 @@
1/* Works like the fakephp driver used to, except a little better.
2 *
3 * - It's possible to remove devices with subordinate busses.
4 * - New PCI devices that appear via any method, not just a fakephp triggered
5 * rescan, will be noticed.
6 * - Devices that are removed via any method, not just a fakephp triggered
7 * removal, will also be noticed.
8 *
9 * Uses nothing from the pci-hotplug subsystem.
10 *
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/list.h>
17#include <linux/kobject.h>
18#include <linux/sysfs.h>
19#include <linux/init.h>
20#include <linux/pci.h>
21#include <linux/device.h>
22#include <linux/slab.h>
23#include "../pci.h"
24
25struct legacy_slot {
26 struct kobject kobj;
27 struct pci_dev *dev;
28 struct list_head list;
29};
30
31static LIST_HEAD(legacy_list);
32
33static ssize_t legacy_show(struct kobject *kobj, struct attribute *attr,
34 char *buf)
35{
36 struct legacy_slot *slot = container_of(kobj, typeof(*slot), kobj);
37 strcpy(buf, "1\n");
38 return 2;
39}
40
41static void remove_callback(void *data)
42{
43 pci_stop_and_remove_bus_device((struct pci_dev *)data);
44}
45
46static ssize_t legacy_store(struct kobject *kobj, struct attribute *attr,
47 const char *buf, size_t len)
48{
49 struct legacy_slot *slot = container_of(kobj, typeof(*slot), kobj);
50 unsigned long val;
51
52 if (strict_strtoul(buf, 0, &val) < 0)
53 return -EINVAL;
54
55 if (val)
56 pci_rescan_bus(slot->dev->bus);
57 else
58 sysfs_schedule_callback(&slot->dev->dev.kobj, remove_callback,
59 slot->dev, THIS_MODULE);
60 return len;
61}
62
63static struct attribute *legacy_attrs[] = {
64 &(struct attribute){ .name = "power", .mode = 0644 },
65 NULL,
66};
67
68static void legacy_release(struct kobject *kobj)
69{
70 struct legacy_slot *slot = container_of(kobj, typeof(*slot), kobj);
71
72 pci_dev_put(slot->dev);
73 kfree(slot);
74}
75
76static struct kobj_type legacy_ktype = {
77 .sysfs_ops = &(const struct sysfs_ops){
78 .store = legacy_store, .show = legacy_show
79 },
80 .release = &legacy_release,
81 .default_attrs = legacy_attrs,
82};
83
84static int legacy_add_slot(struct pci_dev *pdev)
85{
86 struct legacy_slot *slot = kzalloc(sizeof(*slot), GFP_KERNEL);
87
88 if (!slot)
89 return -ENOMEM;
90
91 if (kobject_init_and_add(&slot->kobj, &legacy_ktype,
92 &pci_slots_kset->kobj, "%s",
93 dev_name(&pdev->dev))) {
94 dev_warn(&pdev->dev, "Failed to created legacy fake slot\n");
95 return -EINVAL;
96 }
97 slot->dev = pci_dev_get(pdev);
98
99 list_add(&slot->list, &legacy_list);
100
101 return 0;
102}
103
104static int legacy_notify(struct notifier_block *nb,
105 unsigned long action, void *data)
106{
107 struct pci_dev *pdev = to_pci_dev(data);
108
109 if (action == BUS_NOTIFY_ADD_DEVICE) {
110 legacy_add_slot(pdev);
111 } else if (action == BUS_NOTIFY_DEL_DEVICE) {
112 struct legacy_slot *slot;
113
114 list_for_each_entry(slot, &legacy_list, list)
115 if (slot->dev == pdev)
116 goto found;
117
118 dev_warn(&pdev->dev, "Missing legacy fake slot?");
119 return -ENODEV;
120found:
121 kobject_del(&slot->kobj);
122 list_del(&slot->list);
123 kobject_put(&slot->kobj);
124 }
125
126 return 0;
127}
128
129static struct notifier_block legacy_notifier = {
130 .notifier_call = legacy_notify
131};
132
133static int __init init_legacy(void)
134{
135 struct pci_dev *pdev = NULL;
136
137 /* Add existing devices */
138 for_each_pci_dev(pdev)
139 legacy_add_slot(pdev);
140
141 /* Be alerted of any new ones */
142 bus_register_notifier(&pci_bus_type, &legacy_notifier);
143 return 0;
144}
145module_init(init_legacy);
146
147static void __exit remove_legacy(void)
148{
149 struct legacy_slot *slot, *tmp;
150
151 bus_unregister_notifier(&pci_bus_type, &legacy_notifier);
152
153 list_for_each_entry_safe(slot, tmp, &legacy_list, list) {
154 list_del(&slot->list);
155 kobject_del(&slot->kobj);
156 kobject_put(&slot->kobj);
157 }
158}
159module_exit(remove_legacy);
160
161
162MODULE_AUTHOR("Trent Piepho <xyzzy@speakeasy.org>");
163MODULE_DESCRIPTION("Legacy version of the fakephp interface");
164MODULE_LICENSE("GPL");
diff --git a/drivers/pci/hotplug/pciehp_acpi.c b/drivers/pci/hotplug/pciehp_acpi.c
index 376d70d17176..24d709b7388c 100644
--- a/drivers/pci/hotplug/pciehp_acpi.c
+++ b/drivers/pci/hotplug/pciehp_acpi.c
@@ -81,16 +81,12 @@ static struct list_head __initdata dummy_slots = LIST_HEAD_INIT(dummy_slots);
81/* Dummy driver for dumplicate name detection */ 81/* Dummy driver for dumplicate name detection */
82static int __init dummy_probe(struct pcie_device *dev) 82static int __init dummy_probe(struct pcie_device *dev)
83{ 83{
84 int pos;
85 u32 slot_cap; 84 u32 slot_cap;
86 acpi_handle handle; 85 acpi_handle handle;
87 struct dummy_slot *slot, *tmp; 86 struct dummy_slot *slot, *tmp;
88 struct pci_dev *pdev = dev->port; 87 struct pci_dev *pdev = dev->port;
89 88
90 pos = pci_pcie_cap(pdev); 89 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
91 if (!pos)
92 return -ENODEV;
93 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &slot_cap);
94 slot = kzalloc(sizeof(*slot), GFP_KERNEL); 90 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
95 if (!slot) 91 if (!slot)
96 return -ENOMEM; 92 return -ENOMEM;
diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c
index 365c6b96c642..916bf4f53aba 100644
--- a/drivers/pci/hotplug/pciehp_core.c
+++ b/drivers/pci/hotplug/pciehp_core.c
@@ -300,24 +300,24 @@ static int pciehp_suspend (struct pcie_device *dev)
300 300
301static int pciehp_resume (struct pcie_device *dev) 301static int pciehp_resume (struct pcie_device *dev)
302{ 302{
303 struct controller *ctrl;
304 struct slot *slot;
305 u8 status;
306
303 dev_info(&dev->device, "%s ENTRY\n", __func__); 307 dev_info(&dev->device, "%s ENTRY\n", __func__);
304 if (pciehp_force) { 308 ctrl = get_service_data(dev);
305 struct controller *ctrl = get_service_data(dev);
306 struct slot *slot;
307 u8 status;
308 309
309 /* reinitialize the chipset's event detection logic */ 310 /* reinitialize the chipset's event detection logic */
310 pcie_enable_notification(ctrl); 311 pcie_enable_notification(ctrl);
311 312
312 slot = ctrl->slot; 313 slot = ctrl->slot;
313 314
314 /* Check if slot is occupied */ 315 /* Check if slot is occupied */
315 pciehp_get_adapter_status(slot, &status); 316 pciehp_get_adapter_status(slot, &status);
316 if (status) 317 if (status)
317 pciehp_enable_slot(slot); 318 pciehp_enable_slot(slot);
318 else 319 else
319 pciehp_disable_slot(slot); 320 pciehp_disable_slot(slot);
320 }
321 return 0; 321 return 0;
322} 322}
323#endif /* PM */ 323#endif /* PM */
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 302451e8289d..13b2eaf7ba43 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -44,25 +44,25 @@
44static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) 44static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
45{ 45{
46 struct pci_dev *dev = ctrl->pcie->port; 46 struct pci_dev *dev = ctrl->pcie->port;
47 return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value); 47 return pcie_capability_read_word(dev, reg, value);
48} 48}
49 49
50static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) 50static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
51{ 51{
52 struct pci_dev *dev = ctrl->pcie->port; 52 struct pci_dev *dev = ctrl->pcie->port;
53 return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value); 53 return pcie_capability_read_dword(dev, reg, value);
54} 54}
55 55
56static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) 56static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
57{ 57{
58 struct pci_dev *dev = ctrl->pcie->port; 58 struct pci_dev *dev = ctrl->pcie->port;
59 return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value); 59 return pcie_capability_write_word(dev, reg, value);
60} 60}
61 61
62static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) 62static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
63{ 63{
64 struct pci_dev *dev = ctrl->pcie->port; 64 struct pci_dev *dev = ctrl->pcie->port;
65 return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value); 65 return pcie_capability_write_dword(dev, reg, value);
66} 66}
67 67
68/* Power Control Command */ 68/* Power Control Command */
@@ -855,10 +855,6 @@ struct controller *pcie_init(struct pcie_device *dev)
855 goto abort; 855 goto abort;
856 } 856 }
857 ctrl->pcie = dev; 857 ctrl->pcie = dev;
858 if (!pci_pcie_cap(pdev)) {
859 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
860 goto abort_ctrl;
861 }
862 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { 858 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
863 ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); 859 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
864 goto abort_ctrl; 860 goto abort_ctrl;
diff --git a/drivers/pci/hotplug/pcihp_slot.c b/drivers/pci/hotplug/pcihp_slot.c
index 8c05a18c9770..fec2d5b75440 100644
--- a/drivers/pci/hotplug/pcihp_slot.c
+++ b/drivers/pci/hotplug/pcihp_slot.c
@@ -96,17 +96,11 @@ static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
96static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp) 96static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
97{ 97{
98 int pos; 98 int pos;
99 u16 reg16;
100 u32 reg32; 99 u32 reg32;
101 100
102 if (!hpp) 101 if (!hpp)
103 return; 102 return;
104 103
105 /* Find PCI Express capability */
106 pos = pci_pcie_cap(dev);
107 if (!pos)
108 return;
109
110 if (hpp->revision > 1) { 104 if (hpp->revision > 1) {
111 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n", 105 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
112 hpp->revision); 106 hpp->revision);
@@ -114,17 +108,13 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
114 } 108 }
115 109
116 /* Initialize Device Control Register */ 110 /* Initialize Device Control Register */
117 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &reg16); 111 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
118 reg16 = (reg16 & hpp->pci_exp_devctl_and) | hpp->pci_exp_devctl_or; 112 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
119 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);
120 113
121 /* Initialize Link Control Register */ 114 /* Initialize Link Control Register */
122 if (dev->subordinate) { 115 if (dev->subordinate)
123 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &reg16); 116 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
124 reg16 = (reg16 & hpp->pci_exp_lnkctl_and) 117 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
125 | hpp->pci_exp_lnkctl_or;
126 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, reg16);
127 }
128 118
129 /* Find Advanced Error Reporting Enhanced Capability */ 119 /* Find Advanced Error Reporting Enhanced Capability */
130 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 120 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index 74bbaf82638d..aeccc911abb8 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -433,8 +433,8 @@ static int sriov_init(struct pci_dev *dev, int pos)
433 struct resource *res; 433 struct resource *res;
434 struct pci_dev *pdev; 434 struct pci_dev *pdev;
435 435
436 if (dev->pcie_type != PCI_EXP_TYPE_RC_END && 436 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END &&
437 dev->pcie_type != PCI_EXP_TYPE_ENDPOINT) 437 pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT)
438 return -ENODEV; 438 return -ENODEV;
439 439
440 pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &ctrl); 440 pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &ctrl);
@@ -503,7 +503,7 @@ found:
503 iov->self = dev; 503 iov->self = dev;
504 pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap); 504 pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap);
505 pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link); 505 pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
506 if (dev->pcie_type == PCI_EXP_TYPE_RC_END) 506 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END)
507 iov->link = PCI_DEVFN(PCI_SLOT(dev->devfn), iov->link); 507 iov->link = PCI_DEVFN(PCI_SLOT(dev->devfn), iov->link);
508 508
509 if (pdev) 509 if (pdev)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index f3ea977a5b1b..5ba60dd71faa 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -254,52 +254,17 @@ int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
254} 254}
255 255
256/** 256/**
257 * pci_pcie_cap2 - query for devices' PCI_CAP_ID_EXP v2 capability structure 257 * pci_find_next_ext_capability - Find an extended capability
258 * @dev: PCI device to check
259 *
260 * Like pci_pcie_cap() but also checks that the PCIe capability version is
261 * >= 2. Note that v1 capability structures could be sparse in that not
262 * all register fields were required. v2 requires the entire structure to
263 * be present size wise, while still allowing for non-implemented registers
264 * to exist but they must be hardwired to 0.
265 *
266 * Due to the differences in the versions of capability structures, one
267 * must be careful not to try and access non-existant registers that may
268 * exist in early versions - v1 - of Express devices.
269 *
270 * Returns the offset of the PCIe capability structure as long as the
271 * capability version is >= 2; otherwise 0 is returned.
272 */
273static int pci_pcie_cap2(struct pci_dev *dev)
274{
275 u16 flags;
276 int pos;
277
278 pos = pci_pcie_cap(dev);
279 if (pos) {
280 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
281 if ((flags & PCI_EXP_FLAGS_VERS) < 2)
282 pos = 0;
283 }
284
285 return pos;
286}
287
288/**
289 * pci_find_ext_capability - Find an extended capability
290 * @dev: PCI device to query 258 * @dev: PCI device to query
259 * @start: address at which to start looking (0 to start at beginning of list)
291 * @cap: capability code 260 * @cap: capability code
292 * 261 *
293 * Returns the address of the requested extended capability structure 262 * Returns the address of the next matching extended capability structure
294 * within the device's PCI configuration space or 0 if the device does 263 * within the device's PCI configuration space or 0 if the device does
295 * not support it. Possible values for @cap: 264 * not support it. Some capabilities can occur several times, e.g., the
296 * 265 * vendor-specific capability, and this provides a way to find them all.
297 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
298 * %PCI_EXT_CAP_ID_VC Virtual Channel
299 * %PCI_EXT_CAP_ID_DSN Device Serial Number
300 * %PCI_EXT_CAP_ID_PWR Power Budgeting
301 */ 266 */
302int pci_find_ext_capability(struct pci_dev *dev, int cap) 267int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
303{ 268{
304 u32 header; 269 u32 header;
305 int ttl; 270 int ttl;
@@ -311,6 +276,9 @@ int pci_find_ext_capability(struct pci_dev *dev, int cap)
311 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) 276 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
312 return 0; 277 return 0;
313 278
279 if (start)
280 pos = start;
281
314 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 282 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
315 return 0; 283 return 0;
316 284
@@ -322,7 +290,7 @@ int pci_find_ext_capability(struct pci_dev *dev, int cap)
322 return 0; 290 return 0;
323 291
324 while (ttl-- > 0) { 292 while (ttl-- > 0) {
325 if (PCI_EXT_CAP_ID(header) == cap) 293 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
326 return pos; 294 return pos;
327 295
328 pos = PCI_EXT_CAP_NEXT(header); 296 pos = PCI_EXT_CAP_NEXT(header);
@@ -335,6 +303,26 @@ int pci_find_ext_capability(struct pci_dev *dev, int cap)
335 303
336 return 0; 304 return 0;
337} 305}
306EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
307
308/**
309 * pci_find_ext_capability - Find an extended capability
310 * @dev: PCI device to query
311 * @cap: capability code
312 *
313 * Returns the address of the requested extended capability structure
314 * within the device's PCI configuration space or 0 if the device does
315 * not support it. Possible values for @cap:
316 *
317 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
318 * %PCI_EXT_CAP_ID_VC Virtual Channel
319 * %PCI_EXT_CAP_ID_DSN Device Serial Number
320 * %PCI_EXT_CAP_ID_PWR Power Budgeting
321 */
322int pci_find_ext_capability(struct pci_dev *dev, int cap)
323{
324 return pci_find_next_ext_capability(dev, 0, cap);
325}
338EXPORT_SYMBOL_GPL(pci_find_ext_capability); 326EXPORT_SYMBOL_GPL(pci_find_ext_capability);
339 327
340static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) 328static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
@@ -854,21 +842,6 @@ EXPORT_SYMBOL(pci_choose_state);
854 842
855#define PCI_EXP_SAVE_REGS 7 843#define PCI_EXP_SAVE_REGS 7
856 844
857#define pcie_cap_has_devctl(type, flags) 1
858#define pcie_cap_has_lnkctl(type, flags) \
859 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
860 (type == PCI_EXP_TYPE_ROOT_PORT || \
861 type == PCI_EXP_TYPE_ENDPOINT || \
862 type == PCI_EXP_TYPE_LEG_END))
863#define pcie_cap_has_sltctl(type, flags) \
864 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
865 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
866 (type == PCI_EXP_TYPE_DOWNSTREAM && \
867 (flags & PCI_EXP_FLAGS_SLOT))))
868#define pcie_cap_has_rtctl(type, flags) \
869 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
870 (type == PCI_EXP_TYPE_ROOT_PORT || \
871 type == PCI_EXP_TYPE_RC_EC))
872 845
873static struct pci_cap_saved_state *pci_find_saved_cap( 846static struct pci_cap_saved_state *pci_find_saved_cap(
874 struct pci_dev *pci_dev, char cap) 847 struct pci_dev *pci_dev, char cap)
@@ -885,13 +858,11 @@ static struct pci_cap_saved_state *pci_find_saved_cap(
885 858
886static int pci_save_pcie_state(struct pci_dev *dev) 859static int pci_save_pcie_state(struct pci_dev *dev)
887{ 860{
888 int pos, i = 0; 861 int i = 0;
889 struct pci_cap_saved_state *save_state; 862 struct pci_cap_saved_state *save_state;
890 u16 *cap; 863 u16 *cap;
891 u16 flags;
892 864
893 pos = pci_pcie_cap(dev); 865 if (!pci_is_pcie(dev))
894 if (!pos)
895 return 0; 866 return 0;
896 867
897 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 868 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
@@ -899,60 +870,37 @@ static int pci_save_pcie_state(struct pci_dev *dev)
899 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 870 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
900 return -ENOMEM; 871 return -ENOMEM;
901 } 872 }
902 cap = (u16 *)&save_state->cap.data[0];
903
904 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
905 873
906 if (pcie_cap_has_devctl(dev->pcie_type, flags)) 874 cap = (u16 *)&save_state->cap.data[0];
907 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); 875 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
908 if (pcie_cap_has_lnkctl(dev->pcie_type, flags)) 876 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
909 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); 877 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
910 if (pcie_cap_has_sltctl(dev->pcie_type, flags)) 878 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
911 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); 879 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
912 if (pcie_cap_has_rtctl(dev->pcie_type, flags)) 880 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
913 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); 881 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
914
915 pos = pci_pcie_cap2(dev);
916 if (!pos)
917 return 0;
918 882
919 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
920 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
921 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
922 return 0; 883 return 0;
923} 884}
924 885
925static void pci_restore_pcie_state(struct pci_dev *dev) 886static void pci_restore_pcie_state(struct pci_dev *dev)
926{ 887{
927 int i = 0, pos; 888 int i = 0;
928 struct pci_cap_saved_state *save_state; 889 struct pci_cap_saved_state *save_state;
929 u16 *cap; 890 u16 *cap;
930 u16 flags;
931 891
932 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 892 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
933 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 893 if (!save_state)
934 if (!save_state || pos <= 0)
935 return;
936 cap = (u16 *)&save_state->cap.data[0];
937
938 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
939
940 if (pcie_cap_has_devctl(dev->pcie_type, flags))
941 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
942 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
943 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
944 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
945 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
946 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
947 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
948
949 pos = pci_pcie_cap2(dev);
950 if (!pos)
951 return; 894 return;
952 895
953 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]); 896 cap = (u16 *)&save_state->cap.data[0];
954 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]); 897 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
955 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]); 898 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
899 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
900 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
901 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
902 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
903 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
956} 904}
957 905
958 906
@@ -2066,35 +2014,24 @@ void pci_free_cap_save_buffers(struct pci_dev *dev)
2066 */ 2014 */
2067void pci_enable_ari(struct pci_dev *dev) 2015void pci_enable_ari(struct pci_dev *dev)
2068{ 2016{
2069 int pos;
2070 u32 cap; 2017 u32 cap;
2071 u16 ctrl;
2072 struct pci_dev *bridge; 2018 struct pci_dev *bridge;
2073 2019
2074 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) 2020 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2075 return; 2021 return;
2076 2022
2077 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2023 if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI))
2078 if (!pos)
2079 return; 2024 return;
2080 2025
2081 bridge = dev->bus->self; 2026 bridge = dev->bus->self;
2082 if (!bridge) 2027 if (!bridge)
2083 return; 2028 return;
2084 2029
2085 /* ARI is a PCIe cap v2 feature */ 2030 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2086 pos = pci_pcie_cap2(bridge);
2087 if (!pos)
2088 return;
2089
2090 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
2091 if (!(cap & PCI_EXP_DEVCAP2_ARI)) 2031 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2092 return; 2032 return;
2093 2033
2094 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl); 2034 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_ARI);
2095 ctrl |= PCI_EXP_DEVCTL2_ARI;
2096 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
2097
2098 bridge->ari_enabled = 1; 2035 bridge->ari_enabled = 1;
2099} 2036}
2100 2037
@@ -2109,20 +2046,14 @@ void pci_enable_ari(struct pci_dev *dev)
2109 */ 2046 */
2110void pci_enable_ido(struct pci_dev *dev, unsigned long type) 2047void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2111{ 2048{
2112 int pos; 2049 u16 ctrl = 0;
2113 u16 ctrl;
2114 2050
2115 /* ID-based Ordering is a PCIe cap v2 feature */
2116 pos = pci_pcie_cap2(dev);
2117 if (!pos)
2118 return;
2119
2120 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2121 if (type & PCI_EXP_IDO_REQUEST) 2051 if (type & PCI_EXP_IDO_REQUEST)
2122 ctrl |= PCI_EXP_IDO_REQ_EN; 2052 ctrl |= PCI_EXP_IDO_REQ_EN;
2123 if (type & PCI_EXP_IDO_COMPLETION) 2053 if (type & PCI_EXP_IDO_COMPLETION)
2124 ctrl |= PCI_EXP_IDO_CMP_EN; 2054 ctrl |= PCI_EXP_IDO_CMP_EN;
2125 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2055 if (ctrl)
2056 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
2126} 2057}
2127EXPORT_SYMBOL(pci_enable_ido); 2058EXPORT_SYMBOL(pci_enable_ido);
2128 2059
@@ -2133,20 +2064,14 @@ EXPORT_SYMBOL(pci_enable_ido);
2133 */ 2064 */
2134void pci_disable_ido(struct pci_dev *dev, unsigned long type) 2065void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2135{ 2066{
2136 int pos; 2067 u16 ctrl = 0;
2137 u16 ctrl;
2138 2068
2139 /* ID-based Ordering is a PCIe cap v2 feature */
2140 pos = pci_pcie_cap2(dev);
2141 if (!pos)
2142 return;
2143
2144 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2145 if (type & PCI_EXP_IDO_REQUEST) 2069 if (type & PCI_EXP_IDO_REQUEST)
2146 ctrl &= ~PCI_EXP_IDO_REQ_EN; 2070 ctrl |= PCI_EXP_IDO_REQ_EN;
2147 if (type & PCI_EXP_IDO_COMPLETION) 2071 if (type & PCI_EXP_IDO_COMPLETION)
2148 ctrl &= ~PCI_EXP_IDO_CMP_EN; 2072 ctrl |= PCI_EXP_IDO_CMP_EN;
2149 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2073 if (ctrl)
2074 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
2150} 2075}
2151EXPORT_SYMBOL(pci_disable_ido); 2076EXPORT_SYMBOL(pci_disable_ido);
2152 2077
@@ -2171,17 +2096,11 @@ EXPORT_SYMBOL(pci_disable_ido);
2171 */ 2096 */
2172int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type) 2097int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2173{ 2098{
2174 int pos;
2175 u32 cap; 2099 u32 cap;
2176 u16 ctrl; 2100 u16 ctrl;
2177 int ret; 2101 int ret;
2178 2102
2179 /* OBFF is a PCIe cap v2 feature */ 2103 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2180 pos = pci_pcie_cap2(dev);
2181 if (!pos)
2182 return -ENOTSUPP;
2183
2184 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2185 if (!(cap & PCI_EXP_OBFF_MASK)) 2104 if (!(cap & PCI_EXP_OBFF_MASK))
2186 return -ENOTSUPP; /* no OBFF support at all */ 2105 return -ENOTSUPP; /* no OBFF support at all */
2187 2106
@@ -2192,7 +2111,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2192 return ret; 2111 return ret;
2193 } 2112 }
2194 2113
2195 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 2114 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
2196 if (cap & PCI_EXP_OBFF_WAKE) 2115 if (cap & PCI_EXP_OBFF_WAKE)
2197 ctrl |= PCI_EXP_OBFF_WAKE_EN; 2116 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2198 else { 2117 else {
@@ -2210,7 +2129,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2210 return -ENOTSUPP; 2129 return -ENOTSUPP;
2211 } 2130 }
2212 } 2131 }
2213 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2132 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);
2214 2133
2215 return 0; 2134 return 0;
2216} 2135}
@@ -2224,17 +2143,7 @@ EXPORT_SYMBOL(pci_enable_obff);
2224 */ 2143 */
2225void pci_disable_obff(struct pci_dev *dev) 2144void pci_disable_obff(struct pci_dev *dev)
2226{ 2145{
2227 int pos; 2146 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_OBFF_WAKE_EN);
2228 u16 ctrl;
2229
2230 /* OBFF is a PCIe cap v2 feature */
2231 pos = pci_pcie_cap2(dev);
2232 if (!pos)
2233 return;
2234
2235 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2236 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2237 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2238} 2147}
2239EXPORT_SYMBOL(pci_disable_obff); 2148EXPORT_SYMBOL(pci_disable_obff);
2240 2149
@@ -2247,15 +2156,9 @@ EXPORT_SYMBOL(pci_disable_obff);
2247 */ 2156 */
2248static bool pci_ltr_supported(struct pci_dev *dev) 2157static bool pci_ltr_supported(struct pci_dev *dev)
2249{ 2158{
2250 int pos;
2251 u32 cap; 2159 u32 cap;
2252 2160
2253 /* LTR is a PCIe cap v2 feature */ 2161 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2254 pos = pci_pcie_cap2(dev);
2255 if (!pos)
2256 return false;
2257
2258 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2259 2162
2260 return cap & PCI_EXP_DEVCAP2_LTR; 2163 return cap & PCI_EXP_DEVCAP2_LTR;
2261} 2164}
@@ -2272,22 +2175,15 @@ static bool pci_ltr_supported(struct pci_dev *dev)
2272 */ 2175 */
2273int pci_enable_ltr(struct pci_dev *dev) 2176int pci_enable_ltr(struct pci_dev *dev)
2274{ 2177{
2275 int pos;
2276 u16 ctrl;
2277 int ret; 2178 int ret;
2278 2179
2279 if (!pci_ltr_supported(dev))
2280 return -ENOTSUPP;
2281
2282 /* LTR is a PCIe cap v2 feature */
2283 pos = pci_pcie_cap2(dev);
2284 if (!pos)
2285 return -ENOTSUPP;
2286
2287 /* Only primary function can enable/disable LTR */ 2180 /* Only primary function can enable/disable LTR */
2288 if (PCI_FUNC(dev->devfn) != 0) 2181 if (PCI_FUNC(dev->devfn) != 0)
2289 return -EINVAL; 2182 return -EINVAL;
2290 2183
2184 if (!pci_ltr_supported(dev))
2185 return -ENOTSUPP;
2186
2291 /* Enable upstream ports first */ 2187 /* Enable upstream ports first */
2292 if (dev->bus->self) { 2188 if (dev->bus->self) {
2293 ret = pci_enable_ltr(dev->bus->self); 2189 ret = pci_enable_ltr(dev->bus->self);
@@ -2295,11 +2191,7 @@ int pci_enable_ltr(struct pci_dev *dev)
2295 return ret; 2191 return ret;
2296 } 2192 }
2297 2193
2298 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 2194 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
2299 ctrl |= PCI_EXP_LTR_EN;
2300 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2301
2302 return 0;
2303} 2195}
2304EXPORT_SYMBOL(pci_enable_ltr); 2196EXPORT_SYMBOL(pci_enable_ltr);
2305 2197
@@ -2309,24 +2201,14 @@ EXPORT_SYMBOL(pci_enable_ltr);
2309 */ 2201 */
2310void pci_disable_ltr(struct pci_dev *dev) 2202void pci_disable_ltr(struct pci_dev *dev)
2311{ 2203{
2312 int pos;
2313 u16 ctrl;
2314
2315 if (!pci_ltr_supported(dev))
2316 return;
2317
2318 /* LTR is a PCIe cap v2 feature */
2319 pos = pci_pcie_cap2(dev);
2320 if (!pos)
2321 return;
2322
2323 /* Only primary function can enable/disable LTR */ 2204 /* Only primary function can enable/disable LTR */
2324 if (PCI_FUNC(dev->devfn) != 0) 2205 if (PCI_FUNC(dev->devfn) != 0)
2325 return; 2206 return;
2326 2207
2327 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); 2208 if (!pci_ltr_supported(dev))
2328 ctrl &= ~PCI_EXP_LTR_EN; 2209 return;
2329 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); 2210
2211 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
2330} 2212}
2331EXPORT_SYMBOL(pci_disable_ltr); 2213EXPORT_SYMBOL(pci_disable_ltr);
2332 2214
@@ -2409,9 +2291,6 @@ void pci_enable_acs(struct pci_dev *dev)
2409 if (!pci_acs_enable) 2291 if (!pci_acs_enable)
2410 return; 2292 return;
2411 2293
2412 if (!pci_is_pcie(dev))
2413 return;
2414
2415 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 2294 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2416 if (!pos) 2295 if (!pos)
2417 return; 2296 return;
@@ -2459,8 +2338,8 @@ bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2459 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | 2338 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR |
2460 PCI_ACS_EC | PCI_ACS_DT); 2339 PCI_ACS_EC | PCI_ACS_DT);
2461 2340
2462 if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM || 2341 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM ||
2463 pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2342 pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
2464 pdev->multifunction) { 2343 pdev->multifunction) {
2465 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); 2344 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2466 if (!pos) 2345 if (!pos)
@@ -3176,15 +3055,10 @@ EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3176static int pcie_flr(struct pci_dev *dev, int probe) 3055static int pcie_flr(struct pci_dev *dev, int probe)
3177{ 3056{
3178 int i; 3057 int i;
3179 int pos;
3180 u32 cap; 3058 u32 cap;
3181 u16 status, control; 3059 u16 status;
3182
3183 pos = pci_pcie_cap(dev);
3184 if (!pos)
3185 return -ENOTTY;
3186 3060
3187 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap); 3061 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3188 if (!(cap & PCI_EXP_DEVCAP_FLR)) 3062 if (!(cap & PCI_EXP_DEVCAP_FLR))
3189 return -ENOTTY; 3063 return -ENOTTY;
3190 3064
@@ -3196,7 +3070,7 @@ static int pcie_flr(struct pci_dev *dev, int probe)
3196 if (i) 3070 if (i)
3197 msleep((1 << (i - 1)) * 100); 3071 msleep((1 << (i - 1)) * 100);
3198 3072
3199 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 3073 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
3200 if (!(status & PCI_EXP_DEVSTA_TRPND)) 3074 if (!(status & PCI_EXP_DEVSTA_TRPND))
3201 goto clear; 3075 goto clear;
3202 } 3076 }
@@ -3205,9 +3079,7 @@ static int pcie_flr(struct pci_dev *dev, int probe)
3205 "proceeding with reset anyway\n"); 3079 "proceeding with reset anyway\n");
3206 3080
3207clear: 3081clear:
3208 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control); 3082 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3209 control |= PCI_EXP_DEVCTL_BCR_FLR;
3210 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
3211 3083
3212 msleep(100); 3084 msleep(100);
3213 3085
@@ -3575,18 +3447,11 @@ EXPORT_SYMBOL(pcix_set_mmrbc);
3575 */ 3447 */
3576int pcie_get_readrq(struct pci_dev *dev) 3448int pcie_get_readrq(struct pci_dev *dev)
3577{ 3449{
3578 int ret, cap;
3579 u16 ctl; 3450 u16 ctl;
3580 3451
3581 cap = pci_pcie_cap(dev); 3452 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3582 if (!cap)
3583 return -EINVAL;
3584
3585 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3586 if (!ret)
3587 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3588 3453
3589 return ret; 3454 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3590} 3455}
3591EXPORT_SYMBOL(pcie_get_readrq); 3456EXPORT_SYMBOL(pcie_get_readrq);
3592 3457
@@ -3600,19 +3465,11 @@ EXPORT_SYMBOL(pcie_get_readrq);
3600 */ 3465 */
3601int pcie_set_readrq(struct pci_dev *dev, int rq) 3466int pcie_set_readrq(struct pci_dev *dev, int rq)
3602{ 3467{
3603 int cap, err = -EINVAL; 3468 u16 v;
3604 u16 ctl, v;
3605 3469
3606 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 3470 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3607 goto out; 3471 return -EINVAL;
3608
3609 cap = pci_pcie_cap(dev);
3610 if (!cap)
3611 goto out;
3612 3472
3613 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3614 if (err)
3615 goto out;
3616 /* 3473 /*
3617 * If using the "performance" PCIe config, we clamp the 3474 * If using the "performance" PCIe config, we clamp the
3618 * read rq size to the max packet size to prevent the 3475 * read rq size to the max packet size to prevent the
@@ -3630,14 +3487,8 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
3630 3487
3631 v = (ffs(rq) - 8) << 12; 3488 v = (ffs(rq) - 8) << 12;
3632 3489
3633 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { 3490 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3634 ctl &= ~PCI_EXP_DEVCTL_READRQ; 3491 PCI_EXP_DEVCTL_READRQ, v);
3635 ctl |= v;
3636 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3637 }
3638
3639out:
3640 return err;
3641} 3492}
3642EXPORT_SYMBOL(pcie_set_readrq); 3493EXPORT_SYMBOL(pcie_set_readrq);
3643 3494
@@ -3650,18 +3501,11 @@ EXPORT_SYMBOL(pcie_set_readrq);
3650 */ 3501 */
3651int pcie_get_mps(struct pci_dev *dev) 3502int pcie_get_mps(struct pci_dev *dev)
3652{ 3503{
3653 int ret, cap;
3654 u16 ctl; 3504 u16 ctl;
3655 3505
3656 cap = pci_pcie_cap(dev); 3506 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3657 if (!cap)
3658 return -EINVAL;
3659
3660 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3661 if (!ret)
3662 ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3663 3507
3664 return ret; 3508 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3665} 3509}
3666 3510
3667/** 3511/**
@@ -3674,32 +3518,18 @@ int pcie_get_mps(struct pci_dev *dev)
3674 */ 3518 */
3675int pcie_set_mps(struct pci_dev *dev, int mps) 3519int pcie_set_mps(struct pci_dev *dev, int mps)
3676{ 3520{
3677 int cap, err = -EINVAL; 3521 u16 v;
3678 u16 ctl, v;
3679 3522
3680 if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) 3523 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3681 goto out; 3524 return -EINVAL;
3682 3525
3683 v = ffs(mps) - 8; 3526 v = ffs(mps) - 8;
3684 if (v > dev->pcie_mpss) 3527 if (v > dev->pcie_mpss)
3685 goto out; 3528 return -EINVAL;
3686 v <<= 5; 3529 v <<= 5;
3687 3530
3688 cap = pci_pcie_cap(dev); 3531 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3689 if (!cap) 3532 PCI_EXP_DEVCTL_PAYLOAD, v);
3690 goto out;
3691
3692 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3693 if (err)
3694 goto out;
3695
3696 if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) {
3697 ctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
3698 ctl |= v;
3699 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3700 }
3701out:
3702 return err;
3703} 3533}
3704 3534
3705/** 3535/**
diff --git a/drivers/pci/pcie/aer/aer_inject.c b/drivers/pci/pcie/aer/aer_inject.c
index 52229863e9fe..4e24cb8a94ae 100644
--- a/drivers/pci/pcie/aer/aer_inject.c
+++ b/drivers/pci/pcie/aer/aer_inject.c
@@ -288,7 +288,7 @@ static struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
288 while (1) { 288 while (1) {
289 if (!pci_is_pcie(dev)) 289 if (!pci_is_pcie(dev))
290 break; 290 break;
291 if (dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) 291 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
292 return dev; 292 return dev;
293 if (!dev->bus->self) 293 if (!dev->bus->self)
294 break; 294 break;
diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c
index 7131644e3ae6..030cf12d5468 100644
--- a/drivers/pci/pcie/aer/aerdrv.c
+++ b/drivers/pci/pcie/aer/aerdrv.c
@@ -81,10 +81,11 @@ bool pci_aer_available(void)
81static int set_device_error_reporting(struct pci_dev *dev, void *data) 81static int set_device_error_reporting(struct pci_dev *dev, void *data)
82{ 82{
83 bool enable = *((bool *)data); 83 bool enable = *((bool *)data);
84 int type = pci_pcie_type(dev);
84 85
85 if ((dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) || 86 if ((type == PCI_EXP_TYPE_ROOT_PORT) ||
86 (dev->pcie_type == PCI_EXP_TYPE_UPSTREAM) || 87 (type == PCI_EXP_TYPE_UPSTREAM) ||
87 (dev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)) { 88 (type == PCI_EXP_TYPE_DOWNSTREAM)) {
88 if (enable) 89 if (enable)
89 pci_enable_pcie_error_reporting(dev); 90 pci_enable_pcie_error_reporting(dev);
90 else 91 else
@@ -121,19 +122,17 @@ static void set_downstream_devices_error_reporting(struct pci_dev *dev,
121static void aer_enable_rootport(struct aer_rpc *rpc) 122static void aer_enable_rootport(struct aer_rpc *rpc)
122{ 123{
123 struct pci_dev *pdev = rpc->rpd->port; 124 struct pci_dev *pdev = rpc->rpd->port;
124 int pos, aer_pos; 125 int aer_pos;
125 u16 reg16; 126 u16 reg16;
126 u32 reg32; 127 u32 reg32;
127 128
128 pos = pci_pcie_cap(pdev);
129 /* Clear PCIe Capability's Device Status */ 129 /* Clear PCIe Capability's Device Status */
130 pci_read_config_word(pdev, pos+PCI_EXP_DEVSTA, &reg16); 130 pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, &reg16);
131 pci_write_config_word(pdev, pos+PCI_EXP_DEVSTA, reg16); 131 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16);
132 132
133 /* Disable system error generation in response to error messages */ 133 /* Disable system error generation in response to error messages */
134 pci_read_config_word(pdev, pos + PCI_EXP_RTCTL, &reg16); 134 pcie_capability_clear_word(pdev, PCI_EXP_RTCTL,
135 reg16 &= ~(SYSTEM_ERROR_INTR_ON_MESG_MASK); 135 SYSTEM_ERROR_INTR_ON_MESG_MASK);
136 pci_write_config_word(pdev, pos + PCI_EXP_RTCTL, reg16);
137 136
138 aer_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 137 aer_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
139 /* Clear error status */ 138 /* Clear error status */
@@ -395,9 +394,8 @@ static void aer_error_resume(struct pci_dev *dev)
395 u16 reg16; 394 u16 reg16;
396 395
397 /* Clean up Root device status */ 396 /* Clean up Root device status */
398 pos = pci_pcie_cap(dev); 397 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &reg16);
399 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &reg16); 398 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, reg16);
400 pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, reg16);
401 399
402 /* Clean AER Root Error Status */ 400 /* Clean AER Root Error Status */
403 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 401 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
diff --git a/drivers/pci/pcie/aer/aerdrv_acpi.c b/drivers/pci/pcie/aer/aerdrv_acpi.c
index 124f20ff11b2..5194a7d41730 100644
--- a/drivers/pci/pcie/aer/aerdrv_acpi.c
+++ b/drivers/pci/pcie/aer/aerdrv_acpi.c
@@ -60,7 +60,7 @@ static int aer_hest_parse(struct acpi_hest_header *hest_hdr, void *data)
60 p = (struct acpi_hest_aer_common *)(hest_hdr + 1); 60 p = (struct acpi_hest_aer_common *)(hest_hdr + 1);
61 if (p->flags & ACPI_HEST_GLOBAL) { 61 if (p->flags & ACPI_HEST_GLOBAL) {
62 if ((pci_is_pcie(info->pci_dev) && 62 if ((pci_is_pcie(info->pci_dev) &&
63 info->pci_dev->pcie_type == pcie_type) || bridge) 63 pci_pcie_type(info->pci_dev) == pcie_type) || bridge)
64 ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST); 64 ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST);
65 } else 65 } else
66 if (hest_match_pci(p, info->pci_dev)) 66 if (hest_match_pci(p, info->pci_dev))
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c
index dc901771d34b..cd46d74ec806 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -32,53 +32,28 @@ static bool nosourceid;
32module_param(forceload, bool, 0); 32module_param(forceload, bool, 0);
33module_param(nosourceid, bool, 0); 33module_param(nosourceid, bool, 0);
34 34
35#define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
36 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
37
35int pci_enable_pcie_error_reporting(struct pci_dev *dev) 38int pci_enable_pcie_error_reporting(struct pci_dev *dev)
36{ 39{
37 u16 reg16 = 0;
38 int pos;
39
40 if (pcie_aer_get_firmware_first(dev)) 40 if (pcie_aer_get_firmware_first(dev))
41 return -EIO; 41 return -EIO;
42 42
43 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 43 if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR))
44 if (!pos)
45 return -EIO;
46
47 pos = pci_pcie_cap(dev);
48 if (!pos)
49 return -EIO; 44 return -EIO;
50 45
51 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &reg16); 46 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
52 reg16 |= (PCI_EXP_DEVCTL_CERE |
53 PCI_EXP_DEVCTL_NFERE |
54 PCI_EXP_DEVCTL_FERE |
55 PCI_EXP_DEVCTL_URRE);
56 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);
57
58 return 0;
59} 47}
60EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting); 48EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
61 49
62int pci_disable_pcie_error_reporting(struct pci_dev *dev) 50int pci_disable_pcie_error_reporting(struct pci_dev *dev)
63{ 51{
64 u16 reg16 = 0;
65 int pos;
66
67 if (pcie_aer_get_firmware_first(dev)) 52 if (pcie_aer_get_firmware_first(dev))
68 return -EIO; 53 return -EIO;
69 54
70 pos = pci_pcie_cap(dev); 55 return pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
71 if (!pos) 56 PCI_EXP_AER_FLAGS);
72 return -EIO;
73
74 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &reg16);
75 reg16 &= ~(PCI_EXP_DEVCTL_CERE |
76 PCI_EXP_DEVCTL_NFERE |
77 PCI_EXP_DEVCTL_FERE |
78 PCI_EXP_DEVCTL_URRE);
79 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);
80
81 return 0;
82} 57}
83EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting); 58EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting);
84 59
@@ -151,18 +126,12 @@ static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
151 */ 126 */
152 if (atomic_read(&dev->enable_cnt) == 0) 127 if (atomic_read(&dev->enable_cnt) == 0)
153 return false; 128 return false;
154 pos = pci_pcie_cap(dev);
155 if (!pos)
156 return false;
157 129
158 /* Check if AER is enabled */ 130 /* Check if AER is enabled */
159 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &reg16); 131 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &reg16);
160 if (!(reg16 & ( 132 if (!(reg16 & PCI_EXP_AER_FLAGS))
161 PCI_EXP_DEVCTL_CERE |
162 PCI_EXP_DEVCTL_NFERE |
163 PCI_EXP_DEVCTL_FERE |
164 PCI_EXP_DEVCTL_URRE)))
165 return false; 133 return false;
134
166 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 135 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
167 if (!pos) 136 if (!pos)
168 return false; 137 return false;
@@ -465,7 +434,7 @@ static pci_ers_result_t reset_link(struct pci_dev *dev)
465 434
466 if (driver && driver->reset_link) { 435 if (driver && driver->reset_link) {
467 status = driver->reset_link(udev); 436 status = driver->reset_link(udev);
468 } else if (udev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) { 437 } else if (pci_pcie_type(udev) == PCI_EXP_TYPE_DOWNSTREAM) {
469 status = default_downstream_reset_link(udev); 438 status = default_downstream_reset_link(udev);
470 } else { 439 } else {
471 dev_printk(KERN_DEBUG, &dev->dev, 440 dev_printk(KERN_DEBUG, &dev->dev,
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index b500840a143b..213753b283a6 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -125,21 +125,16 @@ static int policy_to_clkpm_state(struct pcie_link_state *link)
125 125
126static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable) 126static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
127{ 127{
128 int pos;
129 u16 reg16;
130 struct pci_dev *child; 128 struct pci_dev *child;
131 struct pci_bus *linkbus = link->pdev->subordinate; 129 struct pci_bus *linkbus = link->pdev->subordinate;
132 130
133 list_for_each_entry(child, &linkbus->devices, bus_list) { 131 list_for_each_entry(child, &linkbus->devices, bus_list) {
134 pos = pci_pcie_cap(child);
135 if (!pos)
136 return;
137 pci_read_config_word(child, pos + PCI_EXP_LNKCTL, &reg16);
138 if (enable) 132 if (enable)
139 reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN; 133 pcie_capability_set_word(child, PCI_EXP_LNKCTL,
134 PCI_EXP_LNKCTL_CLKREQ_EN);
140 else 135 else
141 reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN; 136 pcie_capability_clear_word(child, PCI_EXP_LNKCTL,
142 pci_write_config_word(child, pos + PCI_EXP_LNKCTL, reg16); 137 PCI_EXP_LNKCTL_CLKREQ_EN);
143 } 138 }
144 link->clkpm_enabled = !!enable; 139 link->clkpm_enabled = !!enable;
145} 140}
@@ -157,7 +152,7 @@ static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
157 152
158static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) 153static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
159{ 154{
160 int pos, capable = 1, enabled = 1; 155 int capable = 1, enabled = 1;
161 u32 reg32; 156 u32 reg32;
162 u16 reg16; 157 u16 reg16;
163 struct pci_dev *child; 158 struct pci_dev *child;
@@ -165,16 +160,13 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
165 160
166 /* All functions should have the same cap and state, take the worst */ 161 /* All functions should have the same cap and state, take the worst */
167 list_for_each_entry(child, &linkbus->devices, bus_list) { 162 list_for_each_entry(child, &linkbus->devices, bus_list) {
168 pos = pci_pcie_cap(child); 163 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &reg32);
169 if (!pos)
170 return;
171 pci_read_config_dword(child, pos + PCI_EXP_LNKCAP, &reg32);
172 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { 164 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
173 capable = 0; 165 capable = 0;
174 enabled = 0; 166 enabled = 0;
175 break; 167 break;
176 } 168 }
177 pci_read_config_word(child, pos + PCI_EXP_LNKCTL, &reg16); 169 pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);
178 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) 170 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
179 enabled = 0; 171 enabled = 0;
180 } 172 }
@@ -190,7 +182,7 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
190 */ 182 */
191static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) 183static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
192{ 184{
193 int ppos, cpos, same_clock = 1; 185 int same_clock = 1;
194 u16 reg16, parent_reg, child_reg[8]; 186 u16 reg16, parent_reg, child_reg[8];
195 unsigned long start_jiffies; 187 unsigned long start_jiffies;
196 struct pci_dev *child, *parent = link->pdev; 188 struct pci_dev *child, *parent = link->pdev;
@@ -203,46 +195,43 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
203 BUG_ON(!pci_is_pcie(child)); 195 BUG_ON(!pci_is_pcie(child));
204 196
205 /* Check downstream component if bit Slot Clock Configuration is 1 */ 197 /* Check downstream component if bit Slot Clock Configuration is 1 */
206 cpos = pci_pcie_cap(child); 198 pcie_capability_read_word(child, PCI_EXP_LNKSTA, &reg16);
207 pci_read_config_word(child, cpos + PCI_EXP_LNKSTA, &reg16);
208 if (!(reg16 & PCI_EXP_LNKSTA_SLC)) 199 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
209 same_clock = 0; 200 same_clock = 0;
210 201
211 /* Check upstream component if bit Slot Clock Configuration is 1 */ 202 /* Check upstream component if bit Slot Clock Configuration is 1 */
212 ppos = pci_pcie_cap(parent); 203 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
213 pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, &reg16);
214 if (!(reg16 & PCI_EXP_LNKSTA_SLC)) 204 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
215 same_clock = 0; 205 same_clock = 0;
216 206
217 /* Configure downstream component, all functions */ 207 /* Configure downstream component, all functions */
218 list_for_each_entry(child, &linkbus->devices, bus_list) { 208 list_for_each_entry(child, &linkbus->devices, bus_list) {
219 cpos = pci_pcie_cap(child); 209 pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);
220 pci_read_config_word(child, cpos + PCI_EXP_LNKCTL, &reg16);
221 child_reg[PCI_FUNC(child->devfn)] = reg16; 210 child_reg[PCI_FUNC(child->devfn)] = reg16;
222 if (same_clock) 211 if (same_clock)
223 reg16 |= PCI_EXP_LNKCTL_CCC; 212 reg16 |= PCI_EXP_LNKCTL_CCC;
224 else 213 else
225 reg16 &= ~PCI_EXP_LNKCTL_CCC; 214 reg16 &= ~PCI_EXP_LNKCTL_CCC;
226 pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16); 215 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
227 } 216 }
228 217
229 /* Configure upstream component */ 218 /* Configure upstream component */
230 pci_read_config_word(parent, ppos + PCI_EXP_LNKCTL, &reg16); 219 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &reg16);
231 parent_reg = reg16; 220 parent_reg = reg16;
232 if (same_clock) 221 if (same_clock)
233 reg16 |= PCI_EXP_LNKCTL_CCC; 222 reg16 |= PCI_EXP_LNKCTL_CCC;
234 else 223 else
235 reg16 &= ~PCI_EXP_LNKCTL_CCC; 224 reg16 &= ~PCI_EXP_LNKCTL_CCC;
236 pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16); 225 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
237 226
238 /* Retrain link */ 227 /* Retrain link */
239 reg16 |= PCI_EXP_LNKCTL_RL; 228 reg16 |= PCI_EXP_LNKCTL_RL;
240 pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16); 229 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
241 230
242 /* Wait for link training end. Break out after waiting for timeout */ 231 /* Wait for link training end. Break out after waiting for timeout */
243 start_jiffies = jiffies; 232 start_jiffies = jiffies;
244 for (;;) { 233 for (;;) {
245 pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, &reg16); 234 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
246 if (!(reg16 & PCI_EXP_LNKSTA_LT)) 235 if (!(reg16 & PCI_EXP_LNKSTA_LT))
247 break; 236 break;
248 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) 237 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
@@ -255,12 +244,10 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
255 /* Training failed. Restore common clock configurations */ 244 /* Training failed. Restore common clock configurations */
256 dev_printk(KERN_ERR, &parent->dev, 245 dev_printk(KERN_ERR, &parent->dev,
257 "ASPM: Could not configure common clock\n"); 246 "ASPM: Could not configure common clock\n");
258 list_for_each_entry(child, &linkbus->devices, bus_list) { 247 list_for_each_entry(child, &linkbus->devices, bus_list)
259 cpos = pci_pcie_cap(child); 248 pcie_capability_write_word(child, PCI_EXP_LNKCTL,
260 pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, 249 child_reg[PCI_FUNC(child->devfn)]);
261 child_reg[PCI_FUNC(child->devfn)]); 250 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
262 }
263 pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, parent_reg);
264} 251}
265 252
266/* Convert L0s latency encoding to ns */ 253/* Convert L0s latency encoding to ns */
@@ -305,16 +292,14 @@ struct aspm_register_info {
305static void pcie_get_aspm_reg(struct pci_dev *pdev, 292static void pcie_get_aspm_reg(struct pci_dev *pdev,
306 struct aspm_register_info *info) 293 struct aspm_register_info *info)
307{ 294{
308 int pos;
309 u16 reg16; 295 u16 reg16;
310 u32 reg32; 296 u32 reg32;
311 297
312 pos = pci_pcie_cap(pdev); 298 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &reg32);
313 pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, &reg32);
314 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; 299 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
315 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; 300 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
316 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; 301 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
317 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16); 302 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &reg16);
318 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC; 303 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
319} 304}
320 305
@@ -412,7 +397,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
412 * do ASPM for now. 397 * do ASPM for now.
413 */ 398 */
414 list_for_each_entry(child, &linkbus->devices, bus_list) { 399 list_for_each_entry(child, &linkbus->devices, bus_list) {
415 if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) { 400 if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) {
416 link->aspm_disable = ASPM_STATE_ALL; 401 link->aspm_disable = ASPM_STATE_ALL;
417 break; 402 break;
418 } 403 }
@@ -420,17 +405,15 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
420 405
421 /* Get and check endpoint acceptable latencies */ 406 /* Get and check endpoint acceptable latencies */
422 list_for_each_entry(child, &linkbus->devices, bus_list) { 407 list_for_each_entry(child, &linkbus->devices, bus_list) {
423 int pos;
424 u32 reg32, encoding; 408 u32 reg32, encoding;
425 struct aspm_latency *acceptable = 409 struct aspm_latency *acceptable =
426 &link->acceptable[PCI_FUNC(child->devfn)]; 410 &link->acceptable[PCI_FUNC(child->devfn)];
427 411
428 if (child->pcie_type != PCI_EXP_TYPE_ENDPOINT && 412 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
429 child->pcie_type != PCI_EXP_TYPE_LEG_END) 413 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
430 continue; 414 continue;
431 415
432 pos = pci_pcie_cap(child); 416 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
433 pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, &reg32);
434 /* Calculate endpoint L0s acceptable latency */ 417 /* Calculate endpoint L0s acceptable latency */
435 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; 418 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
436 acceptable->l0s = calc_l0s_acceptable(encoding); 419 acceptable->l0s = calc_l0s_acceptable(encoding);
@@ -444,13 +427,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
444 427
445static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) 428static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
446{ 429{
447 u16 reg16; 430 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, 0x3, val);
448 int pos = pci_pcie_cap(pdev);
449
450 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
451 reg16 &= ~0x3;
452 reg16 |= val;
453 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
454} 431}
455 432
456static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) 433static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
@@ -505,7 +482,6 @@ static void free_link_state(struct pcie_link_state *link)
505static int pcie_aspm_sanity_check(struct pci_dev *pdev) 482static int pcie_aspm_sanity_check(struct pci_dev *pdev)
506{ 483{
507 struct pci_dev *child; 484 struct pci_dev *child;
508 int pos;
509 u32 reg32; 485 u32 reg32;
510 486
511 /* 487 /*
@@ -513,8 +489,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
513 * very strange. Disable ASPM for the whole slot 489 * very strange. Disable ASPM for the whole slot
514 */ 490 */
515 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { 491 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
516 pos = pci_pcie_cap(child); 492 if (!pci_is_pcie(child))
517 if (!pos)
518 return -EINVAL; 493 return -EINVAL;
519 494
520 /* 495 /*
@@ -530,7 +505,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
530 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use 505 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
531 * RBER bit to determine if a function is 1.1 version device 506 * RBER bit to determine if a function is 1.1 version device
532 */ 507 */
533 pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, &reg32); 508 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
534 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { 509 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
535 dev_printk(KERN_INFO, &child->dev, "disabling ASPM" 510 dev_printk(KERN_INFO, &child->dev, "disabling ASPM"
536 " on pre-1.1 PCIe device. You can enable it" 511 " on pre-1.1 PCIe device. You can enable it"
@@ -552,7 +527,7 @@ static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
552 INIT_LIST_HEAD(&link->children); 527 INIT_LIST_HEAD(&link->children);
553 INIT_LIST_HEAD(&link->link); 528 INIT_LIST_HEAD(&link->link);
554 link->pdev = pdev; 529 link->pdev = pdev;
555 if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) { 530 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM) {
556 struct pcie_link_state *parent; 531 struct pcie_link_state *parent;
557 parent = pdev->bus->parent->self->link_state; 532 parent = pdev->bus->parent->self->link_state;
558 if (!parent) { 533 if (!parent) {
@@ -585,12 +560,12 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev)
585 560
586 if (!pci_is_pcie(pdev) || pdev->link_state) 561 if (!pci_is_pcie(pdev) || pdev->link_state)
587 return; 562 return;
588 if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && 563 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
589 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) 564 pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM)
590 return; 565 return;
591 566
592 /* VIA has a strange chipset, root port is under a bridge */ 567 /* VIA has a strange chipset, root port is under a bridge */
593 if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT && 568 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
594 pdev->bus->self) 569 pdev->bus->self)
595 return; 570 return;
596 571
@@ -647,8 +622,8 @@ static void pcie_update_aspm_capable(struct pcie_link_state *root)
647 if (link->root != root) 622 if (link->root != root)
648 continue; 623 continue;
649 list_for_each_entry(child, &linkbus->devices, bus_list) { 624 list_for_each_entry(child, &linkbus->devices, bus_list) {
650 if ((child->pcie_type != PCI_EXP_TYPE_ENDPOINT) && 625 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
651 (child->pcie_type != PCI_EXP_TYPE_LEG_END)) 626 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
652 continue; 627 continue;
653 pcie_aspm_check_latency(child); 628 pcie_aspm_check_latency(child);
654 } 629 }
@@ -663,8 +638,8 @@ void pcie_aspm_exit_link_state(struct pci_dev *pdev)
663 638
664 if (!pci_is_pcie(pdev) || !parent || !parent->link_state) 639 if (!pci_is_pcie(pdev) || !parent || !parent->link_state)
665 return; 640 return;
666 if ((parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT) && 641 if ((pci_pcie_type(parent) != PCI_EXP_TYPE_ROOT_PORT) &&
667 (parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)) 642 (pci_pcie_type(parent) != PCI_EXP_TYPE_DOWNSTREAM))
668 return; 643 return;
669 644
670 down_read(&pci_bus_sem); 645 down_read(&pci_bus_sem);
@@ -704,8 +679,8 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev)
704 679
705 if (aspm_disabled || !pci_is_pcie(pdev) || !link) 680 if (aspm_disabled || !pci_is_pcie(pdev) || !link)
706 return; 681 return;
707 if ((pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) && 682 if ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) &&
708 (pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)) 683 (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM))
709 return; 684 return;
710 /* 685 /*
711 * Devices changed PM state, we should recheck if latency 686 * Devices changed PM state, we should recheck if latency
@@ -729,8 +704,8 @@ void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
729 if (aspm_policy != POLICY_POWERSAVE) 704 if (aspm_policy != POLICY_POWERSAVE)
730 return; 705 return;
731 706
732 if ((pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) && 707 if ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) &&
733 (pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)) 708 (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM))
734 return; 709 return;
735 710
736 down_read(&pci_bus_sem); 711 down_read(&pci_bus_sem);
@@ -757,8 +732,8 @@ static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem,
757 if (!pci_is_pcie(pdev)) 732 if (!pci_is_pcie(pdev))
758 return; 733 return;
759 734
760 if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT || 735 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
761 pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) 736 pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM)
762 parent = pdev; 737 parent = pdev;
763 if (!parent || !parent->link_state) 738 if (!parent || !parent->link_state)
764 return; 739 return;
@@ -933,8 +908,8 @@ void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
933 struct pcie_link_state *link_state = pdev->link_state; 908 struct pcie_link_state *link_state = pdev->link_state;
934 909
935 if (!pci_is_pcie(pdev) || 910 if (!pci_is_pcie(pdev) ||
936 (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && 911 (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
937 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) 912 pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
938 return; 913 return;
939 914
940 if (link_state->aspm_support) 915 if (link_state->aspm_support)
@@ -950,8 +925,8 @@ void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
950 struct pcie_link_state *link_state = pdev->link_state; 925 struct pcie_link_state *link_state = pdev->link_state;
951 926
952 if (!pci_is_pcie(pdev) || 927 if (!pci_is_pcie(pdev) ||
953 (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && 928 (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
954 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) 929 pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
955 return; 930 return;
956 931
957 if (link_state->aspm_support) 932 if (link_state->aspm_support)
diff --git a/drivers/pci/pcie/pme.c b/drivers/pci/pcie/pme.c
index 001f1b78f39c..9ca0dc9ffd84 100644
--- a/drivers/pci/pcie/pme.c
+++ b/drivers/pci/pcie/pme.c
@@ -57,17 +57,12 @@ struct pcie_pme_service_data {
57 */ 57 */
58void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable) 58void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable)
59{ 59{
60 int rtctl_pos;
61 u16 rtctl;
62
63 rtctl_pos = pci_pcie_cap(dev) + PCI_EXP_RTCTL;
64
65 pci_read_config_word(dev, rtctl_pos, &rtctl);
66 if (enable) 60 if (enable)
67 rtctl |= PCI_EXP_RTCTL_PMEIE; 61 pcie_capability_set_word(dev, PCI_EXP_RTCTL,
62 PCI_EXP_RTCTL_PMEIE);
68 else 63 else
69 rtctl &= ~PCI_EXP_RTCTL_PMEIE; 64 pcie_capability_clear_word(dev, PCI_EXP_RTCTL,
70 pci_write_config_word(dev, rtctl_pos, rtctl); 65 PCI_EXP_RTCTL_PMEIE);
71} 66}
72 67
73/** 68/**
@@ -120,7 +115,7 @@ static bool pcie_pme_from_pci_bridge(struct pci_bus *bus, u8 devfn)
120 if (!dev) 115 if (!dev)
121 return false; 116 return false;
122 117
123 if (pci_is_pcie(dev) && dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) { 118 if (pci_is_pcie(dev) && pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
124 down_read(&pci_bus_sem); 119 down_read(&pci_bus_sem);
125 if (pcie_pme_walk_bus(bus)) 120 if (pcie_pme_walk_bus(bus))
126 found = true; 121 found = true;
@@ -226,18 +221,15 @@ static void pcie_pme_work_fn(struct work_struct *work)
226 struct pcie_pme_service_data *data = 221 struct pcie_pme_service_data *data =
227 container_of(work, struct pcie_pme_service_data, work); 222 container_of(work, struct pcie_pme_service_data, work);
228 struct pci_dev *port = data->srv->port; 223 struct pci_dev *port = data->srv->port;
229 int rtsta_pos;
230 u32 rtsta; 224 u32 rtsta;
231 225
232 rtsta_pos = pci_pcie_cap(port) + PCI_EXP_RTSTA;
233
234 spin_lock_irq(&data->lock); 226 spin_lock_irq(&data->lock);
235 227
236 for (;;) { 228 for (;;) {
237 if (data->noirq) 229 if (data->noirq)
238 break; 230 break;
239 231
240 pci_read_config_dword(port, rtsta_pos, &rtsta); 232 pcie_capability_read_dword(port, PCI_EXP_RTSTA, &rtsta);
241 if (rtsta & PCI_EXP_RTSTA_PME) { 233 if (rtsta & PCI_EXP_RTSTA_PME) {
242 /* 234 /*
243 * Clear PME status of the port. If there are other 235 * Clear PME status of the port. If there are other
@@ -276,17 +268,14 @@ static irqreturn_t pcie_pme_irq(int irq, void *context)
276{ 268{
277 struct pci_dev *port; 269 struct pci_dev *port;
278 struct pcie_pme_service_data *data; 270 struct pcie_pme_service_data *data;
279 int rtsta_pos;
280 u32 rtsta; 271 u32 rtsta;
281 unsigned long flags; 272 unsigned long flags;
282 273
283 port = ((struct pcie_device *)context)->port; 274 port = ((struct pcie_device *)context)->port;
284 data = get_service_data((struct pcie_device *)context); 275 data = get_service_data((struct pcie_device *)context);
285 276
286 rtsta_pos = pci_pcie_cap(port) + PCI_EXP_RTSTA;
287
288 spin_lock_irqsave(&data->lock, flags); 277 spin_lock_irqsave(&data->lock, flags);
289 pci_read_config_dword(port, rtsta_pos, &rtsta); 278 pcie_capability_read_dword(port, PCI_EXP_RTSTA, &rtsta);
290 279
291 if (!(rtsta & PCI_EXP_RTSTA_PME)) { 280 if (!(rtsta & PCI_EXP_RTSTA_PME)) {
292 spin_unlock_irqrestore(&data->lock, flags); 281 spin_unlock_irqrestore(&data->lock, flags);
@@ -335,13 +324,13 @@ static void pcie_pme_mark_devices(struct pci_dev *port)
335 struct pci_dev *dev; 324 struct pci_dev *dev;
336 325
337 /* Check if this is a root port event collector. */ 326 /* Check if this is a root port event collector. */
338 if (port->pcie_type != PCI_EXP_TYPE_RC_EC || !bus) 327 if (pci_pcie_type(port) != PCI_EXP_TYPE_RC_EC || !bus)
339 return; 328 return;
340 329
341 down_read(&pci_bus_sem); 330 down_read(&pci_bus_sem);
342 list_for_each_entry(dev, &bus->devices, bus_list) 331 list_for_each_entry(dev, &bus->devices, bus_list)
343 if (pci_is_pcie(dev) 332 if (pci_is_pcie(dev)
344 && dev->pcie_type == PCI_EXP_TYPE_RC_END) 333 && pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END)
345 pcie_pme_set_native(dev, NULL); 334 pcie_pme_set_native(dev, NULL);
346 up_read(&pci_bus_sem); 335 up_read(&pci_bus_sem);
347 } 336 }
diff --git a/drivers/pci/pcie/portdrv_bus.c b/drivers/pci/pcie/portdrv_bus.c
index 18bf90f748f6..67be55a7f260 100644
--- a/drivers/pci/pcie/portdrv_bus.c
+++ b/drivers/pci/pcie/portdrv_bus.c
@@ -38,7 +38,7 @@ static int pcie_port_bus_match(struct device *dev, struct device_driver *drv)
38 return 0; 38 return 0;
39 39
40 if ((driver->port_type != PCIE_ANY_PORT) && 40 if ((driver->port_type != PCIE_ANY_PORT) &&
41 (driver->port_type != pciedev->port->pcie_type)) 41 (driver->port_type != pci_pcie_type(pciedev->port)))
42 return 0; 42 return 0;
43 43
44 return 1; 44 return 1;
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index 75915b30ad19..d03a7a39b2d8 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -200,10 +200,13 @@ static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
200{ 200{
201 int i, irq = -1; 201 int i, irq = -1;
202 202
203 /* We have to use INTx if MSI cannot be used for PCIe PME or pciehp. */ 203 /*
204 * If MSI cannot be used for PCIe PME or hotplug, we have to use
205 * INTx or other interrupts, e.g. system shared interrupt.
206 */
204 if (((mask & PCIE_PORT_SERVICE_PME) && pcie_pme_no_msi()) || 207 if (((mask & PCIE_PORT_SERVICE_PME) && pcie_pme_no_msi()) ||
205 ((mask & PCIE_PORT_SERVICE_HP) && pciehp_no_msi())) { 208 ((mask & PCIE_PORT_SERVICE_HP) && pciehp_no_msi())) {
206 if (dev->pin) 209 if (dev->irq)
207 irq = dev->irq; 210 irq = dev->irq;
208 goto no_msi; 211 goto no_msi;
209 } 212 }
@@ -212,8 +215,12 @@ static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
212 if (!pcie_port_enable_msix(dev, irqs, mask)) 215 if (!pcie_port_enable_msix(dev, irqs, mask))
213 return 0; 216 return 0;
214 217
215 /* We're not going to use MSI-X, so try MSI and fall back to INTx */ 218 /*
216 if (!pci_enable_msi(dev) || dev->pin) 219 * We're not going to use MSI-X, so try MSI and fall back to INTx.
220 * If neither MSI/MSI-X nor INTx available, try other interrupt. On
221 * some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
222 */
223 if (!pci_enable_msi(dev) || dev->irq)
217 irq = dev->irq; 224 irq = dev->irq;
218 225
219 no_msi: 226 no_msi:
@@ -246,8 +253,7 @@ static void cleanup_service_irqs(struct pci_dev *dev)
246 */ 253 */
247static int get_port_device_capability(struct pci_dev *dev) 254static int get_port_device_capability(struct pci_dev *dev)
248{ 255{
249 int services = 0, pos; 256 int services = 0;
250 u16 reg16;
251 u32 reg32; 257 u32 reg32;
252 int cap_mask = 0; 258 int cap_mask = 0;
253 int err; 259 int err;
@@ -265,11 +271,9 @@ static int get_port_device_capability(struct pci_dev *dev)
265 return 0; 271 return 0;
266 } 272 }
267 273
268 pos = pci_pcie_cap(dev);
269 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &reg16);
270 /* Hot-Plug Capable */ 274 /* Hot-Plug Capable */
271 if ((cap_mask & PCIE_PORT_SERVICE_HP) && (reg16 & PCI_EXP_FLAGS_SLOT)) { 275 if (cap_mask & PCIE_PORT_SERVICE_HP) {
272 pci_read_config_dword(dev, pos + PCI_EXP_SLTCAP, &reg32); 276 pcie_capability_read_dword(dev, PCI_EXP_SLTCAP, &reg32);
273 if (reg32 & PCI_EXP_SLTCAP_HPC) { 277 if (reg32 & PCI_EXP_SLTCAP_HPC) {
274 services |= PCIE_PORT_SERVICE_HP; 278 services |= PCIE_PORT_SERVICE_HP;
275 /* 279 /*
@@ -277,10 +281,8 @@ static int get_port_device_capability(struct pci_dev *dev)
277 * enabled by the BIOS and the hot-plug service driver 281 * enabled by the BIOS and the hot-plug service driver
278 * is not loaded. 282 * is not loaded.
279 */ 283 */
280 pos += PCI_EXP_SLTCTL; 284 pcie_capability_clear_word(dev, PCI_EXP_SLTCTL,
281 pci_read_config_word(dev, pos, &reg16); 285 PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE);
282 reg16 &= ~(PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE);
283 pci_write_config_word(dev, pos, reg16);
284 } 286 }
285 } 287 }
286 /* AER capable */ 288 /* AER capable */
@@ -298,7 +300,7 @@ static int get_port_device_capability(struct pci_dev *dev)
298 services |= PCIE_PORT_SERVICE_VC; 300 services |= PCIE_PORT_SERVICE_VC;
299 /* Root ports are capable of generating PME too */ 301 /* Root ports are capable of generating PME too */
300 if ((cap_mask & PCIE_PORT_SERVICE_PME) 302 if ((cap_mask & PCIE_PORT_SERVICE_PME)
301 && dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) { 303 && pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
302 services |= PCIE_PORT_SERVICE_PME; 304 services |= PCIE_PORT_SERVICE_PME;
303 /* 305 /*
304 * Disable PME interrupt on this port in case it's been enabled 306 * Disable PME interrupt on this port in case it's been enabled
@@ -336,7 +338,7 @@ static int pcie_device_init(struct pci_dev *pdev, int service, int irq)
336 device->release = release_pcie_device; /* callback to free pcie dev */ 338 device->release = release_pcie_device; /* callback to free pcie dev */
337 dev_set_name(device, "%s:pcie%02x", 339 dev_set_name(device, "%s:pcie%02x",
338 pci_name(pdev), 340 pci_name(pdev),
339 get_descriptor_id(pdev->pcie_type, service)); 341 get_descriptor_id(pci_pcie_type(pdev), service));
340 device->parent = &pdev->dev; 342 device->parent = &pdev->dev;
341 device_enable_async_suspend(device); 343 device_enable_async_suspend(device);
342 344
diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c
index 943443510089..ca10911ee0df 100644
--- a/drivers/pci/pcie/portdrv_pci.c
+++ b/drivers/pci/pcie/portdrv_pci.c
@@ -64,14 +64,7 @@ __setup("pcie_ports=", pcie_port_setup);
64 */ 64 */
65void pcie_clear_root_pme_status(struct pci_dev *dev) 65void pcie_clear_root_pme_status(struct pci_dev *dev)
66{ 66{
67 int rtsta_pos; 67 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
68 u32 rtsta;
69
70 rtsta_pos = pci_pcie_cap(dev) + PCI_EXP_RTSTA;
71
72 pci_read_config_dword(dev, rtsta_pos, &rtsta);
73 rtsta |= PCI_EXP_RTSTA_PME;
74 pci_write_config_dword(dev, rtsta_pos, rtsta);
75} 68}
76 69
77static int pcie_portdrv_restore_config(struct pci_dev *dev) 70static int pcie_portdrv_restore_config(struct pci_dev *dev)
@@ -95,7 +88,7 @@ static int pcie_port_resume_noirq(struct device *dev)
95 * which breaks ACPI-based runtime wakeup on PCI Express, so clear those 88 * which breaks ACPI-based runtime wakeup on PCI Express, so clear those
96 * bits now just in case (shouldn't hurt). 89 * bits now just in case (shouldn't hurt).
97 */ 90 */
98 if(pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) 91 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
99 pcie_clear_root_pme_status(pdev); 92 pcie_clear_root_pme_status(pdev);
100 return 0; 93 return 0;
101} 94}
@@ -186,9 +179,9 @@ static int __devinit pcie_portdrv_probe(struct pci_dev *dev,
186 int status; 179 int status;
187 180
188 if (!pci_is_pcie(dev) || 181 if (!pci_is_pcie(dev) ||
189 ((dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) && 182 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
190 (dev->pcie_type != PCI_EXP_TYPE_UPSTREAM) && 183 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) &&
191 (dev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))) 184 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
192 return -ENODEV; 185 return -ENODEV;
193 186
194 if (!dev->irq && dev->pin) { 187 if (!dev->irq && dev->pin) {
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 6c143b4497ca..d8f513bdf95c 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -603,10 +603,10 @@ static void pci_set_bus_speed(struct pci_bus *bus)
603 u32 linkcap; 603 u32 linkcap;
604 u16 linksta; 604 u16 linksta;
605 605
606 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap); 606 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
607 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf]; 607 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
608 608
609 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta); 609 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
610 pcie_update_link_speed(bus, linksta); 610 pcie_update_link_speed(bus, linksta);
611 } 611 }
612} 612}
@@ -929,24 +929,16 @@ void set_pcie_port_type(struct pci_dev *pdev)
929 pdev->is_pcie = 1; 929 pdev->is_pcie = 1;
930 pdev->pcie_cap = pos; 930 pdev->pcie_cap = pos;
931 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16); 931 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
932 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; 932 pdev->pcie_flags_reg = reg16;
933 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16); 933 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
934 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 934 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
935} 935}
936 936
937void set_pcie_hotplug_bridge(struct pci_dev *pdev) 937void set_pcie_hotplug_bridge(struct pci_dev *pdev)
938{ 938{
939 int pos;
940 u16 reg16;
941 u32 reg32; 939 u32 reg32;
942 940
943 pos = pci_pcie_cap(pdev); 941 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
944 if (!pos)
945 return;
946 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
947 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
948 return;
949 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
950 if (reg32 & PCI_EXP_SLTCAP_HPC) 942 if (reg32 & PCI_EXP_SLTCAP_HPC)
951 pdev->is_hotplug_bridge = 1; 943 pdev->is_hotplug_bridge = 1;
952} 944}
@@ -1160,8 +1152,7 @@ int pci_cfg_space_size(struct pci_dev *dev)
1160 if (class == PCI_CLASS_BRIDGE_HOST) 1152 if (class == PCI_CLASS_BRIDGE_HOST)
1161 return pci_cfg_space_size_ext(dev); 1153 return pci_cfg_space_size_ext(dev);
1162 1154
1163 pos = pci_pcie_cap(dev); 1155 if (!pci_is_pcie(dev)) {
1164 if (!pos) {
1165 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1156 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1166 if (!pos) 1157 if (!pos)
1167 goto fail; 1158 goto fail;
@@ -1383,9 +1374,9 @@ static int only_one_child(struct pci_bus *bus)
1383 1374
1384 if (!parent || !pci_is_pcie(parent)) 1375 if (!parent || !pci_is_pcie(parent))
1385 return 0; 1376 return 0;
1386 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT) 1377 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1387 return 1; 1378 return 1;
1388 if (parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM && 1379 if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM &&
1389 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 1380 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1390 return 1; 1381 return 1;
1391 return 0; 1382 return 0;
@@ -1462,7 +1453,7 @@ static int pcie_find_smpss(struct pci_dev *dev, void *data)
1462 */ 1453 */
1463 if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) || 1454 if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
1464 (dev->bus->self && 1455 (dev->bus->self &&
1465 dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT))) 1456 pci_pcie_type(dev->bus->self) != PCI_EXP_TYPE_ROOT_PORT)))
1466 *smpss = 0; 1457 *smpss = 0;
1467 1458
1468 if (*smpss > dev->pcie_mpss) 1459 if (*smpss > dev->pcie_mpss)
@@ -1478,7 +1469,8 @@ static void pcie_write_mps(struct pci_dev *dev, int mps)
1478 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 1469 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1479 mps = 128 << dev->pcie_mpss; 1470 mps = 128 << dev->pcie_mpss;
1480 1471
1481 if (dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && dev->bus->self) 1472 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1473 dev->bus->self)
1482 /* For "Performance", the assumption is made that 1474 /* For "Performance", the assumption is made that
1483 * downstream communication will never be larger than 1475 * downstream communication will never be larger than
1484 * the MRRS. So, the MPS only needs to be configured 1476 * the MRRS. So, the MPS only needs to be configured
diff --git a/drivers/pci/proc.c b/drivers/pci/proc.c
index 27911b55c2a5..eb907a8faf2a 100644
--- a/drivers/pci/proc.c
+++ b/drivers/pci/proc.c
@@ -434,25 +434,6 @@ int pci_proc_detach_device(struct pci_dev *dev)
434 return 0; 434 return 0;
435} 435}
436 436
437#if 0
438int pci_proc_attach_bus(struct pci_bus* bus)
439{
440 struct proc_dir_entry *de = bus->procdir;
441
442 if (!proc_initialized)
443 return -EACCES;
444
445 if (!de) {
446 char name[16];
447 sprintf(name, "%02x", bus->number);
448 de = bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
449 if (!de)
450 return -ENOMEM;
451 }
452 return 0;
453}
454#endif /* 0 */
455
456int pci_proc_detach_bus(struct pci_bus* bus) 437int pci_proc_detach_bus(struct pci_bus* bus)
457{ 438{
458 struct proc_dir_entry *de = bus->procdir; 439 struct proc_dir_entry *de = bus->procdir;
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 51553179e967..7a451ff56ecc 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3081,17 +3081,36 @@ static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3081 3081
3082static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 3082static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3083{ 3083{
3084 int pos; 3084 int i;
3085 u16 status;
3085 3086
3086 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 3087 /*
3087 if (!pos) 3088 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3088 return -ENOTTY; 3089 *
3090 * The 82599 supports FLR on VFs, but FLR support is reported only
3091 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3092 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3093 */
3089 3094
3090 if (probe) 3095 if (probe)
3091 return 0; 3096 return 0;
3092 3097
3093 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, 3098 /* Wait for Transaction Pending bit clean */
3094 PCI_EXP_DEVCTL_BCR_FLR); 3099 for (i = 0; i < 4; i++) {
3100 if (i)
3101 msleep((1 << (i - 1)) * 100);
3102
3103 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
3104 if (!(status & PCI_EXP_DEVSTA_TRPND))
3105 goto clear;
3106 }
3107
3108 dev_err(&dev->dev, "transaction is not cleared; "
3109 "proceeding with reset anyway\n");
3110
3111clear:
3112 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3113
3095 msleep(100); 3114 msleep(100);
3096 3115
3097 return 0; 3116 return 0;
diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c
index 04a4861b4749..4f9ca9162895 100644
--- a/drivers/pci/remove.c
+++ b/drivers/pci/remove.c
@@ -32,53 +32,30 @@ static void pci_stop_dev(struct pci_dev *dev)
32 32
33static void pci_destroy_dev(struct pci_dev *dev) 33static void pci_destroy_dev(struct pci_dev *dev)
34{ 34{
35 /* Remove the device from the device lists, and prevent any further
36 * list accesses from this device */
37 down_write(&pci_bus_sem); 35 down_write(&pci_bus_sem);
38 list_del(&dev->bus_list); 36 list_del(&dev->bus_list);
39 dev->bus_list.next = dev->bus_list.prev = NULL;
40 up_write(&pci_bus_sem); 37 up_write(&pci_bus_sem);
41 38
42 pci_free_resources(dev); 39 pci_free_resources(dev);
43 pci_dev_put(dev); 40 pci_dev_put(dev);
44} 41}
45 42
46/** 43void pci_remove_bus(struct pci_bus *bus)
47 * pci_remove_device_safe - remove an unused hotplug device
48 * @dev: the device to remove
49 *
50 * Delete the device structure from the device lists and
51 * notify userspace (/sbin/hotplug), but only if the device
52 * in question is not being used by a driver.
53 * Returns 0 on success.
54 */
55#if 0
56int pci_remove_device_safe(struct pci_dev *dev)
57{ 44{
58 if (pci_dev_driver(dev)) 45 pci_proc_detach_bus(bus);
59 return -EBUSY;
60 pci_destroy_dev(dev);
61 return 0;
62}
63#endif /* 0 */
64
65void pci_remove_bus(struct pci_bus *pci_bus)
66{
67 pci_proc_detach_bus(pci_bus);
68 46
69 down_write(&pci_bus_sem); 47 down_write(&pci_bus_sem);
70 list_del(&pci_bus->node); 48 list_del(&bus->node);
71 pci_bus_release_busn_res(pci_bus); 49 pci_bus_release_busn_res(bus);
72 up_write(&pci_bus_sem); 50 up_write(&pci_bus_sem);
73 if (!pci_bus->is_added) 51 if (!bus->is_added)
74 return; 52 return;
75 53
76 pci_remove_legacy_files(pci_bus); 54 pci_remove_legacy_files(bus);
77 device_unregister(&pci_bus->dev); 55 device_unregister(&bus->dev);
78} 56}
79EXPORT_SYMBOL(pci_remove_bus); 57EXPORT_SYMBOL(pci_remove_bus);
80 58
81static void __pci_remove_behind_bridge(struct pci_dev *dev);
82/** 59/**
83 * pci_stop_and_remove_bus_device - remove a PCI device and any children 60 * pci_stop_and_remove_bus_device - remove a PCI device and any children
84 * @dev: the device to remove 61 * @dev: the device to remove
@@ -91,93 +68,27 @@ static void __pci_remove_behind_bridge(struct pci_dev *dev);
91 * device lists, remove the /proc entry, and notify userspace 68 * device lists, remove the /proc entry, and notify userspace
92 * (/sbin/hotplug). 69 * (/sbin/hotplug).
93 */ 70 */
94void __pci_remove_bus_device(struct pci_dev *dev)
95{
96 if (dev->subordinate) {
97 struct pci_bus *b = dev->subordinate;
98
99 __pci_remove_behind_bridge(dev);
100 pci_remove_bus(b);
101 dev->subordinate = NULL;
102 }
103
104 pci_destroy_dev(dev);
105}
106EXPORT_SYMBOL(__pci_remove_bus_device);
107
108void pci_stop_and_remove_bus_device(struct pci_dev *dev) 71void pci_stop_and_remove_bus_device(struct pci_dev *dev)
109{ 72{
110 pci_stop_bus_device(dev); 73 struct pci_bus *bus = dev->subordinate;
111 __pci_remove_bus_device(dev); 74 struct pci_dev *child, *tmp;
112}
113
114static void __pci_remove_behind_bridge(struct pci_dev *dev)
115{
116 struct list_head *l, *n;
117
118 if (dev->subordinate)
119 list_for_each_safe(l, n, &dev->subordinate->devices)
120 __pci_remove_bus_device(pci_dev_b(l));
121}
122
123static void pci_stop_behind_bridge(struct pci_dev *dev)
124{
125 struct list_head *l, *n;
126
127 if (dev->subordinate)
128 list_for_each_safe(l, n, &dev->subordinate->devices)
129 pci_stop_bus_device(pci_dev_b(l));
130}
131
132/**
133 * pci_stop_and_remove_behind_bridge - stop and remove all devices behind
134 * a PCI bridge
135 * @dev: PCI bridge device
136 *
137 * Remove all devices on the bus, except for the parent bridge.
138 * This also removes any child buses, and any devices they may
139 * contain in a depth-first manner.
140 */
141void pci_stop_and_remove_behind_bridge(struct pci_dev *dev)
142{
143 pci_stop_behind_bridge(dev);
144 __pci_remove_behind_bridge(dev);
145}
146
147static void pci_stop_bus_devices(struct pci_bus *bus)
148{
149 struct list_head *l, *n;
150 75
151 /* 76 /*
152 * VFs could be removed by pci_stop_and_remove_bus_device() in the 77 * Removing an SR-IOV PF device removes all the associated VFs,
153 * pci_stop_bus_devices() code path for PF. 78 * which will update the bus->devices list and confuse the
154 * aka, bus->devices get updated in the process. 79 * iterator. Therefore, iterate in reverse so we remove the VFs
155 * but VFs are inserted after PFs when SRIOV is enabled for PF, 80 * first, then the PF.
156 * We can iterate the list backwards to get prev valid PF instead
157 * of removed VF.
158 */ 81 */
159 list_for_each_prev_safe(l, n, &bus->devices) { 82 if (bus) {
160 struct pci_dev *dev = pci_dev_b(l); 83 list_for_each_entry_safe_reverse(child, tmp,
161 pci_stop_bus_device(dev); 84 &bus->devices, bus_list)
162 } 85 pci_stop_and_remove_bus_device(child);
163}
164 86
165/** 87 pci_remove_bus(bus);
166 * pci_stop_bus_device - stop a PCI device and any children 88 dev->subordinate = NULL;
167 * @dev: the device to stop 89 }
168 *
169 * Stop a PCI device (detach the driver, remove from the global list
170 * and so on). This also stop any subordinate buses and children in a
171 * depth-first manner.
172 */
173void pci_stop_bus_device(struct pci_dev *dev)
174{
175 if (dev->subordinate)
176 pci_stop_bus_devices(dev->subordinate);
177 90
178 pci_stop_dev(dev); 91 pci_stop_dev(dev);
92 pci_destroy_dev(dev);
179} 93}
180
181EXPORT_SYMBOL(pci_stop_and_remove_bus_device); 94EXPORT_SYMBOL(pci_stop_and_remove_bus_device);
182EXPORT_SYMBOL(pci_stop_and_remove_behind_bridge);
183EXPORT_SYMBOL_GPL(pci_stop_bus_device);
diff --git a/drivers/pci/rom.c b/drivers/pci/rom.c
index 48ebdb237f3f..0b3037ab8b93 100644
--- a/drivers/pci/rom.c
+++ b/drivers/pci/rom.c
@@ -167,44 +167,6 @@ void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
167 return rom; 167 return rom;
168} 168}
169 169
170#if 0
171/**
172 * pci_map_rom_copy - map a PCI ROM to kernel space, create a copy
173 * @pdev: pointer to pci device struct
174 * @size: pointer to receive size of pci window over ROM
175 *
176 * Return: kernel virtual pointer to image of ROM
177 *
178 * Map a PCI ROM into kernel space. If ROM is boot video ROM,
179 * the shadow BIOS copy will be returned instead of the
180 * actual ROM.
181 */
182void __iomem *pci_map_rom_copy(struct pci_dev *pdev, size_t *size)
183{
184 struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
185 void __iomem *rom;
186
187 rom = pci_map_rom(pdev, size);
188 if (!rom)
189 return NULL;
190
191 if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_SHADOW |
192 IORESOURCE_ROM_BIOS_COPY))
193 return rom;
194
195 res->start = (unsigned long)kmalloc(*size, GFP_KERNEL);
196 if (!res->start)
197 return rom;
198
199 res->end = res->start + *size;
200 memcpy_fromio((void*)(unsigned long)res->start, rom, *size);
201 pci_unmap_rom(pdev, rom);
202 res->flags |= IORESOURCE_ROM_COPY;
203
204 return (void __iomem *)(unsigned long)res->start;
205}
206#endif /* 0 */
207
208/** 170/**
209 * pci_unmap_rom - unmap the ROM from kernel space 171 * pci_unmap_rom - unmap the ROM from kernel space
210 * @pdev: pointer to pci device struct 172 * @pdev: pointer to pci device struct
@@ -226,27 +188,6 @@ void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom)
226 pci_disable_rom(pdev); 188 pci_disable_rom(pdev);
227} 189}
228 190
229#if 0
230/**
231 * pci_remove_rom - disable the ROM and remove its sysfs attribute
232 * @pdev: pointer to pci device struct
233 *
234 * Remove the rom file in sysfs and disable ROM decoding.
235 */
236void pci_remove_rom(struct pci_dev *pdev)
237{
238 struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
239
240 if (pci_resource_len(pdev, PCI_ROM_RESOURCE))
241 sysfs_remove_bin_file(&pdev->dev.kobj, pdev->rom_attr);
242 if (!(res->flags & (IORESOURCE_ROM_ENABLE |
243 IORESOURCE_ROM_SHADOW |
244 IORESOURCE_ROM_BIOS_COPY |
245 IORESOURCE_ROM_COPY)))
246 pci_disable_rom(pdev);
247}
248#endif /* 0 */
249
250/** 191/**
251 * pci_cleanup_rom - free the ROM copy created by pci_map_rom_copy 192 * pci_cleanup_rom - free the ROM copy created by pci_map_rom_copy
252 * @pdev: pointer to pci device struct 193 * @pdev: pointer to pci device struct
diff --git a/drivers/pci/search.c b/drivers/pci/search.c
index 993d4a0a2469..bf969ba58e59 100644
--- a/drivers/pci/search.c
+++ b/drivers/pci/search.c
@@ -41,7 +41,7 @@ pci_find_upstream_pcie_bridge(struct pci_dev *pdev)
41 continue; 41 continue;
42 } 42 }
43 /* PCI device should connect to a PCIe bridge */ 43 /* PCI device should connect to a PCIe bridge */
44 if (pdev->pcie_type != PCI_EXP_TYPE_PCI_BRIDGE) { 44 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_PCI_BRIDGE) {
45 /* Busted hardware? */ 45 /* Busted hardware? */
46 WARN_ON_ONCE(1); 46 WARN_ON_ONCE(1);
47 return NULL; 47 return NULL;
@@ -130,16 +130,14 @@ pci_find_next_bus(const struct pci_bus *from)
130 * decrement the reference count by calling pci_dev_put(). 130 * decrement the reference count by calling pci_dev_put().
131 * If no device is found, %NULL is returned. 131 * If no device is found, %NULL is returned.
132 */ 132 */
133struct pci_dev * pci_get_slot(struct pci_bus *bus, unsigned int devfn) 133struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn)
134{ 134{
135 struct list_head *tmp;
136 struct pci_dev *dev; 135 struct pci_dev *dev;
137 136
138 WARN_ON(in_interrupt()); 137 WARN_ON(in_interrupt());
139 down_read(&pci_bus_sem); 138 down_read(&pci_bus_sem);
140 139
141 list_for_each(tmp, &bus->devices) { 140 list_for_each_entry(dev, &bus->devices, bus_list) {
142 dev = pci_dev_b(tmp);
143 if (dev->devfn == devfn) 141 if (dev->devfn == devfn)
144 goto out; 142 goto out;
145 } 143 }
@@ -245,30 +243,14 @@ struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
245 unsigned int ss_vendor, unsigned int ss_device, 243 unsigned int ss_vendor, unsigned int ss_device,
246 struct pci_dev *from) 244 struct pci_dev *from)
247{ 245{
248 struct pci_dev *pdev; 246 struct pci_device_id id = {
249 struct pci_device_id *id; 247 .vendor = vendor,
250 248 .device = device,
251 /* 249 .subvendor = ss_vendor,
252 * pci_find_subsys() can be called on the ide_setup() path, 250 .subdevice = ss_device,
253 * super-early in boot. But the down_read() will enable local 251 };
254 * interrupts, which can cause some machines to crash. So here we 252
255 * detect and flag that situation and bail out early. 253 return pci_get_dev_by_id(&id, from);
256 */
257 if (unlikely(no_pci_devices()))
258 return NULL;
259
260 id = kzalloc(sizeof(*id), GFP_KERNEL);
261 if (!id)
262 return NULL;
263 id->vendor = vendor;
264 id->device = device;
265 id->subvendor = ss_vendor;
266 id->subdevice = ss_device;
267
268 pdev = pci_get_dev_by_id(id, from);
269 kfree(id);
270
271 return pdev;
272} 254}
273 255
274/** 256/**
@@ -307,19 +289,16 @@ pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from)
307 */ 289 */
308struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from) 290struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
309{ 291{
310 struct pci_dev *dev; 292 struct pci_device_id id = {
311 struct pci_device_id *id; 293 .vendor = PCI_ANY_ID,
312 294 .device = PCI_ANY_ID,
313 id = kzalloc(sizeof(*id), GFP_KERNEL); 295 .subvendor = PCI_ANY_ID,
314 if (!id) 296 .subdevice = PCI_ANY_ID,
315 return NULL; 297 .class_mask = PCI_ANY_ID,
316 id->vendor = id->device = id->subvendor = id->subdevice = PCI_ANY_ID; 298 .class = class,
317 id->class_mask = PCI_ANY_ID; 299 };
318 id->class = class; 300
319 301 return pci_get_dev_by_id(&id, from);
320 dev = pci_get_dev_by_id(id, from);
321 kfree(id);
322 return dev;
323} 302}
324 303
325/** 304/**
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index fb506137aaee..1e808ca338f8 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -697,6 +697,38 @@ static resource_size_t calculate_memsize(resource_size_t size,
697 return size; 697 return size;
698} 698}
699 699
700resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
701 unsigned long type)
702{
703 return 1;
704}
705
706#define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
707#define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
708#define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
709
710static resource_size_t window_alignment(struct pci_bus *bus,
711 unsigned long type)
712{
713 resource_size_t align = 1, arch_align;
714
715 if (type & IORESOURCE_MEM)
716 align = PCI_P2P_DEFAULT_MEM_ALIGN;
717 else if (type & IORESOURCE_IO) {
718 /*
719 * Per spec, I/O windows are 4K-aligned, but some
720 * bridges have an extension to support 1K alignment.
721 */
722 if (bus->self->io_window_1k)
723 align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
724 else
725 align = PCI_P2P_DEFAULT_IO_ALIGN;
726 }
727
728 arch_align = pcibios_window_alignment(bus, type);
729 return max(align, arch_align);
730}
731
700/** 732/**
701 * pbus_size_io() - size the io window of a given bus 733 * pbus_size_io() - size the io window of a given bus
702 * 734 *
@@ -717,17 +749,12 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
717 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); 749 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
718 unsigned long size = 0, size0 = 0, size1 = 0; 750 unsigned long size = 0, size0 = 0, size1 = 0;
719 resource_size_t children_add_size = 0; 751 resource_size_t children_add_size = 0;
720 resource_size_t min_align = 4096, align; 752 resource_size_t min_align, io_align, align;
721 753
722 if (!b_res) 754 if (!b_res)
723 return; 755 return;
724 756
725 /* 757 io_align = min_align = window_alignment(bus, IORESOURCE_IO);
726 * Per spec, I/O windows are 4K-aligned, but some bridges have an
727 * extension to support 1K alignment.
728 */
729 if (bus->self->io_window_1k)
730 min_align = 1024;
731 list_for_each_entry(dev, &bus->devices, bus_list) { 758 list_for_each_entry(dev, &bus->devices, bus_list) {
732 int i; 759 int i;
733 760
@@ -754,8 +781,8 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
754 } 781 }
755 } 782 }
756 783
757 if (min_align > 4096) 784 if (min_align > io_align)
758 min_align = 4096; 785 min_align = io_align;
759 786
760 size0 = calculate_iosize(size, min_size, size1, 787 size0 = calculate_iosize(size, min_size, size1,
761 resource_size(b_res), min_align); 788 resource_size(b_res), min_align);
@@ -785,6 +812,28 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
785 } 812 }
786} 813}
787 814
815static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
816 int max_order)
817{
818 resource_size_t align = 0;
819 resource_size_t min_align = 0;
820 int order;
821
822 for (order = 0; order <= max_order; order++) {
823 resource_size_t align1 = 1;
824
825 align1 <<= (order + 20);
826
827 if (!align)
828 min_align = align1;
829 else if (ALIGN(align + min_align, min_align) < align1)
830 min_align = align1 >> 1;
831 align += aligns[order];
832 }
833
834 return min_align;
835}
836
788/** 837/**
789 * pbus_size_mem() - size the memory window of a given bus 838 * pbus_size_mem() - size the memory window of a given bus
790 * 839 *
@@ -864,19 +913,9 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
864 children_add_size += get_res_add_size(realloc_head, r); 913 children_add_size += get_res_add_size(realloc_head, r);
865 } 914 }
866 } 915 }
867 align = 0;
868 min_align = 0;
869 for (order = 0; order <= max_order; order++) {
870 resource_size_t align1 = 1;
871 916
872 align1 <<= (order + 20); 917 min_align = calculate_mem_align(aligns, max_order);
873 918 min_align = max(min_align, window_alignment(bus, b_res->flags & mask));
874 if (!align)
875 min_align = align1;
876 else if (ALIGN(align + min_align, min_align) < align1)
877 min_align = align1 >> 1;
878 align += aligns[order];
879 }
880 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); 919 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
881 if (children_add_size > add_size) 920 if (children_add_size > add_size)
882 add_size = children_add_size; 921 add_size = children_add_size;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-06 01:01:04 -0500