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path: root/drivers/net/wireless/rt2x00/rt61pci.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt61pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.c722
1 files changed, 378 insertions, 344 deletions
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index 93ea212fedd5..babb240cef3d 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -24,6 +24,7 @@
24 Supported chipsets: RT2561, RT2561s, RT2661. 24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */ 25 */
26 26
27#include <linux/crc-itu-t.h>
27#include <linux/delay.h> 28#include <linux/delay.h>
28#include <linux/etherdevice.h> 29#include <linux/etherdevice.h>
29#include <linux/init.h> 30#include <linux/init.h>
@@ -155,6 +156,12 @@ rf_write:
155 rt2x00_rf_write(rt2x00dev, word, value); 156 rt2x00_rf_write(rt2x00dev, word, value);
156} 157}
157 158
159#ifdef CONFIG_RT61PCI_LEDS
160/*
161 * This function is only called from rt61pci_led_brightness()
162 * make gcc happy by placing this function inside the
163 * same ifdef statement as the caller.
164 */
158static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev, 165static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
159 const u8 command, const u8 token, 166 const u8 command, const u8 token,
160 const u8 arg0, const u8 arg1) 167 const u8 arg0, const u8 arg1)
@@ -181,6 +188,7 @@ static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
181 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1); 188 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
182 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg); 189 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
183} 190}
191#endif /* CONFIG_RT61PCI_LEDS */
184 192
185static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom) 193static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
186{ 194{
@@ -262,83 +270,119 @@ static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
262 u32 reg; 270 u32 reg;
263 271
264 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg); 272 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
265 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);; 273 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
266} 274}
267#else 275#else
268#define rt61pci_rfkill_poll NULL 276#define rt61pci_rfkill_poll NULL
269#endif /* CONFIG_RT61PCI_RFKILL */ 277#endif /* CONFIG_RT61PCI_RFKILL */
270 278
279#ifdef CONFIG_RT61PCI_LEDS
280static void rt61pci_led_brightness(struct led_classdev *led_cdev,
281 enum led_brightness brightness)
282{
283 struct rt2x00_led *led =
284 container_of(led_cdev, struct rt2x00_led, led_dev);
285 unsigned int enabled = brightness != LED_OFF;
286 unsigned int a_mode =
287 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
288 unsigned int bg_mode =
289 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
290
291 if (led->type == LED_TYPE_RADIO) {
292 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
293 MCU_LEDCS_RADIO_STATUS, enabled);
294
295 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
296 (led->rt2x00dev->led_mcu_reg & 0xff),
297 ((led->rt2x00dev->led_mcu_reg >> 8)));
298 } else if (led->type == LED_TYPE_ASSOC) {
299 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
300 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
301 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
302 MCU_LEDCS_LINK_A_STATUS, a_mode);
303
304 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
305 (led->rt2x00dev->led_mcu_reg & 0xff),
306 ((led->rt2x00dev->led_mcu_reg >> 8)));
307 } else if (led->type == LED_TYPE_QUALITY) {
308 /*
309 * The brightness is divided into 6 levels (0 - 5),
310 * this means we need to convert the brightness
311 * argument into the matching level within that range.
312 */
313 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
314 brightness / (LED_FULL / 6), 0);
315 }
316}
317#else
318#define rt61pci_led_brightness NULL
319#endif /* CONFIG_RT61PCI_LEDS */
320
271/* 321/*
272 * Configuration handlers. 322 * Configuration handlers.
273 */ 323 */
274static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac) 324static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
325 struct rt2x00_intf *intf,
326 struct rt2x00intf_conf *conf,
327 const unsigned int flags)
275{ 328{
276 u32 tmp; 329 unsigned int beacon_base;
277 330 u32 reg;
278 tmp = le32_to_cpu(mac[1]);
279 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
280 mac[1] = cpu_to_le32(tmp);
281
282 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
283 (2 * sizeof(__le32)));
284}
285 331
286static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid) 332 if (flags & CONFIG_UPDATE_TYPE) {
287{ 333 /*
288 u32 tmp; 334 * Clear current synchronisation setup.
335 * For the Beacon base registers we only need to clear
336 * the first byte since that byte contains the VALID and OWNER
337 * bits which (when set to 0) will invalidate the entire beacon.
338 */
339 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
340 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
289 341
290 tmp = le32_to_cpu(bssid[1]); 342 /*
291 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3); 343 * Enable synchronisation.
292 bssid[1] = cpu_to_le32(tmp); 344 */
345 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
346 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
347 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
348 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
349 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
350 }
293 351
294 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, bssid, 352 if (flags & CONFIG_UPDATE_MAC) {
295 (2 * sizeof(__le32))); 353 reg = le32_to_cpu(conf->mac[1]);
296} 354 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
355 conf->mac[1] = cpu_to_le32(reg);
297 356
298static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev, const int type, 357 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
299 const int tsf_sync) 358 conf->mac, sizeof(conf->mac));
300{ 359 }
301 u32 reg;
302 360
303 /* 361 if (flags & CONFIG_UPDATE_BSSID) {
304 * Clear current synchronisation setup. 362 reg = le32_to_cpu(conf->bssid[1]);
305 * For the Beacon base registers we only need to clear 363 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
306 * the first byte since that byte contains the VALID and OWNER 364 conf->bssid[1] = cpu_to_le32(reg);
307 * bits which (when set to 0) will invalidate the entire beacon.
308 */
309 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
310 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
311 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
312 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
313 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
314 365
315 /* 366 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
316 * Enable synchronisation. 367 conf->bssid, sizeof(conf->bssid));
317 */ 368 }
318 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
319 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
320 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE,
321 (tsf_sync == TSF_SYNC_BEACON));
322 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
323 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, tsf_sync);
324 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
325} 369}
326 370
327static void rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev, 371static int rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
328 const int short_preamble, 372 struct rt2x00lib_erp *erp)
329 const int ack_timeout,
330 const int ack_consume_time)
331{ 373{
332 u32 reg; 374 u32 reg;
333 375
334 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg); 376 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
335 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout); 377 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
336 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); 378 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
337 379
338 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg); 380 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
339 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 381 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
340 !!short_preamble); 382 !!erp->short_preamble);
341 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); 383 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
384
385 return 0;
342} 386}
343 387
344static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev, 388static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
@@ -427,27 +471,21 @@ static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
427 case ANTENNA_HW_DIVERSITY: 471 case ANTENNA_HW_DIVERSITY:
428 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); 472 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
429 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 473 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
430 (rt2x00dev->curr_hwmode != HWMODE_A)); 474 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
431 break; 475 break;
432 case ANTENNA_A: 476 case ANTENNA_A:
433 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 477 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
434 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); 478 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
435 if (rt2x00dev->curr_hwmode == HWMODE_A) 479 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
436 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); 480 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
437 else 481 else
438 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); 482 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
439 break; 483 break;
440 case ANTENNA_SW_DIVERSITY:
441 /*
442 * NOTE: We should never come here because rt2x00lib is
443 * supposed to catch this and send us the correct antenna
444 * explicitely. However we are nog going to bug about this.
445 * Instead, just default to antenna B.
446 */
447 case ANTENNA_B: 484 case ANTENNA_B:
485 default:
448 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 486 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
449 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); 487 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
450 if (rt2x00dev->curr_hwmode == HWMODE_A) 488 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
451 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); 489 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
452 else 490 else
453 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); 491 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
@@ -486,14 +524,8 @@ static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
486 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 524 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
487 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); 525 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
488 break; 526 break;
489 case ANTENNA_SW_DIVERSITY:
490 /*
491 * NOTE: We should never come here because rt2x00lib is
492 * supposed to catch this and send us the correct antenna
493 * explicitely. However we are nog going to bug about this.
494 * Instead, just default to antenna B.
495 */
496 case ANTENNA_B: 527 case ANTENNA_B:
528 default:
497 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 529 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
498 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); 530 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
499 break; 531 break;
@@ -531,10 +563,6 @@ static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
531 rt61pci_bbp_read(rt2x00dev, 4, &r4); 563 rt61pci_bbp_read(rt2x00dev, 4, &r4);
532 rt61pci_bbp_read(rt2x00dev, 77, &r77); 564 rt61pci_bbp_read(rt2x00dev, 77, &r77);
533 565
534 /* FIXME: Antenna selection for the rf 2529 is very confusing in the
535 * legacy driver. The code below should be ok for non-diversity setups.
536 */
537
538 /* 566 /*
539 * Configure the RX antenna. 567 * Configure the RX antenna.
540 */ 568 */
@@ -544,15 +572,14 @@ static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
544 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); 572 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
545 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0); 573 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
546 break; 574 break;
547 case ANTENNA_SW_DIVERSITY:
548 case ANTENNA_HW_DIVERSITY: 575 case ANTENNA_HW_DIVERSITY:
549 /* 576 /*
550 * NOTE: We should never come here because rt2x00lib is 577 * FIXME: Antenna selection for the rf 2529 is very confusing
551 * supposed to catch this and send us the correct antenna 578 * in the legacy driver. Just default to antenna B until the
552 * explicitely. However we are nog going to bug about this. 579 * legacy code can be properly translated into rt2x00 code.
553 * Instead, just default to antenna B.
554 */ 580 */
555 case ANTENNA_B: 581 case ANTENNA_B:
582 default:
556 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 583 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
557 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); 584 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
558 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1); 585 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
@@ -603,7 +630,14 @@ static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
603 unsigned int i; 630 unsigned int i;
604 u32 reg; 631 u32 reg;
605 632
606 if (rt2x00dev->curr_hwmode == HWMODE_A) { 633 /*
634 * We should never come here because rt2x00lib is supposed
635 * to catch this and send us the correct antenna explicitely.
636 */
637 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
638 ant->tx == ANTENNA_SW_DIVERSITY);
639
640 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
607 sel = antenna_sel_a; 641 sel = antenna_sel_a;
608 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); 642 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
609 } else { 643 } else {
@@ -617,10 +651,9 @@ static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
617 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg); 651 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
618 652
619 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 653 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
620 (rt2x00dev->curr_hwmode == HWMODE_B || 654 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
621 rt2x00dev->curr_hwmode == HWMODE_G));
622 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 655 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
623 (rt2x00dev->curr_hwmode == HWMODE_A)); 656 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
624 657
625 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg); 658 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
626 659
@@ -667,8 +700,8 @@ static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
667} 700}
668 701
669static void rt61pci_config(struct rt2x00_dev *rt2x00dev, 702static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
670 const unsigned int flags, 703 struct rt2x00lib_conf *libconf,
671 struct rt2x00lib_conf *libconf) 704 const unsigned int flags)
672{ 705{
673 if (flags & CONFIG_UPDATE_PHYMODE) 706 if (flags & CONFIG_UPDATE_PHYMODE)
674 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates); 707 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
@@ -684,78 +717,6 @@ static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
684} 717}
685 718
686/* 719/*
687 * LED functions.
688 */
689static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
690{
691 u32 reg;
692 u8 arg0;
693 u8 arg1;
694
695 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
696 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
697 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
698 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
699
700 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
701 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS,
702 (rt2x00dev->rx_status.phymode == MODE_IEEE80211A));
703 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS,
704 (rt2x00dev->rx_status.phymode != MODE_IEEE80211A));
705
706 arg0 = rt2x00dev->led_reg & 0xff;
707 arg1 = (rt2x00dev->led_reg >> 8) & 0xff;
708
709 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
710}
711
712static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
713{
714 u16 led_reg;
715 u8 arg0;
716 u8 arg1;
717
718 led_reg = rt2x00dev->led_reg;
719 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
720 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
721 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
722
723 arg0 = led_reg & 0xff;
724 arg1 = (led_reg >> 8) & 0xff;
725
726 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
727}
728
729static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
730{
731 u8 led;
732
733 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
734 return;
735
736 /*
737 * Led handling requires a positive value for the rssi,
738 * to do that correctly we need to add the correction.
739 */
740 rssi += rt2x00dev->rssi_offset;
741
742 if (rssi <= 30)
743 led = 0;
744 else if (rssi <= 39)
745 led = 1;
746 else if (rssi <= 49)
747 led = 2;
748 else if (rssi <= 53)
749 led = 3;
750 else if (rssi <= 63)
751 led = 4;
752 else
753 led = 5;
754
755 rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
756}
757
758/*
759 * Link tuning 720 * Link tuning
760 */ 721 */
761static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev, 722static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
@@ -789,17 +750,12 @@ static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
789 u8 up_bound; 750 u8 up_bound;
790 u8 low_bound; 751 u8 low_bound;
791 752
792 /*
793 * Update Led strength
794 */
795 rt61pci_activity_led(rt2x00dev, rssi);
796
797 rt61pci_bbp_read(rt2x00dev, 17, &r17); 753 rt61pci_bbp_read(rt2x00dev, 17, &r17);
798 754
799 /* 755 /*
800 * Determine r17 bounds. 756 * Determine r17 bounds.
801 */ 757 */
802 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) { 758 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
803 low_bound = 0x28; 759 low_bound = 0x28;
804 up_bound = 0x48; 760 up_bound = 0x48;
805 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) { 761 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
@@ -816,6 +772,13 @@ static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
816 } 772 }
817 773
818 /* 774 /*
775 * If we are not associated, we should go straight to the
776 * dynamic CCA tuning.
777 */
778 if (!rt2x00dev->intf_associated)
779 goto dynamic_cca_tune;
780
781 /*
819 * Special big-R17 for very short distance 782 * Special big-R17 for very short distance
820 */ 783 */
821 if (rssi >= -35) { 784 if (rssi >= -35) {
@@ -866,6 +829,8 @@ static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
866 return; 829 return;
867 } 830 }
868 831
832dynamic_cca_tune:
833
869 /* 834 /*
870 * r17 does not yet exceed upper limit, continue and base 835 * r17 does not yet exceed upper limit, continue and base
871 * the r17 tuning on the false CCA count. 836 * the r17 tuning on the false CCA count.
@@ -882,7 +847,7 @@ static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
882} 847}
883 848
884/* 849/*
885 * Firmware name function. 850 * Firmware functions
886 */ 851 */
887static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) 852static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
888{ 853{
@@ -906,9 +871,23 @@ static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
906 return fw_name; 871 return fw_name;
907} 872}
908 873
909/* 874static u16 rt61pci_get_firmware_crc(void *data, const size_t len)
910 * Initialization functions. 875{
911 */ 876 u16 crc;
877
878 /*
879 * Use the crc itu-t algorithm.
880 * The last 2 bytes in the firmware array are the crc checksum itself,
881 * this means that we should never pass those 2 bytes to the crc
882 * algorithm.
883 */
884 crc = crc_itu_t(0, data, len - 2);
885 crc = crc_itu_t_byte(crc, 0);
886 crc = crc_itu_t_byte(crc, 0);
887
888 return crc;
889}
890
912static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data, 891static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
913 const size_t len) 892 const size_t len)
914{ 893{
@@ -989,50 +968,55 @@ static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
989 return 0; 968 return 0;
990} 969}
991 970
971/*
972 * Initialization functions.
973 */
992static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev, 974static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
993 struct data_entry *entry) 975 struct queue_entry *entry)
994{ 976{
995 __le32 *rxd = entry->priv; 977 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
996 u32 word; 978 u32 word;
997 979
998 rt2x00_desc_read(rxd, 5, &word); 980 rt2x00_desc_read(priv_rx->desc, 5, &word);
999 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, 981 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1000 entry->data_dma); 982 priv_rx->data_dma);
1001 rt2x00_desc_write(rxd, 5, word); 983 rt2x00_desc_write(priv_rx->desc, 5, word);
1002 984
1003 rt2x00_desc_read(rxd, 0, &word); 985 rt2x00_desc_read(priv_rx->desc, 0, &word);
1004 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); 986 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1005 rt2x00_desc_write(rxd, 0, word); 987 rt2x00_desc_write(priv_rx->desc, 0, word);
1006} 988}
1007 989
1008static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev, 990static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1009 struct data_entry *entry) 991 struct queue_entry *entry)
1010{ 992{
1011 __le32 *txd = entry->priv; 993 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
1012 u32 word; 994 u32 word;
1013 995
1014 rt2x00_desc_read(txd, 1, &word); 996 rt2x00_desc_read(priv_tx->desc, 1, &word);
1015 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1); 997 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1016 rt2x00_desc_write(txd, 1, word); 998 rt2x00_desc_write(priv_tx->desc, 1, word);
1017 999
1018 rt2x00_desc_read(txd, 5, &word); 1000 rt2x00_desc_read(priv_tx->desc, 5, &word);
1019 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->ring->queue_idx); 1001 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1020 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx); 1002 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
1021 rt2x00_desc_write(txd, 5, word); 1003 rt2x00_desc_write(priv_tx->desc, 5, word);
1022 1004
1023 rt2x00_desc_read(txd, 6, &word); 1005 rt2x00_desc_read(priv_tx->desc, 6, &word);
1024 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, 1006 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1025 entry->data_dma); 1007 priv_tx->data_dma);
1026 rt2x00_desc_write(txd, 6, word); 1008 rt2x00_desc_write(priv_tx->desc, 6, word);
1027 1009
1028 rt2x00_desc_read(txd, 0, &word); 1010 rt2x00_desc_read(priv_tx->desc, 0, &word);
1029 rt2x00_set_field32(&word, TXD_W0_VALID, 0); 1011 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1030 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); 1012 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1031 rt2x00_desc_write(txd, 0, word); 1013 rt2x00_desc_write(priv_tx->desc, 0, word);
1032} 1014}
1033 1015
1034static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev) 1016static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1035{ 1017{
1018 struct queue_entry_priv_pci_rx *priv_rx;
1019 struct queue_entry_priv_pci_tx *priv_tx;
1036 u32 reg; 1020 u32 reg;
1037 1021
1038 /* 1022 /*
@@ -1040,59 +1024,55 @@ static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1040 */ 1024 */
1041 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg); 1025 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1042 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE, 1026 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1043 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit); 1027 rt2x00dev->tx[0].limit);
1044 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE, 1028 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1045 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit); 1029 rt2x00dev->tx[1].limit);
1046 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE, 1030 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1047 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit); 1031 rt2x00dev->tx[2].limit);
1048 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE, 1032 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1049 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit); 1033 rt2x00dev->tx[3].limit);
1050 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg); 1034 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1051 1035
1052 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg); 1036 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1053 rt2x00_set_field32(&reg, TX_RING_CSR1_MGMT_RING_SIZE,
1054 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
1055 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE, 1037 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1056 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size / 1038 rt2x00dev->tx[0].desc_size / 4);
1057 4);
1058 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg); 1039 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1059 1040
1041 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
1060 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg); 1042 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1061 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER, 1043 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1062 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma); 1044 priv_tx->desc_dma);
1063 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg); 1045 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1064 1046
1047 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
1065 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg); 1048 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1066 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER, 1049 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1067 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma); 1050 priv_tx->desc_dma);
1068 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg); 1051 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1069 1052
1053 priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
1070 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg); 1054 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1071 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER, 1055 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1072 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma); 1056 priv_tx->desc_dma);
1073 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg); 1057 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1074 1058
1059 priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
1075 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg); 1060 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1076 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER, 1061 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1077 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma); 1062 priv_tx->desc_dma);
1078 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg); 1063 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1079 1064
1080 rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, &reg);
1081 rt2x00_set_field32(&reg, MGMT_BASE_CSR_RING_REGISTER,
1082 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
1083 rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
1084
1085 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg); 1065 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1086 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, 1066 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1087 rt2x00dev->rx->stats.limit);
1088 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE, 1067 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1089 rt2x00dev->rx->desc_size / 4); 1068 rt2x00dev->rx->desc_size / 4);
1090 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); 1069 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1091 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg); 1070 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1092 1071
1072 priv_rx = rt2x00dev->rx->entries[0].priv_data;
1093 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg); 1073 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1094 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER, 1074 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1095 rt2x00dev->rx->data_dma); 1075 priv_rx->desc_dma);
1096 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg); 1076 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1097 1077
1098 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg); 1078 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
@@ -1100,7 +1080,6 @@ static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1100 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2); 1080 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1101 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2); 1081 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1102 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2); 1082 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1103 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_MGMT, 0);
1104 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); 1083 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1105 1084
1106 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg); 1085 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
@@ -1108,7 +1087,6 @@ static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1108 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1); 1087 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1109 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1); 1088 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1110 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1); 1089 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1111 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1);
1112 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); 1090 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1113 1091
1114 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg); 1092 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
@@ -1194,6 +1172,11 @@ static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1194 1172
1195 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000); 1173 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1196 1174
1175 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
1176 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
1177 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
1178 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
1179
1197 /* 1180 /*
1198 * Invalidate all Shared Keys (SEC_CSR0), 1181 * Invalidate all Shared Keys (SEC_CSR0),
1199 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) 1182 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
@@ -1224,6 +1207,17 @@ static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1224 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg); 1207 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1225 1208
1226 /* 1209 /*
1210 * Clear all beacons
1211 * For the Beacon base registers we only need to clear
1212 * the first byte since that byte contains the VALID and OWNER
1213 * bits which (when set to 0) will invalidate the entire beacon.
1214 */
1215 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1216 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1217 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1218 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1219
1220 /*
1227 * We must clear the error counters. 1221 * We must clear the error counters.
1228 * These registers are cleared on read, 1222 * These registers are cleared on read,
1229 * so we may pass a useless variable to store the value. 1223 * so we may pass a useless variable to store the value.
@@ -1296,19 +1290,15 @@ continue_csr_init:
1296 rt61pci_bbp_write(rt2x00dev, 102, 0x16); 1290 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1297 rt61pci_bbp_write(rt2x00dev, 107, 0x04); 1291 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1298 1292
1299 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1300 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 1293 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1301 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); 1294 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1302 1295
1303 if (eeprom != 0xffff && eeprom != 0x0000) { 1296 if (eeprom != 0xffff && eeprom != 0x0000) {
1304 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 1297 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1305 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 1298 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1306 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1307 reg_id, value);
1308 rt61pci_bbp_write(rt2x00dev, reg_id, value); 1299 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1309 } 1300 }
1310 } 1301 }
1311 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1312 1302
1313 return 0; 1303 return 0;
1314} 1304}
@@ -1375,7 +1365,7 @@ static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1375 /* 1365 /*
1376 * Initialize all registers. 1366 * Initialize all registers.
1377 */ 1367 */
1378 if (rt61pci_init_rings(rt2x00dev) || 1368 if (rt61pci_init_queues(rt2x00dev) ||
1379 rt61pci_init_registers(rt2x00dev) || 1369 rt61pci_init_registers(rt2x00dev) ||
1380 rt61pci_init_bbp(rt2x00dev)) { 1370 rt61pci_init_bbp(rt2x00dev)) {
1381 ERROR(rt2x00dev, "Register initialization failed.\n"); 1371 ERROR(rt2x00dev, "Register initialization failed.\n");
@@ -1394,11 +1384,6 @@ static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1394 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1); 1384 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1395 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg); 1385 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1396 1386
1397 /*
1398 * Enable LED
1399 */
1400 rt61pci_enable_led(rt2x00dev);
1401
1402 return 0; 1387 return 0;
1403} 1388}
1404 1389
@@ -1406,11 +1391,6 @@ static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1406{ 1391{
1407 u32 reg; 1392 u32 reg;
1408 1393
1409 /*
1410 * Disable LED
1411 */
1412 rt61pci_disable_led(rt2x00dev);
1413
1414 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818); 1394 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1415 1395
1416 /* 1396 /*
@@ -1426,7 +1406,6 @@ static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1426 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1); 1406 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1427 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1); 1407 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1428 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1); 1408 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1429 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
1430 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1409 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1431 1410
1432 /* 1411 /*
@@ -1508,10 +1487,10 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1508 */ 1487 */
1509static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, 1488static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1510 struct sk_buff *skb, 1489 struct sk_buff *skb,
1511 struct txdata_entry_desc *desc, 1490 struct txentry_desc *txdesc,
1512 struct ieee80211_tx_control *control) 1491 struct ieee80211_tx_control *control)
1513{ 1492{
1514 struct skb_desc *skbdesc = get_skb_desc(skb); 1493 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1515 __le32 *txd = skbdesc->desc; 1494 __le32 *txd = skbdesc->desc;
1516 u32 word; 1495 u32 word;
1517 1496
@@ -1519,50 +1498,52 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1519 * Start writing the descriptor words. 1498 * Start writing the descriptor words.
1520 */ 1499 */
1521 rt2x00_desc_read(txd, 1, &word); 1500 rt2x00_desc_read(txd, 1, &word);
1522 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue); 1501 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1523 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs); 1502 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1524 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min); 1503 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1525 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max); 1504 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1526 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER); 1505 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1527 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1); 1506 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1528 rt2x00_desc_write(txd, 1, word); 1507 rt2x00_desc_write(txd, 1, word);
1529 1508
1530 rt2x00_desc_read(txd, 2, &word); 1509 rt2x00_desc_read(txd, 2, &word);
1531 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal); 1510 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1532 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service); 1511 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1533 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low); 1512 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1534 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high); 1513 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1535 rt2x00_desc_write(txd, 2, word); 1514 rt2x00_desc_write(txd, 2, word);
1536 1515
1537 rt2x00_desc_read(txd, 5, &word); 1516 rt2x00_desc_read(txd, 5, &word);
1538 rt2x00_set_field32(&word, TXD_W5_TX_POWER, 1517 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1539 TXPOWER_TO_DEV(control->power_level)); 1518 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1540 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); 1519 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1541 rt2x00_desc_write(txd, 5, word); 1520 rt2x00_desc_write(txd, 5, word);
1542 1521
1543 rt2x00_desc_read(txd, 11, &word); 1522 if (skbdesc->desc_len > TXINFO_SIZE) {
1544 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len); 1523 rt2x00_desc_read(txd, 11, &word);
1545 rt2x00_desc_write(txd, 11, word); 1524 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1525 rt2x00_desc_write(txd, 11, word);
1526 }
1546 1527
1547 rt2x00_desc_read(txd, 0, &word); 1528 rt2x00_desc_read(txd, 0, &word);
1548 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); 1529 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1549 rt2x00_set_field32(&word, TXD_W0_VALID, 1); 1530 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1550 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, 1531 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1551 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags)); 1532 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1552 rt2x00_set_field32(&word, TXD_W0_ACK, 1533 rt2x00_set_field32(&word, TXD_W0_ACK,
1553 test_bit(ENTRY_TXD_ACK, &desc->flags)); 1534 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1554 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, 1535 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1555 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags)); 1536 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1556 rt2x00_set_field32(&word, TXD_W0_OFDM, 1537 rt2x00_set_field32(&word, TXD_W0_OFDM,
1557 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags)); 1538 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1558 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs); 1539 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1559 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1540 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1560 !!(control->flags & 1541 !!(control->flags &
1561 IEEE80211_TXCTL_LONG_RETRY_LIMIT)); 1542 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1562 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0); 1543 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1563 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len); 1544 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1564 rt2x00_set_field32(&word, TXD_W0_BURST, 1545 rt2x00_set_field32(&word, TXD_W0_BURST,
1565 test_bit(ENTRY_TXD_BURST, &desc->flags)); 1546 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1566 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); 1547 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1567 rt2x00_desc_write(txd, 0, word); 1548 rt2x00_desc_write(txd, 0, word);
1568} 1549}
@@ -1571,11 +1552,11 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1571 * TX data initialization 1552 * TX data initialization
1572 */ 1553 */
1573static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, 1554static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1574 unsigned int queue) 1555 const unsigned int queue)
1575{ 1556{
1576 u32 reg; 1557 u32 reg;
1577 1558
1578 if (queue == IEEE80211_TX_QUEUE_BEACON) { 1559 if (queue == RT2X00_BCN_QUEUE_BEACON) {
1579 /* 1560 /*
1580 * For Wi-Fi faily generated beacons between participating 1561 * For Wi-Fi faily generated beacons between participating
1581 * stations. Set TBTT phase adaptive adjustment step to 8us. 1562 * stations. Set TBTT phase adaptive adjustment step to 8us.
@@ -1584,6 +1565,8 @@ static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1584 1565
1585 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 1566 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1586 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) { 1567 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1568 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1569 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1587 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1); 1570 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1588 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 1571 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1589 } 1572 }
@@ -1599,8 +1582,6 @@ static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1599 (queue == IEEE80211_TX_QUEUE_DATA2)); 1582 (queue == IEEE80211_TX_QUEUE_DATA2));
1600 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1583 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3,
1601 (queue == IEEE80211_TX_QUEUE_DATA3)); 1584 (queue == IEEE80211_TX_QUEUE_DATA3));
1602 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_MGMT,
1603 (queue == IEEE80211_TX_QUEUE_DATA4));
1604 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1585 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1605} 1586}
1606 1587
@@ -1628,7 +1609,7 @@ static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1628 return 0; 1609 return 0;
1629 } 1610 }
1630 1611
1631 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) { 1612 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1632 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) 1613 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1633 offset += 14; 1614 offset += 14;
1634 1615
@@ -1648,28 +1629,32 @@ static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1648 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset; 1629 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1649} 1630}
1650 1631
1651static void rt61pci_fill_rxdone(struct data_entry *entry, 1632static void rt61pci_fill_rxdone(struct queue_entry *entry,
1652 struct rxdata_entry_desc *desc) 1633 struct rxdone_entry_desc *rxdesc)
1653{ 1634{
1654 __le32 *rxd = entry->priv; 1635 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1655 u32 word0; 1636 u32 word0;
1656 u32 word1; 1637 u32 word1;
1657 1638
1658 rt2x00_desc_read(rxd, 0, &word0); 1639 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1659 rt2x00_desc_read(rxd, 1, &word1); 1640 rt2x00_desc_read(priv_rx->desc, 1, &word1);
1660 1641
1661 desc->flags = 0; 1642 rxdesc->flags = 0;
1662 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1643 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1663 desc->flags |= RX_FLAG_FAILED_FCS_CRC; 1644 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1664 1645
1665 /* 1646 /*
1666 * Obtain the status about this packet. 1647 * Obtain the status about this packet.
1667 */ 1648 * When frame was received with an OFDM bitrate,
1668 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL); 1649 * the signal is the PLCP value. If it was received with
1669 desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1); 1650 * a CCK bitrate the signal is the rate in 100kbit/s.
1670 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM); 1651 */
1671 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); 1652 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1672 desc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS); 1653 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1654 rxdesc->signal_plcp = rxdesc->ofdm;
1655 rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1656 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1657 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1673} 1658}
1674 1659
1675/* 1660/*
@@ -1677,17 +1662,16 @@ static void rt61pci_fill_rxdone(struct data_entry *entry,
1677 */ 1662 */
1678static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev) 1663static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1679{ 1664{
1680 struct data_ring *ring; 1665 struct data_queue *queue;
1681 struct data_entry *entry; 1666 struct queue_entry *entry;
1682 struct data_entry *entry_done; 1667 struct queue_entry *entry_done;
1683 __le32 *txd; 1668 struct queue_entry_priv_pci_tx *priv_tx;
1669 struct txdone_entry_desc txdesc;
1684 u32 word; 1670 u32 word;
1685 u32 reg; 1671 u32 reg;
1686 u32 old_reg; 1672 u32 old_reg;
1687 int type; 1673 int type;
1688 int index; 1674 int index;
1689 int tx_status;
1690 int retry;
1691 1675
1692 /* 1676 /*
1693 * During each loop we will compare the freshly read 1677 * During each loop we will compare the freshly read
@@ -1710,11 +1694,11 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1710 1694
1711 /* 1695 /*
1712 * Skip this entry when it contains an invalid 1696 * Skip this entry when it contains an invalid
1713 * ring identication number. 1697 * queue identication number.
1714 */ 1698 */
1715 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE); 1699 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1716 ring = rt2x00lib_get_ring(rt2x00dev, type); 1700 queue = rt2x00queue_get_queue(rt2x00dev, type);
1717 if (unlikely(!ring)) 1701 if (unlikely(!queue))
1718 continue; 1702 continue;
1719 1703
1720 /* 1704 /*
@@ -1722,36 +1706,40 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1722 * index number. 1706 * index number.
1723 */ 1707 */
1724 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE); 1708 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1725 if (unlikely(index >= ring->stats.limit)) 1709 if (unlikely(index >= queue->limit))
1726 continue; 1710 continue;
1727 1711
1728 entry = &ring->entry[index]; 1712 entry = &queue->entries[index];
1729 txd = entry->priv; 1713 priv_tx = entry->priv_data;
1730 rt2x00_desc_read(txd, 0, &word); 1714 rt2x00_desc_read(priv_tx->desc, 0, &word);
1731 1715
1732 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 1716 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1733 !rt2x00_get_field32(word, TXD_W0_VALID)) 1717 !rt2x00_get_field32(word, TXD_W0_VALID))
1734 return; 1718 return;
1735 1719
1736 entry_done = rt2x00_get_data_entry_done(ring); 1720 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1737 while (entry != entry_done) { 1721 while (entry != entry_done) {
1738 /* Catch up. Just report any entries we missed as 1722 /* Catch up.
1739 * failed. */ 1723 * Just report any entries we missed as failed.
1724 */
1740 WARNING(rt2x00dev, 1725 WARNING(rt2x00dev,
1741 "TX status report missed for entry %p\n", 1726 "TX status report missed for entry %d\n",
1742 entry_done); 1727 entry_done->entry_idx);
1743 rt2x00pci_txdone(rt2x00dev, entry_done, TX_FAIL_OTHER, 1728
1744 0); 1729 txdesc.status = TX_FAIL_OTHER;
1745 entry_done = rt2x00_get_data_entry_done(ring); 1730 txdesc.retry = 0;
1731
1732 rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
1733 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1746 } 1734 }
1747 1735
1748 /* 1736 /*
1749 * Obtain the status about this packet. 1737 * Obtain the status about this packet.
1750 */ 1738 */
1751 tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT); 1739 txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1752 retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT); 1740 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1753 1741
1754 rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry); 1742 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1755 } 1743 }
1756} 1744}
1757 1745
@@ -1906,7 +1894,7 @@ static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1906 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); 1894 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1907 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); 1895 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1908 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); 1896 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1909 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); 1897 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1910 } else { 1898 } else {
1911 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1); 1899 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1912 if (value < -10 || value > 10) 1900 if (value < -10 || value > 10)
@@ -2035,35 +2023,51 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2035 * If the eeprom value is invalid, 2023 * If the eeprom value is invalid,
2036 * switch to default led mode. 2024 * switch to default led mode.
2037 */ 2025 */
2026#ifdef CONFIG_RT61PCI_LEDS
2038 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom); 2027 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2039 2028
2040 rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE); 2029 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2030
2031 switch (value) {
2032 case LED_MODE_TXRX_ACTIVITY:
2033 case LED_MODE_ASUS:
2034 case LED_MODE_ALPHA:
2035 case LED_MODE_DEFAULT:
2036 rt2x00dev->led_flags =
2037 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
2038 break;
2039 case LED_MODE_SIGNAL_STRENGTH:
2040 rt2x00dev->led_flags =
2041 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
2042 LED_SUPPORT_QUALITY;
2043 break;
2044 }
2041 2045
2042 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE, 2046 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2043 rt2x00dev->led_mode); 2047 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2044 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
2045 rt2x00_get_field16(eeprom, 2048 rt2x00_get_field16(eeprom,
2046 EEPROM_LED_POLARITY_GPIO_0)); 2049 EEPROM_LED_POLARITY_GPIO_0));
2047 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1, 2050 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2048 rt2x00_get_field16(eeprom, 2051 rt2x00_get_field16(eeprom,
2049 EEPROM_LED_POLARITY_GPIO_1)); 2052 EEPROM_LED_POLARITY_GPIO_1));
2050 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2, 2053 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2051 rt2x00_get_field16(eeprom, 2054 rt2x00_get_field16(eeprom,
2052 EEPROM_LED_POLARITY_GPIO_2)); 2055 EEPROM_LED_POLARITY_GPIO_2));
2053 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3, 2056 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2054 rt2x00_get_field16(eeprom, 2057 rt2x00_get_field16(eeprom,
2055 EEPROM_LED_POLARITY_GPIO_3)); 2058 EEPROM_LED_POLARITY_GPIO_3));
2056 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4, 2059 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2057 rt2x00_get_field16(eeprom, 2060 rt2x00_get_field16(eeprom,
2058 EEPROM_LED_POLARITY_GPIO_4)); 2061 EEPROM_LED_POLARITY_GPIO_4));
2059 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT, 2062 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2060 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT)); 2063 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2061 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG, 2064 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2062 rt2x00_get_field16(eeprom, 2065 rt2x00_get_field16(eeprom,
2063 EEPROM_LED_POLARITY_RDY_G)); 2066 EEPROM_LED_POLARITY_RDY_G));
2064 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A, 2067 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2065 rt2x00_get_field16(eeprom, 2068 rt2x00_get_field16(eeprom,
2066 EEPROM_LED_POLARITY_RDY_A)); 2069 EEPROM_LED_POLARITY_RDY_A));
2070#endif /* CONFIG_RT61PCI_LEDS */
2067 2071
2068 return 0; 2072 return 0;
2069} 2073}
@@ -2197,7 +2201,7 @@ static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2197 rt2x00dev->hw->extra_tx_headroom = 0; 2201 rt2x00dev->hw->extra_tx_headroom = 0;
2198 rt2x00dev->hw->max_signal = MAX_SIGNAL; 2202 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2199 rt2x00dev->hw->max_rssi = MAX_RX_SSI; 2203 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2200 rt2x00dev->hw->queues = 5; 2204 rt2x00dev->hw->queues = 4;
2201 2205
2202 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev); 2206 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2203 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 2207 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
@@ -2214,8 +2218,8 @@ static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2214 /* 2218 /*
2215 * Initialize hw_mode information. 2219 * Initialize hw_mode information.
2216 */ 2220 */
2217 spec->num_modes = 2; 2221 spec->supported_bands = SUPPORT_BAND_2GHZ;
2218 spec->num_rates = 12; 2222 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2219 spec->tx_power_a = NULL; 2223 spec->tx_power_a = NULL;
2220 spec->tx_power_bg = txpower; 2224 spec->tx_power_bg = txpower;
2221 spec->tx_power_default = DEFAULT_TXPOWER; 2225 spec->tx_power_default = DEFAULT_TXPOWER;
@@ -2230,7 +2234,7 @@ static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2230 2234
2231 if (rt2x00_rf(&rt2x00dev->chip, RF5225) || 2235 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2232 rt2x00_rf(&rt2x00dev->chip, RF5325)) { 2236 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2233 spec->num_modes = 3; 2237 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2234 spec->num_channels = ARRAY_SIZE(rf_vals_seq); 2238 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2235 2239
2236 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); 2240 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
@@ -2262,7 +2266,7 @@ static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2262 rt61pci_probe_hw_mode(rt2x00dev); 2266 rt61pci_probe_hw_mode(rt2x00dev);
2263 2267
2264 /* 2268 /*
2265 * This device requires firmware 2269 * This device requires firmware.
2266 */ 2270 */
2267 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags); 2271 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2268 2272
@@ -2336,8 +2340,9 @@ static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2336 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1); 2340 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2337 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST, 2341 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
2338 !(*total_flags & FIF_ALLMULTI)); 2342 !(*total_flags & FIF_ALLMULTI));
2339 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BORADCAST, 0); 2343 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
2340 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1); 2344 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
2345 !(*total_flags & FIF_CONTROL));
2341 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); 2346 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2342} 2347}
2343 2348
@@ -2369,37 +2374,25 @@ static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2369 return tsf; 2374 return tsf;
2370} 2375}
2371 2376
2372static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2373{
2374 struct rt2x00_dev *rt2x00dev = hw->priv;
2375
2376 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2377 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2378}
2379
2380static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, 2377static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2381 struct ieee80211_tx_control *control) 2378 struct ieee80211_tx_control *control)
2382{ 2379{
2383 struct rt2x00_dev *rt2x00dev = hw->priv; 2380 struct rt2x00_dev *rt2x00dev = hw->priv;
2384 struct skb_desc *desc; 2381 struct rt2x00_intf *intf = vif_to_intf(control->vif);
2385 struct data_ring *ring; 2382 struct skb_frame_desc *skbdesc;
2386 struct data_entry *entry; 2383 unsigned int beacon_base;
2384 u32 reg;
2387 2385
2388 /* 2386 if (unlikely(!intf->beacon))
2389 * Just in case the ieee80211 doesn't set this, 2387 return -ENOBUFS;
2390 * but we need this queue set for the descriptor
2391 * initialization.
2392 */
2393 control->queue = IEEE80211_TX_QUEUE_BEACON;
2394 ring = rt2x00lib_get_ring(rt2x00dev, control->queue);
2395 entry = rt2x00_get_data_entry(ring);
2396 2388
2397 /* 2389 /*
2398 * We need to append the descriptor in front of the 2390 * We need to append the descriptor in front of the
2399 * beacon frame. 2391 * beacon frame.
2400 */ 2392 */
2401 if (skb_headroom(skb) < TXD_DESC_SIZE) { 2393 if (skb_headroom(skb) < intf->beacon->queue->desc_size) {
2402 if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) { 2394 if (pskb_expand_head(skb, intf->beacon->queue->desc_size,
2395 0, GFP_ATOMIC)) {
2403 dev_kfree_skb(skb); 2396 dev_kfree_skb(skb);
2404 return -ENOMEM; 2397 return -ENOMEM;
2405 } 2398 }
@@ -2408,29 +2401,47 @@ static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2408 /* 2401 /*
2409 * Add the descriptor in front of the skb. 2402 * Add the descriptor in front of the skb.
2410 */ 2403 */
2411 skb_push(skb, ring->desc_size); 2404 skb_push(skb, intf->beacon->queue->desc_size);
2412 memset(skb->data, 0, ring->desc_size); 2405 memset(skb->data, 0, intf->beacon->queue->desc_size);
2413 2406
2414 /* 2407 /*
2415 * Fill in skb descriptor 2408 * Fill in skb descriptor
2416 */ 2409 */
2417 desc = get_skb_desc(skb); 2410 skbdesc = get_skb_frame_desc(skb);
2418 desc->desc_len = ring->desc_size; 2411 memset(skbdesc, 0, sizeof(*skbdesc));
2419 desc->data_len = skb->len - ring->desc_size; 2412 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
2420 desc->desc = skb->data; 2413 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2421 desc->data = skb->data + ring->desc_size; 2414 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
2422 desc->ring = ring; 2415 skbdesc->desc = skb->data;
2423 desc->entry = entry; 2416 skbdesc->desc_len = intf->beacon->queue->desc_size;
2417 skbdesc->entry = intf->beacon;
2418
2419 /*
2420 * Disable beaconing while we are reloading the beacon data,
2421 * otherwise we might be sending out invalid data.
2422 */
2423 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
2424 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
2425 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
2426 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2427 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2424 2428
2429 /*
2430 * mac80211 doesn't provide the control->queue variable
2431 * for beacons. Set our own queue identification so
2432 * it can be used during descriptor initialization.
2433 */
2434 control->queue = RT2X00_BCN_QUEUE_BEACON;
2425 rt2x00lib_write_tx_desc(rt2x00dev, skb, control); 2435 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2426 2436
2427 /* 2437 /*
2428 * Write entire beacon with descriptor to register, 2438 * Write entire beacon with descriptor to register,
2429 * and kick the beacon generator. 2439 * and kick the beacon generator.
2430 */ 2440 */
2431 rt2x00pci_register_multiwrite(rt2x00dev, HW_BEACON_BASE0, 2441 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2442 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
2432 skb->data, skb->len); 2443 skb->data, skb->len);
2433 rt61pci_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON); 2444 rt61pci_kick_tx_queue(rt2x00dev, control->queue);
2434 2445
2435 return 0; 2446 return 0;
2436} 2447}
@@ -2450,7 +2461,6 @@ static const struct ieee80211_ops rt61pci_mac80211_ops = {
2450 .conf_tx = rt2x00mac_conf_tx, 2461 .conf_tx = rt2x00mac_conf_tx,
2451 .get_tx_stats = rt2x00mac_get_tx_stats, 2462 .get_tx_stats = rt2x00mac_get_tx_stats,
2452 .get_tsf = rt61pci_get_tsf, 2463 .get_tsf = rt61pci_get_tsf,
2453 .reset_tsf = rt61pci_reset_tsf,
2454 .beacon_update = rt61pci_beacon_update, 2464 .beacon_update = rt61pci_beacon_update,
2455}; 2465};
2456 2466
@@ -2458,6 +2468,7 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2458 .irq_handler = rt61pci_interrupt, 2468 .irq_handler = rt61pci_interrupt,
2459 .probe_hw = rt61pci_probe_hw, 2469 .probe_hw = rt61pci_probe_hw,
2460 .get_firmware_name = rt61pci_get_firmware_name, 2470 .get_firmware_name = rt61pci_get_firmware_name,
2471 .get_firmware_crc = rt61pci_get_firmware_crc,
2461 .load_firmware = rt61pci_load_firmware, 2472 .load_firmware = rt61pci_load_firmware,
2462 .initialize = rt2x00pci_initialize, 2473 .initialize = rt2x00pci_initialize,
2463 .uninitialize = rt2x00pci_uninitialize, 2474 .uninitialize = rt2x00pci_uninitialize,
@@ -2468,23 +2479,46 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2468 .link_stats = rt61pci_link_stats, 2479 .link_stats = rt61pci_link_stats,
2469 .reset_tuner = rt61pci_reset_tuner, 2480 .reset_tuner = rt61pci_reset_tuner,
2470 .link_tuner = rt61pci_link_tuner, 2481 .link_tuner = rt61pci_link_tuner,
2482 .led_brightness = rt61pci_led_brightness,
2471 .write_tx_desc = rt61pci_write_tx_desc, 2483 .write_tx_desc = rt61pci_write_tx_desc,
2472 .write_tx_data = rt2x00pci_write_tx_data, 2484 .write_tx_data = rt2x00pci_write_tx_data,
2473 .kick_tx_queue = rt61pci_kick_tx_queue, 2485 .kick_tx_queue = rt61pci_kick_tx_queue,
2474 .fill_rxdone = rt61pci_fill_rxdone, 2486 .fill_rxdone = rt61pci_fill_rxdone,
2475 .config_mac_addr = rt61pci_config_mac_addr, 2487 .config_intf = rt61pci_config_intf,
2476 .config_bssid = rt61pci_config_bssid, 2488 .config_erp = rt61pci_config_erp,
2477 .config_type = rt61pci_config_type,
2478 .config_preamble = rt61pci_config_preamble,
2479 .config = rt61pci_config, 2489 .config = rt61pci_config,
2480}; 2490};
2481 2491
2492static const struct data_queue_desc rt61pci_queue_rx = {
2493 .entry_num = RX_ENTRIES,
2494 .data_size = DATA_FRAME_SIZE,
2495 .desc_size = RXD_DESC_SIZE,
2496 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
2497};
2498
2499static const struct data_queue_desc rt61pci_queue_tx = {
2500 .entry_num = TX_ENTRIES,
2501 .data_size = DATA_FRAME_SIZE,
2502 .desc_size = TXD_DESC_SIZE,
2503 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2504};
2505
2506static const struct data_queue_desc rt61pci_queue_bcn = {
2507 .entry_num = 4 * BEACON_ENTRIES,
2508 .data_size = MGMT_FRAME_SIZE,
2509 .desc_size = TXINFO_SIZE,
2510 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2511};
2512
2482static const struct rt2x00_ops rt61pci_ops = { 2513static const struct rt2x00_ops rt61pci_ops = {
2483 .name = KBUILD_MODNAME, 2514 .name = KBUILD_MODNAME,
2484 .rxd_size = RXD_DESC_SIZE, 2515 .max_sta_intf = 1,
2485 .txd_size = TXD_DESC_SIZE, 2516 .max_ap_intf = 4,
2486 .eeprom_size = EEPROM_SIZE, 2517 .eeprom_size = EEPROM_SIZE,
2487 .rf_size = RF_SIZE, 2518 .rf_size = RF_SIZE,
2519 .rx = &rt61pci_queue_rx,
2520 .tx = &rt61pci_queue_tx,
2521 .bcn = &rt61pci_queue_bcn,
2488 .lib = &rt61pci_rt2x00_ops, 2522 .lib = &rt61pci_rt2x00_ops,
2489 .hw = &rt61pci_mac80211_ops, 2523 .hw = &rt61pci_mac80211_ops,
2490#ifdef CONFIG_RT2X00_LIB_DEBUGFS 2524#ifdef CONFIG_RT2X00_LIB_DEBUGFS
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-27 01:57:02 -0500