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path: root/drivers/net/wireless/rt2x00/rt2400pci.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2400pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.c480
1 files changed, 282 insertions, 198 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c
index c69f85ed7669..1f49561d3ddc 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.c
+++ b/drivers/net/wireless/rt2x00/rt2400pci.c
@@ -1,5 +1,5 @@
1/* 1/*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com> 3 <http://rt2x00.serialmonkey.com>
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
@@ -243,53 +243,71 @@ static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
243#define rt2400pci_rfkill_poll NULL 243#define rt2400pci_rfkill_poll NULL
244#endif /* CONFIG_RT2400PCI_RFKILL */ 244#endif /* CONFIG_RT2400PCI_RFKILL */
245 245
246/* 246#ifdef CONFIG_RT2400PCI_LEDS
247 * Configuration handlers. 247static void rt2400pci_led_brightness(struct led_classdev *led_cdev,
248 */ 248 enum led_brightness brightness)
249static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
250 __le32 *mac)
251{ 249{
252 rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac, 250 struct rt2x00_led *led =
253 (2 * sizeof(__le32))); 251 container_of(led_cdev, struct rt2x00_led, led_dev);
254} 252 unsigned int enabled = brightness != LED_OFF;
253 unsigned int activity =
254 led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
255 u32 reg;
255 256
256static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev, 257 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
257 __le32 *bssid) 258
258{ 259 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
259 rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid, 260 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
260 (2 * sizeof(__le32))); 261 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled && activity);
262 }
263
264 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
261} 265}
266#else
267#define rt2400pci_led_brightness NULL
268#endif /* CONFIG_RT2400PCI_LEDS */
262 269
263static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, const int type, 270/*
264 const int tsf_sync) 271 * Configuration handlers.
272 */
273static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
274 struct rt2x00_intf *intf,
275 struct rt2x00intf_conf *conf,
276 const unsigned int flags)
265{ 277{
278 unsigned int bcn_preload;
266 u32 reg; 279 u32 reg;
267 280
268 rt2x00pci_register_write(rt2x00dev, CSR14, 0); 281 if (flags & CONFIG_UPDATE_TYPE) {
282 /*
283 * Enable beacon config
284 */
285 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
286 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
287 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
288 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
269 289
270 /* 290 /*
271 * Enable beacon config 291 * Enable synchronisation.
272 */ 292 */
273 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg); 293 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
274 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, 294 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
275 PREAMBLE + get_duration(IEEE80211_HEADER, 20)); 295 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
276 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg); 296 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
297 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
298 }
277 299
278 /* 300 if (flags & CONFIG_UPDATE_MAC)
279 * Enable synchronisation. 301 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
280 */ 302 conf->mac, sizeof(conf->mac));
281 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 303
282 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1); 304 if (flags & CONFIG_UPDATE_BSSID)
283 rt2x00_set_field32(&reg, CSR14_TBCN, (tsf_sync == TSF_SYNC_BEACON)); 305 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
284 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); 306 conf->bssid, sizeof(conf->bssid));
285 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
286 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
287} 307}
288 308
289static void rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev, 309static int rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
290 const int short_preamble, 310 struct rt2x00lib_erp *erp)
291 const int ack_timeout,
292 const int ack_consume_time)
293{ 311{
294 int preamble_mask; 312 int preamble_mask;
295 u32 reg; 313 u32 reg;
@@ -297,11 +315,13 @@ static void rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
297 /* 315 /*
298 * When short preamble is enabled, we should set bit 0x08 316 * When short preamble is enabled, we should set bit 0x08
299 */ 317 */
300 preamble_mask = short_preamble << 3; 318 preamble_mask = erp->short_preamble << 3;
301 319
302 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg); 320 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
303 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout); 321 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
304 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time); 322 erp->ack_timeout);
323 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
324 erp->ack_consume_time);
305 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); 325 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
306 326
307 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg); 327 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
@@ -327,6 +347,8 @@ static void rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
327 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84); 347 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
328 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110)); 348 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
329 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg); 349 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
350
351 return 0;
330} 352}
331 353
332static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev, 354static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
@@ -397,6 +419,13 @@ static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
397 u8 r1; 419 u8 r1;
398 u8 r4; 420 u8 r4;
399 421
422 /*
423 * We should never come here because rt2x00lib is supposed
424 * to catch this and send us the correct antenna explicitely.
425 */
426 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
427 ant->tx == ANTENNA_SW_DIVERSITY);
428
400 rt2400pci_bbp_read(rt2x00dev, 4, &r4); 429 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
401 rt2400pci_bbp_read(rt2x00dev, 1, &r1); 430 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
402 431
@@ -410,14 +439,8 @@ static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
410 case ANTENNA_A: 439 case ANTENNA_A:
411 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0); 440 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
412 break; 441 break;
413 case ANTENNA_SW_DIVERSITY:
414 /*
415 * NOTE: We should never come here because rt2x00lib is
416 * supposed to catch this and send us the correct antenna
417 * explicitely. However we are nog going to bug about this.
418 * Instead, just default to antenna B.
419 */
420 case ANTENNA_B: 442 case ANTENNA_B:
443 default:
421 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2); 444 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
422 break; 445 break;
423 } 446 }
@@ -432,14 +455,8 @@ static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
432 case ANTENNA_A: 455 case ANTENNA_A:
433 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0); 456 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
434 break; 457 break;
435 case ANTENNA_SW_DIVERSITY:
436 /*
437 * NOTE: We should never come here because rt2x00lib is
438 * supposed to catch this and send us the correct antenna
439 * explicitely. However we are nog going to bug about this.
440 * Instead, just default to antenna B.
441 */
442 case ANTENNA_B: 458 case ANTENNA_B:
459 default:
443 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2); 460 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
444 break; 461 break;
445 } 462 }
@@ -481,8 +498,8 @@ static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
481} 498}
482 499
483static void rt2400pci_config(struct rt2x00_dev *rt2x00dev, 500static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
484 const unsigned int flags, 501 struct rt2x00lib_conf *libconf,
485 struct rt2x00lib_conf *libconf) 502 const unsigned int flags)
486{ 503{
487 if (flags & CONFIG_UPDATE_PHYMODE) 504 if (flags & CONFIG_UPDATE_PHYMODE)
488 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates); 505 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
@@ -498,45 +515,17 @@ static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
498} 515}
499 516
500static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev, 517static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
501 struct ieee80211_tx_queue_params *params) 518 const int cw_min, const int cw_max)
502{ 519{
503 u32 reg; 520 u32 reg;
504 521
505 rt2x00pci_register_read(rt2x00dev, CSR11, &reg); 522 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
506 rt2x00_set_field32(&reg, CSR11_CWMIN, params->cw_min); 523 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
507 rt2x00_set_field32(&reg, CSR11_CWMAX, params->cw_max); 524 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
508 rt2x00pci_register_write(rt2x00dev, CSR11, reg); 525 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
509} 526}
510 527
511/* 528/*
512 * LED functions.
513 */
514static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
515{
516 u32 reg;
517
518 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
519
520 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
521 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
522 rt2x00_set_field32(&reg, LEDCSR_LINK,
523 (rt2x00dev->led_mode != LED_MODE_ASUS));
524 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY,
525 (rt2x00dev->led_mode != LED_MODE_TXRX_ACTIVITY));
526 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
527}
528
529static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
530{
531 u32 reg;
532
533 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
534 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
535 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
536 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
537}
538
539/*
540 * Link tuning 529 * Link tuning
541 */ 530 */
542static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev, 531static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
@@ -593,90 +582,94 @@ static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
593 * Initialization functions. 582 * Initialization functions.
594 */ 583 */
595static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev, 584static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
596 struct data_entry *entry) 585 struct queue_entry *entry)
597{ 586{
598 __le32 *rxd = entry->priv; 587 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
599 u32 word; 588 u32 word;
600 589
601 rt2x00_desc_read(rxd, 2, &word); 590 rt2x00_desc_read(priv_rx->desc, 2, &word);
602 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->ring->data_size); 591 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
603 rt2x00_desc_write(rxd, 2, word); 592 entry->queue->data_size);
593 rt2x00_desc_write(priv_rx->desc, 2, word);
604 594
605 rt2x00_desc_read(rxd, 1, &word); 595 rt2x00_desc_read(priv_rx->desc, 1, &word);
606 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, entry->data_dma); 596 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
607 rt2x00_desc_write(rxd, 1, word); 597 rt2x00_desc_write(priv_rx->desc, 1, word);
608 598
609 rt2x00_desc_read(rxd, 0, &word); 599 rt2x00_desc_read(priv_rx->desc, 0, &word);
610 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); 600 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
611 rt2x00_desc_write(rxd, 0, word); 601 rt2x00_desc_write(priv_rx->desc, 0, word);
612} 602}
613 603
614static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev, 604static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
615 struct data_entry *entry) 605 struct queue_entry *entry)
616{ 606{
617 __le32 *txd = entry->priv; 607 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
618 u32 word; 608 u32 word;
619 609
620 rt2x00_desc_read(txd, 1, &word); 610 rt2x00_desc_read(priv_tx->desc, 1, &word);
621 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, entry->data_dma); 611 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
622 rt2x00_desc_write(txd, 1, word); 612 rt2x00_desc_write(priv_tx->desc, 1, word);
623 613
624 rt2x00_desc_read(txd, 2, &word); 614 rt2x00_desc_read(priv_tx->desc, 2, &word);
625 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, entry->ring->data_size); 615 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
626 rt2x00_desc_write(txd, 2, word); 616 entry->queue->data_size);
617 rt2x00_desc_write(priv_tx->desc, 2, word);
627 618
628 rt2x00_desc_read(txd, 0, &word); 619 rt2x00_desc_read(priv_tx->desc, 0, &word);
629 rt2x00_set_field32(&word, TXD_W0_VALID, 0); 620 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
630 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); 621 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
631 rt2x00_desc_write(txd, 0, word); 622 rt2x00_desc_write(priv_tx->desc, 0, word);
632} 623}
633 624
634static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev) 625static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
635{ 626{
627 struct queue_entry_priv_pci_rx *priv_rx;
628 struct queue_entry_priv_pci_tx *priv_tx;
636 u32 reg; 629 u32 reg;
637 630
638 /* 631 /*
639 * Initialize registers. 632 * Initialize registers.
640 */ 633 */
641 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg); 634 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
642 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, 635 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
643 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size); 636 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
644 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, 637 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
645 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit); 638 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
646 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
647 rt2x00dev->bcn[1].stats.limit);
648 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
649 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
650 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); 639 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
651 640
641 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
652 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg); 642 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
653 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER, 643 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
654 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma); 644 priv_tx->desc_dma);
655 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); 645 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
656 646
647 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
657 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg); 648 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
658 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER, 649 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
659 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma); 650 priv_tx->desc_dma);
660 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); 651 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
661 652
653 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
662 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg); 654 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
663 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, 655 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
664 rt2x00dev->bcn[1].data_dma); 656 priv_tx->desc_dma);
665 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); 657 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
666 658
659 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
667 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg); 660 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
668 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, 661 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
669 rt2x00dev->bcn[0].data_dma); 662 priv_tx->desc_dma);
670 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); 663 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
671 664
672 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg); 665 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
673 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); 666 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
674 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit); 667 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
675 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); 668 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
676 669
670 priv_rx = rt2x00dev->rx->entries[0].priv_data;
677 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg); 671 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
678 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, 672 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma);
679 rt2x00dev->rx->data_dma);
680 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); 673 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
681 674
682 return 0; 675 return 0;
@@ -702,6 +695,11 @@ static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
702 (rt2x00dev->rx->data_size / 128)); 695 (rt2x00dev->rx->data_size / 128));
703 rt2x00pci_register_write(rt2x00dev, CSR9, reg); 696 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
704 697
698 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
699 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
700 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
701 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
702
705 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000); 703 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
706 704
707 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg); 705 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
@@ -795,19 +793,15 @@ continue_csr_init:
795 rt2400pci_bbp_write(rt2x00dev, 30, 0x21); 793 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
796 rt2400pci_bbp_write(rt2x00dev, 31, 0x00); 794 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
797 795
798 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
799 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 796 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
800 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); 797 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
801 798
802 if (eeprom != 0xffff && eeprom != 0x0000) { 799 if (eeprom != 0xffff && eeprom != 0x0000) {
803 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 800 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
804 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 801 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
805 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
806 reg_id, value);
807 rt2400pci_bbp_write(rt2x00dev, reg_id, value); 802 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
808 } 803 }
809 } 804 }
810 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
811 805
812 return 0; 806 return 0;
813} 807}
@@ -859,7 +853,7 @@ static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
859 /* 853 /*
860 * Initialize all registers. 854 * Initialize all registers.
861 */ 855 */
862 if (rt2400pci_init_rings(rt2x00dev) || 856 if (rt2400pci_init_queues(rt2x00dev) ||
863 rt2400pci_init_registers(rt2x00dev) || 857 rt2400pci_init_registers(rt2x00dev) ||
864 rt2400pci_init_bbp(rt2x00dev)) { 858 rt2400pci_init_bbp(rt2x00dev)) {
865 ERROR(rt2x00dev, "Register initialization failed.\n"); 859 ERROR(rt2x00dev, "Register initialization failed.\n");
@@ -871,11 +865,6 @@ static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
871 */ 865 */
872 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON); 866 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
873 867
874 /*
875 * Enable LED
876 */
877 rt2400pci_enable_led(rt2x00dev);
878
879 return 0; 868 return 0;
880} 869}
881 870
@@ -883,11 +872,6 @@ static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
883{ 872{
884 u32 reg; 873 u32 reg;
885 874
886 /*
887 * Disable LED
888 */
889 rt2400pci_disable_led(rt2x00dev);
890
891 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0); 875 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
892 876
893 /* 877 /*
@@ -986,10 +970,10 @@ static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
986 */ 970 */
987static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, 971static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
988 struct sk_buff *skb, 972 struct sk_buff *skb,
989 struct txdata_entry_desc *desc, 973 struct txentry_desc *txdesc,
990 struct ieee80211_tx_control *control) 974 struct ieee80211_tx_control *control)
991{ 975{
992 struct skb_desc *skbdesc = get_skb_desc(skb); 976 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
993 __le32 *txd = skbdesc->desc; 977 __le32 *txd = skbdesc->desc;
994 u32 word; 978 u32 word;
995 979
@@ -1001,19 +985,19 @@ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1001 rt2x00_desc_write(txd, 2, word); 985 rt2x00_desc_write(txd, 2, word);
1002 986
1003 rt2x00_desc_read(txd, 3, &word); 987 rt2x00_desc_read(txd, 3, &word);
1004 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal); 988 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1005 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5); 989 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1006 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1); 990 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1007 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service); 991 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1008 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6); 992 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1009 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1); 993 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1010 rt2x00_desc_write(txd, 3, word); 994 rt2x00_desc_write(txd, 3, word);
1011 995
1012 rt2x00_desc_read(txd, 4, &word); 996 rt2x00_desc_read(txd, 4, &word);
1013 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, desc->length_low); 997 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1014 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8); 998 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1015 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1); 999 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1016 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, desc->length_high); 1000 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1017 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7); 1001 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1018 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1); 1002 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1019 rt2x00_desc_write(txd, 4, word); 1003 rt2x00_desc_write(txd, 4, word);
@@ -1022,14 +1006,14 @@ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1022 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); 1006 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1023 rt2x00_set_field32(&word, TXD_W0_VALID, 1); 1007 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1024 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, 1008 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1025 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags)); 1009 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1026 rt2x00_set_field32(&word, TXD_W0_ACK, 1010 rt2x00_set_field32(&word, TXD_W0_ACK,
1027 test_bit(ENTRY_TXD_ACK, &desc->flags)); 1011 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1028 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, 1012 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1029 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags)); 1013 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1030 rt2x00_set_field32(&word, TXD_W0_RTS, 1014 rt2x00_set_field32(&word, TXD_W0_RTS,
1031 test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags)); 1015 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1032 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs); 1016 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1033 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1017 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1034 !!(control->flags & 1018 !!(control->flags &
1035 IEEE80211_TXCTL_LONG_RETRY_LIMIT)); 1019 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
@@ -1040,13 +1024,15 @@ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1040 * TX data initialization 1024 * TX data initialization
1041 */ 1025 */
1042static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, 1026static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1043 unsigned int queue) 1027 const unsigned int queue)
1044{ 1028{
1045 u32 reg; 1029 u32 reg;
1046 1030
1047 if (queue == IEEE80211_TX_QUEUE_BEACON) { 1031 if (queue == RT2X00_BCN_QUEUE_BEACON) {
1048 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 1032 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1049 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) { 1033 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1034 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1035 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1050 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1); 1036 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1051 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 1037 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1052 } 1038 }
@@ -1059,56 +1045,61 @@ static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1059 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1045 rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1060 (queue == IEEE80211_TX_QUEUE_DATA1)); 1046 (queue == IEEE80211_TX_QUEUE_DATA1));
1061 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1047 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1062 (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)); 1048 (queue == RT2X00_BCN_QUEUE_ATIM));
1063 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); 1049 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1064} 1050}
1065 1051
1066/* 1052/*
1067 * RX control handlers 1053 * RX control handlers
1068 */ 1054 */
1069static void rt2400pci_fill_rxdone(struct data_entry *entry, 1055static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1070 struct rxdata_entry_desc *desc) 1056 struct rxdone_entry_desc *rxdesc)
1071{ 1057{
1072 __le32 *rxd = entry->priv; 1058 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1073 u32 word0; 1059 u32 word0;
1074 u32 word2; 1060 u32 word2;
1061 u32 word3;
1075 1062
1076 rt2x00_desc_read(rxd, 0, &word0); 1063 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1077 rt2x00_desc_read(rxd, 2, &word2); 1064 rt2x00_desc_read(priv_rx->desc, 2, &word2);
1065 rt2x00_desc_read(priv_rx->desc, 3, &word3);
1078 1066
1079 desc->flags = 0; 1067 rxdesc->flags = 0;
1080 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1068 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1081 desc->flags |= RX_FLAG_FAILED_FCS_CRC; 1069 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1082 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) 1070 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1083 desc->flags |= RX_FLAG_FAILED_PLCP_CRC; 1071 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1084 1072
1085 /* 1073 /*
1086 * Obtain the status about this packet. 1074 * Obtain the status about this packet.
1075 * The signal is the PLCP value, and needs to be stripped
1076 * of the preamble bit (0x08).
1087 */ 1077 */
1088 desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL); 1078 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1089 desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) - 1079 rxdesc->signal_plcp = 1;
1090 entry->ring->rt2x00dev->rssi_offset; 1080 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1091 desc->ofdm = 0; 1081 entry->queue->rt2x00dev->rssi_offset;
1092 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); 1082 rxdesc->ofdm = 0;
1093 desc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS); 1083 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1084 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1094} 1085}
1095 1086
1096/* 1087/*
1097 * Interrupt functions. 1088 * Interrupt functions.
1098 */ 1089 */
1099static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue) 1090static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1091 const enum ieee80211_tx_queue queue_idx)
1100{ 1092{
1101 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue); 1093 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1102 struct data_entry *entry; 1094 struct queue_entry_priv_pci_tx *priv_tx;
1103 __le32 *txd; 1095 struct queue_entry *entry;
1096 struct txdone_entry_desc txdesc;
1104 u32 word; 1097 u32 word;
1105 int tx_status;
1106 int retry;
1107 1098
1108 while (!rt2x00_ring_empty(ring)) { 1099 while (!rt2x00queue_empty(queue)) {
1109 entry = rt2x00_get_data_entry_done(ring); 1100 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1110 txd = entry->priv; 1101 priv_tx = entry->priv_data;
1111 rt2x00_desc_read(txd, 0, &word); 1102 rt2x00_desc_read(priv_tx->desc, 0, &word);
1112 1103
1113 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 1104 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1114 !rt2x00_get_field32(word, TXD_W0_VALID)) 1105 !rt2x00_get_field32(word, TXD_W0_VALID))
@@ -1117,10 +1108,10 @@ static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1117 /* 1108 /*
1118 * Obtain the status about this packet. 1109 * Obtain the status about this packet.
1119 */ 1110 */
1120 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT); 1111 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1121 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); 1112 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1122 1113
1123 rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry); 1114 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1124 } 1115 }
1125} 1116}
1126 1117
@@ -1164,7 +1155,7 @@ static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1164 * 3 - Atim ring transmit done interrupt. 1155 * 3 - Atim ring transmit done interrupt.
1165 */ 1156 */
1166 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING)) 1157 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1167 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON); 1158 rt2400pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
1168 1159
1169 /* 1160 /*
1170 * 4 - Priority ring transmit done interrupt. 1161 * 4 - Priority ring transmit done interrupt.
@@ -1272,8 +1263,24 @@ static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1272 /* 1263 /*
1273 * Store led mode, for correct led behaviour. 1264 * Store led mode, for correct led behaviour.
1274 */ 1265 */
1275 rt2x00dev->led_mode = 1266#ifdef CONFIG_RT2400PCI_LEDS
1276 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE); 1267 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1268
1269 switch (value) {
1270 case LED_MODE_ASUS:
1271 case LED_MODE_ALPHA:
1272 case LED_MODE_DEFAULT:
1273 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1274 break;
1275 case LED_MODE_TXRX_ACTIVITY:
1276 rt2x00dev->led_flags =
1277 LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1278 break;
1279 case LED_MODE_SIGNAL_STRENGTH:
1280 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1281 break;
1282 }
1283#endif /* CONFIG_RT2400PCI_LEDS */
1277 1284
1278 /* 1285 /*
1279 * Detect if this device has an hardware controlled radio. 1286 * Detect if this device has an hardware controlled radio.
@@ -1343,8 +1350,8 @@ static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1343 /* 1350 /*
1344 * Initialize hw_mode information. 1351 * Initialize hw_mode information.
1345 */ 1352 */
1346 spec->num_modes = 1; 1353 spec->supported_bands = SUPPORT_BAND_2GHZ;
1347 spec->num_rates = 4; 1354 spec->supported_rates = SUPPORT_RATE_CCK;
1348 spec->tx_power_a = NULL; 1355 spec->tx_power_a = NULL;
1349 spec->tx_power_bg = txpower; 1356 spec->tx_power_bg = txpower;
1350 spec->tx_power_default = DEFAULT_TXPOWER; 1357 spec->tx_power_default = DEFAULT_TXPOWER;
@@ -1374,9 +1381,9 @@ static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1374 rt2400pci_probe_hw_mode(rt2x00dev); 1381 rt2400pci_probe_hw_mode(rt2x00dev);
1375 1382
1376 /* 1383 /*
1377 * This device requires the beacon ring 1384 * This device requires the atim queue
1378 */ 1385 */
1379 __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags); 1386 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1380 1387
1381 /* 1388 /*
1382 * Set the rssi offset. 1389 * Set the rssi offset.
@@ -1481,7 +1488,8 @@ static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1481 /* 1488 /*
1482 * Write configuration to register. 1489 * Write configuration to register.
1483 */ 1490 */
1484 rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params); 1491 rt2400pci_config_cw(rt2x00dev,
1492 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1485 1493
1486 return 0; 1494 return 0;
1487} 1495}
@@ -1500,12 +1508,58 @@ static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1500 return tsf; 1508 return tsf;
1501} 1509}
1502 1510
1503static void rt2400pci_reset_tsf(struct ieee80211_hw *hw) 1511static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1512 struct ieee80211_tx_control *control)
1504{ 1513{
1505 struct rt2x00_dev *rt2x00dev = hw->priv; 1514 struct rt2x00_dev *rt2x00dev = hw->priv;
1515 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1516 struct queue_entry_priv_pci_tx *priv_tx;
1517 struct skb_frame_desc *skbdesc;
1518 u32 reg;
1506 1519
1507 rt2x00pci_register_write(rt2x00dev, CSR16, 0); 1520 if (unlikely(!intf->beacon))
1508 rt2x00pci_register_write(rt2x00dev, CSR17, 0); 1521 return -ENOBUFS;
1522 priv_tx = intf->beacon->priv_data;
1523
1524 /*
1525 * Fill in skb descriptor
1526 */
1527 skbdesc = get_skb_frame_desc(skb);
1528 memset(skbdesc, 0, sizeof(*skbdesc));
1529 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1530 skbdesc->data = skb->data;
1531 skbdesc->data_len = skb->len;
1532 skbdesc->desc = priv_tx->desc;
1533 skbdesc->desc_len = intf->beacon->queue->desc_size;
1534 skbdesc->entry = intf->beacon;
1535
1536 /*
1537 * Disable beaconing while we are reloading the beacon data,
1538 * otherwise we might be sending out invalid data.
1539 */
1540 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1541 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1542 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1543 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1544 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1545
1546 /*
1547 * mac80211 doesn't provide the control->queue variable
1548 * for beacons. Set our own queue identification so
1549 * it can be used during descriptor initialization.
1550 */
1551 control->queue = RT2X00_BCN_QUEUE_BEACON;
1552 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1553
1554 /*
1555 * Enable beacon generation.
1556 * Write entire beacon with descriptor to register,
1557 * and kick the beacon generator.
1558 */
1559 memcpy(priv_tx->data, skb->data, skb->len);
1560 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1561
1562 return 0;
1509} 1563}
1510 1564
1511static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw) 1565static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
@@ -1532,8 +1586,7 @@ static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1532 .conf_tx = rt2400pci_conf_tx, 1586 .conf_tx = rt2400pci_conf_tx,
1533 .get_tx_stats = rt2x00mac_get_tx_stats, 1587 .get_tx_stats = rt2x00mac_get_tx_stats,
1534 .get_tsf = rt2400pci_get_tsf, 1588 .get_tsf = rt2400pci_get_tsf,
1535 .reset_tsf = rt2400pci_reset_tsf, 1589 .beacon_update = rt2400pci_beacon_update,
1536 .beacon_update = rt2x00pci_beacon_update,
1537 .tx_last_beacon = rt2400pci_tx_last_beacon, 1590 .tx_last_beacon = rt2400pci_tx_last_beacon,
1538}; 1591};
1539 1592
@@ -1549,23 +1602,54 @@ static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1549 .link_stats = rt2400pci_link_stats, 1602 .link_stats = rt2400pci_link_stats,
1550 .reset_tuner = rt2400pci_reset_tuner, 1603 .reset_tuner = rt2400pci_reset_tuner,
1551 .link_tuner = rt2400pci_link_tuner, 1604 .link_tuner = rt2400pci_link_tuner,
1605 .led_brightness = rt2400pci_led_brightness,
1552 .write_tx_desc = rt2400pci_write_tx_desc, 1606 .write_tx_desc = rt2400pci_write_tx_desc,
1553 .write_tx_data = rt2x00pci_write_tx_data, 1607 .write_tx_data = rt2x00pci_write_tx_data,
1554 .kick_tx_queue = rt2400pci_kick_tx_queue, 1608 .kick_tx_queue = rt2400pci_kick_tx_queue,
1555 .fill_rxdone = rt2400pci_fill_rxdone, 1609 .fill_rxdone = rt2400pci_fill_rxdone,
1556 .config_mac_addr = rt2400pci_config_mac_addr, 1610 .config_intf = rt2400pci_config_intf,
1557 .config_bssid = rt2400pci_config_bssid, 1611 .config_erp = rt2400pci_config_erp,
1558 .config_type = rt2400pci_config_type,
1559 .config_preamble = rt2400pci_config_preamble,
1560 .config = rt2400pci_config, 1612 .config = rt2400pci_config,
1561}; 1613};
1562 1614
1615static const struct data_queue_desc rt2400pci_queue_rx = {
1616 .entry_num = RX_ENTRIES,
1617 .data_size = DATA_FRAME_SIZE,
1618 .desc_size = RXD_DESC_SIZE,
1619 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
1620};
1621
1622static const struct data_queue_desc rt2400pci_queue_tx = {
1623 .entry_num = TX_ENTRIES,
1624 .data_size = DATA_FRAME_SIZE,
1625 .desc_size = TXD_DESC_SIZE,
1626 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1627};
1628
1629static const struct data_queue_desc rt2400pci_queue_bcn = {
1630 .entry_num = BEACON_ENTRIES,
1631 .data_size = MGMT_FRAME_SIZE,
1632 .desc_size = TXD_DESC_SIZE,
1633 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1634};
1635
1636static const struct data_queue_desc rt2400pci_queue_atim = {
1637 .entry_num = ATIM_ENTRIES,
1638 .data_size = DATA_FRAME_SIZE,
1639 .desc_size = TXD_DESC_SIZE,
1640 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1641};
1642
1563static const struct rt2x00_ops rt2400pci_ops = { 1643static const struct rt2x00_ops rt2400pci_ops = {
1564 .name = KBUILD_MODNAME, 1644 .name = KBUILD_MODNAME,
1565 .rxd_size = RXD_DESC_SIZE, 1645 .max_sta_intf = 1,
1566 .txd_size = TXD_DESC_SIZE, 1646 .max_ap_intf = 1,
1567 .eeprom_size = EEPROM_SIZE, 1647 .eeprom_size = EEPROM_SIZE,
1568 .rf_size = RF_SIZE, 1648 .rf_size = RF_SIZE,
1649 .rx = &rt2400pci_queue_rx,
1650 .tx = &rt2400pci_queue_tx,
1651 .bcn = &rt2400pci_queue_bcn,
1652 .atim = &rt2400pci_queue_atim,
1569 .lib = &rt2400pci_rt2x00_ops, 1653 .lib = &rt2400pci_rt2x00_ops,
1570 .hw = &rt2400pci_mac80211_ops, 1654 .hw = &rt2400pci_mac80211_ops,
1571#ifdef CONFIG_RT2X00_LIB_DEBUGFS 1655#ifdef CONFIG_RT2X00_LIB_DEBUGFS
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 15:51:26 -0500