1 files changed, 250 insertions, 25 deletions

diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index dbbf7ca5f97d..77245dff5993 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2010 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -41,18 +41,16 @@
 #define AR9280_DEVID_PCIE       0x002a
 #define AR9285_DEVID_PCIE       0x002b
 #define AR2427_DEVID_PCIE       0x002c
+#define AR9287_DEVID_PCI        0x002d
+#define AR9287_DEVID_PCIE       0x002e
+#define AR9300_DEVID_PCIE       0x0030
 
 #define AR5416_AR9100_DEVID     0x000b
 
-#define AR9271_USB             0x9271
-
 #define AR_SUBVENDOR_ID_NOG     0x0e11
 #define AR_SUBVENDOR_ID_NEW_A   0x7065
 #define AR5416_MAGIC            0x19641014
 
-#define AR5416_DEVID_AR9287_PCI  0x002D
-#define AR5416_DEVID_AR9287_PCIE 0x002E
-
 #define AR9280_COEX2WIRE_SUBSYSID       0x309b
 #define AT9285_COEX3WIRE_SA_SUBSYSID    0x30aa
 #define AT9285_COEX3WIRE_DA_SUBSYSID    0x30ab
@@ -70,6 +68,24 @@
 #define REG_READ(_ah, _reg) \
         ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
 
+#define ENABLE_REGWRITE_BUFFER(_ah)                                     \
+        do {                                                            \
+                if (AR_SREV_9271(_ah))                                  \
+                        ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
+        } while (0)
+
+#define DISABLE_REGWRITE_BUFFER(_ah)                                    \
+        do {                                                            \
+                if (AR_SREV_9271(_ah))                                  \
+                        ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \
+        } while (0)
+
+#define REGWRITE_BUFFER_FLUSH(_ah)                                      \
+        do {                                                            \
+                if (AR_SREV_9271(_ah))                                  \
+                        ath9k_hw_common(_ah)->ops->write_flush((_ah));  \
+        } while (0)
+
 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
 #define REG_RMW(_a, _r, _set, _clr)    \
@@ -77,6 +93,8 @@
 #define REG_RMW_FIELD(_a, _r, _f, _v) \
         REG_WRITE(_a, _r, \
         (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
+#define REG_READ_FIELD(_a, _r, _f) \
+        (((REG_READ(_a, _r) & _f) >> _f##_S))
 #define REG_SET_BIT(_a, _r, _f) \
         REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
 #define REG_CLR_BIT(_a, _r, _f) \
@@ -137,6 +155,16 @@
 
 #define TU_TO_USEC(_tu)             ((_tu) << 10)
 
+#define ATH9K_HW_RX_HP_QDEPTH   16
+#define ATH9K_HW_RX_LP_QDEPTH   128
+
+enum ath_ini_subsys {
+        ATH_INI_PRE = 0,
+        ATH_INI_CORE,
+        ATH_INI_POST,
+        ATH_INI_NUM_SPLIT,
+};
+
 enum wireless_mode {
         ATH9K_MODE_11A = 0,
         ATH9K_MODE_11G,
@@ -167,13 +195,16 @@ enum ath9k_hw_caps {
         ATH9K_HW_CAP_ENHANCEDPM                 = BIT(14),
         ATH9K_HW_CAP_AUTOSLEEP                  = BIT(15),
         ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(16),
+        ATH9K_HW_CAP_EDMA                       = BIT(17),
+        ATH9K_HW_CAP_RAC_SUPPORTED              = BIT(18),
+        ATH9K_HW_CAP_LDPC                       = BIT(19),
+        ATH9K_HW_CAP_FASTCLOCK                  = BIT(20),
 };
 
 enum ath9k_capability_type {
         ATH9K_CAP_CIPHER = 0,
         ATH9K_CAP_TKIP_MIC,
         ATH9K_CAP_TKIP_SPLIT,
-        ATH9K_CAP_DIVERSITY,
         ATH9K_CAP_TXPOW,
         ATH9K_CAP_MCAST_KEYSRCH,
         ATH9K_CAP_DS
@@ -194,6 +225,11 @@ struct ath9k_hw_capabilities {
         u8 num_gpio_pins;
         u8 num_antcfg_2ghz;
         u8 num_antcfg_5ghz;
+        u8 rx_hp_qdepth;
+        u8 rx_lp_qdepth;
+        u8 rx_status_len;
+        u8 tx_desc_len;
+        u8 txs_len;
 };
 
 struct ath9k_ops_config {
@@ -214,6 +250,7 @@ struct ath9k_ops_config {
         u32 enable_ani;
         int serialize_regmode;
         bool rx_intr_mitigation;
+        bool tx_intr_mitigation;
 #define SPUR_DISABLE            0
 #define SPUR_ENABLE_IOCTL       1
 #define SPUR_ENABLE_EEPROM      2
@@ -225,6 +262,7 @@ struct ath9k_ops_config {
 #define AR_BASE_FREQ_5GHZ       4900
 #define AR_SPUR_FEEQ_BOUND_HT40 19
 #define AR_SPUR_FEEQ_BOUND_HT20 10
+        bool tx_iq_calibration; /* Only available for >= AR9003 */
         int spurmode;
         u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
         u8 max_txtrig_level;
@@ -233,6 +271,8 @@ struct ath9k_ops_config {
 enum ath9k_int {
         ATH9K_INT_RX = 0x00000001,
         ATH9K_INT_RXDESC = 0x00000002,
+        ATH9K_INT_RXHP = 0x00000001,
+        ATH9K_INT_RXLP = 0x00000002,
         ATH9K_INT_RXNOFRM = 0x00000008,
         ATH9K_INT_RXEOL = 0x00000010,
         ATH9K_INT_RXORN = 0x00000020,
@@ -329,10 +369,9 @@ struct ath9k_channel {
 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
-#define IS_CHAN_A_5MHZ_SPACED(_c)                       \
+#define IS_CHAN_A_FAST_CLOCK(_ah, _c)                   \
         ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) &&  \
-         (((_c)->channel % 20) != 0) &&                 \
-         (((_c)->channel % 10) != 0))
+         ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
 
 /* These macros check chanmode and not channelFlags */
 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
@@ -365,6 +404,12 @@ enum ser_reg_mode {
         SER_REG_MODE_AUTO = 2,
 };
 
+enum ath9k_rx_qtype {
+        ATH9K_RX_QUEUE_HP,
+        ATH9K_RX_QUEUE_LP,
+        ATH9K_RX_QUEUE_MAX,
+};
+
 struct ath9k_beacon_state {
         u32 bs_nexttbtt;
         u32 bs_nextdtim;
@@ -442,6 +487,124 @@ struct ath_gen_timer_table {
         } timer_mask;
 };
 
+/**
+ * struct ath_hw_private_ops - callbacks used internally by hardware code
+ *
+ * This structure contains private callbacks designed to only be used internally
+ * by the hardware core.
+ *
+ * @init_cal_settings: setup types of calibrations supported
+ * @init_cal: starts actual calibration
+ *
+ * @init_mode_regs: Initializes mode registers
+ * @init_mode_gain_regs: Initialize TX/RX gain registers
+ * @macversion_supported: If this specific mac revision is supported
+ *
+ * @rf_set_freq: change frequency
+ * @spur_mitigate_freq: spur mitigation
+ * @rf_alloc_ext_banks:
+ * @rf_free_ext_banks:
+ * @set_rf_regs:
+ * @compute_pll_control: compute the PLL control value to use for
+ *      AR_RTC_PLL_CONTROL for a given channel
+ * @setup_calibration: set up calibration
+ * @iscal_supported: used to query if a type of calibration is supported
+ * @loadnf: load noise floor read from each chain on the CCA registers
+ */
+struct ath_hw_private_ops {
+        /* Calibration ops */
+        void (*init_cal_settings)(struct ath_hw *ah);
+        bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
+
+        void (*init_mode_regs)(struct ath_hw *ah);
+        void (*init_mode_gain_regs)(struct ath_hw *ah);
+        bool (*macversion_supported)(u32 macversion);
+        void (*setup_calibration)(struct ath_hw *ah,
+                                  struct ath9k_cal_list *currCal);
+        bool (*iscal_supported)(struct ath_hw *ah,
+                                enum ath9k_cal_types calType);
+
+        /* PHY ops */
+        int (*rf_set_freq)(struct ath_hw *ah,
+                           struct ath9k_channel *chan);
+        void (*spur_mitigate_freq)(struct ath_hw *ah,
+                                   struct ath9k_channel *chan);
+        int (*rf_alloc_ext_banks)(struct ath_hw *ah);
+        void (*rf_free_ext_banks)(struct ath_hw *ah);
+        bool (*set_rf_regs)(struct ath_hw *ah,
+                            struct ath9k_channel *chan,
+                            u16 modesIndex);
+        void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
+        void (*init_bb)(struct ath_hw *ah,
+                        struct ath9k_channel *chan);
+        int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
+        void (*olc_init)(struct ath_hw *ah);
+        void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
+        void (*mark_phy_inactive)(struct ath_hw *ah);
+        void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
+        bool (*rfbus_req)(struct ath_hw *ah);
+        void (*rfbus_done)(struct ath_hw *ah);
+        void (*enable_rfkill)(struct ath_hw *ah);
+        void (*restore_chainmask)(struct ath_hw *ah);
+        void (*set_diversity)(struct ath_hw *ah, bool value);
+        u32 (*compute_pll_control)(struct ath_hw *ah,
+                                   struct ath9k_channel *chan);
+        bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
+                            int param);
+        void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
+        void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
+};
+
+/**
+ * struct ath_hw_ops - callbacks used by hardware code and driver code
+ *
+ * This structure contains callbacks designed to to be used internally by
+ * hardware code and also by the lower level driver.
+ *
+ * @config_pci_powersave:
+ * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
+ */
+struct ath_hw_ops {
+        void (*config_pci_powersave)(struct ath_hw *ah,
+                                     int restore,
+                                     int power_off);
+        void (*rx_enable)(struct ath_hw *ah);
+        void (*set_desc_link)(void *ds, u32 link);
+        void (*get_desc_link)(void *ds, u32 **link);
+        bool (*calibrate)(struct ath_hw *ah,
+                          struct ath9k_channel *chan,
+                          u8 rxchainmask,
+                          bool longcal);
+        bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
+        void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
+                            bool is_firstseg, bool is_is_lastseg,
+                            const void *ds0, dma_addr_t buf_addr,
+                            unsigned int qcu);
+        int (*proc_txdesc)(struct ath_hw *ah, void *ds,
+                           struct ath_tx_status *ts);
+        void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
+                              u32 pktLen, enum ath9k_pkt_type type,
+                              u32 txPower, u32 keyIx,
+                              enum ath9k_key_type keyType,
+                              u32 flags);
+        void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
+                                void *lastds,
+                                u32 durUpdateEn, u32 rtsctsRate,
+                                u32 rtsctsDuration,
+                                struct ath9k_11n_rate_series series[],
+                                u32 nseries, u32 flags);
+        void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
+                                  u32 aggrLen);
+        void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
+                                   u32 numDelims);
+        void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
+        void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
+        void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
+                                     u32 burstDuration);
+        void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
+                                       u32 vmf);
+};
+
 struct ath_hw {
         struct ieee80211_hw *hw;
         struct ath_common common;
@@ -455,13 +618,18 @@ struct ath_hw {
                 struct ar5416_eeprom_def def;
                 struct ar5416_eeprom_4k map4k;
                 struct ar9287_eeprom map9287;
+                struct ar9300_eeprom ar9300_eep;
         } eeprom;
         const struct eeprom_ops *eep_ops;
-        enum ath9k_eep_map eep_map;
 
         bool sw_mgmt_crypto;
         bool is_pciexpress;
+        bool need_an_top2_fixup;
         u16 tx_trig_level;
+        s16 nf_2g_max;
+        s16 nf_2g_min;
+        s16 nf_5g_max;
+        s16 nf_5g_min;
         u16 rfsilent;
         u32 rfkill_gpio;
         u32 rfkill_polarity;
@@ -478,7 +646,8 @@ struct ath_hw {
         struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
 
         int16_t curchan_rad_index;
-        u32 mask_reg;
+        enum ath9k_int imask;
+        u32 imrs2_reg;
         u32 txok_interrupt_mask;
         u32 txerr_interrupt_mask;
         u32 txdesc_interrupt_mask;
@@ -493,6 +662,7 @@ struct ath_hw {
         struct ath9k_cal_list adcgain_caldata;
         struct ath9k_cal_list adcdc_calinitdata;
         struct ath9k_cal_list adcdc_caldata;
+        struct ath9k_cal_list tempCompCalData;
         struct ath9k_cal_list *cal_list;
         struct ath9k_cal_list *cal_list_last;
         struct ath9k_cal_list *cal_list_curr;
@@ -533,12 +703,10 @@ struct ath_hw {
                 DONT_USE_32KHZ,
         } enable_32kHz_clock;
 
-        /* Callback for radio frequency change */
-        int (*ath9k_hw_rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan);
-
-        /* Callback for baseband spur frequency */
-        void (*ath9k_hw_spur_mitigate_freq)(struct ath_hw *ah,
-                                            struct ath9k_channel *chan);
+        /* Private to hardware code */
+        struct ath_hw_private_ops private_ops;
+        /* Accessed by the lower level driver */
+        struct ath_hw_ops ops;
 
         /* Used to program the radio on non single-chip devices */
         u32 *analogBank0Data;
@@ -551,6 +719,7 @@ struct ath_hw {
         u32 *addac5416_21;
         u32 *bank6Temp;
 
+        u8 txpower_limit;
         int16_t txpower_indexoffset;
         int coverage_class;
         u32 beacon_interval;
@@ -592,16 +761,34 @@ struct ath_hw {
         struct ar5416IniArray iniBank7;
         struct ar5416IniArray iniAddac;
         struct ar5416IniArray iniPcieSerdes;
+        struct ar5416IniArray iniPcieSerdesLowPower;
         struct ar5416IniArray iniModesAdditional;
         struct ar5416IniArray iniModesRxGain;
         struct ar5416IniArray iniModesTxGain;
         struct ar5416IniArray iniModes_9271_1_0_only;
         struct ar5416IniArray iniCckfirNormal;
         struct ar5416IniArray iniCckfirJapan2484;
+        struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
+        struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
+        struct ar5416IniArray iniModes_9271_ANI_reg;
+        struct ar5416IniArray iniModes_high_power_tx_gain_9271;
+        struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
+
+        struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
+        struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
+        struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
+        struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
 
         u32 intr_gen_timer_trigger;
         u32 intr_gen_timer_thresh;
         struct ath_gen_timer_table hw_gen_timers;
+
+        struct ar9003_txs *ts_ring;
+        void *ts_start;
+        u32 ts_paddr_start;
+        u32 ts_paddr_end;
+        u16 ts_tail;
+        u8 ts_size;
 };
 
 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
@@ -614,6 +801,16 @@ static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
         return &(ath9k_hw_common(ah)->regulatory);
 }
 
+static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
+{
+        return &ah->private_ops;
+}
+
+static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
+{
+        return &ah->ops;
+}
+
 /* Initialization, Detach, Reset */
 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
 void ath9k_hw_deinit(struct ath_hw *ah);
@@ -625,6 +822,7 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
                             u32 capability, u32 *result);
 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
                             u32 capability, u32 setting, int *status);
+u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
 
 /* Key Cache Management */
 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
@@ -673,16 +871,10 @@ void ath9k_hw_set11nmac2040(struct ath_hw *ah);
 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
                                     const struct ath9k_beacon_state *bs);
+bool ath9k_hw_check_alive(struct ath_hw *ah);
 
 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
 
-void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
-
-/* Interrupt Handling */
-bool ath9k_hw_intrpend(struct ath_hw *ah);
-bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
-enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
-
 /* Generic hw timer primitives */
 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
                                           void (*trigger)(void *),
@@ -701,6 +893,39 @@ u32 ath9k_hw_gettsf32(struct ath_hw *ah);
 
 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
 
+/* HTC */
+void ath9k_hw_htc_resetinit(struct ath_hw *ah);
+
+/* PHY */
+void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
+                                   u32 *coef_mantissa, u32 *coef_exponent);
+
+/*
+ * Code Specific to AR5008, AR9001 or AR9002,
+ * we stuff these here to avoid callbacks for AR9003.
+ */
+void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
+int ar9002_hw_rf_claim(struct ath_hw *ah);
+void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
+void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
+
+/*
+ * Code specifric to AR9003, we stuff these here to avoid callbacks
+ * for older families
+ */
+void ar9003_hw_set_nf_limits(struct ath_hw *ah);
+
+/* Hardware family op attach helpers */
+void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
+void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
+void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
+
+void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
+void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
+
+void ar9002_hw_attach_ops(struct ath_hw *ah);
+void ar9003_hw_attach_ops(struct ath_hw *ah);
+
 #define ATH_PCIE_CAP_LINK_CTRL  0x70
 #define ATH_PCIE_CAP_LINK_L0S   1
 #define ATH_PCIE_CAP_LINK_L1    2