diff options
Diffstat (limited to 'drivers/net/netxen/netxen_nic_ethtool.c')
-rw-r--r-- | drivers/net/netxen/netxen_nic_ethtool.c | 193 |
1 files changed, 67 insertions, 126 deletions
diff --git a/drivers/net/netxen/netxen_nic_ethtool.c b/drivers/net/netxen/netxen_nic_ethtool.c index ddd704ae0188..542f408333ff 100644 --- a/drivers/net/netxen/netxen_nic_ethtool.c +++ b/drivers/net/netxen/netxen_nic_ethtool.c | |||
@@ -66,7 +66,7 @@ static const char netxen_nic_gstrings_test[][ETH_GSTRING_LEN] = { | |||
66 | 66 | ||
67 | #define NETXEN_NIC_TEST_LEN ARRAY_SIZE(netxen_nic_gstrings_test) | 67 | #define NETXEN_NIC_TEST_LEN ARRAY_SIZE(netxen_nic_gstrings_test) |
68 | 68 | ||
69 | #define NETXEN_NIC_REGS_COUNT 42 | 69 | #define NETXEN_NIC_REGS_COUNT 30 |
70 | #define NETXEN_NIC_REGS_LEN (NETXEN_NIC_REGS_COUNT * sizeof(__le32)) | 70 | #define NETXEN_NIC_REGS_LEN (NETXEN_NIC_REGS_COUNT * sizeof(__le32)) |
71 | #define NETXEN_MAX_EEPROM_LEN 1024 | 71 | #define NETXEN_MAX_EEPROM_LEN 1024 |
72 | 72 | ||
@@ -312,150 +312,91 @@ static int netxen_nic_get_regs_len(struct net_device *dev) | |||
312 | return NETXEN_NIC_REGS_LEN; | 312 | return NETXEN_NIC_REGS_LEN; |
313 | } | 313 | } |
314 | 314 | ||
315 | struct netxen_niu_regs { | ||
316 | __u32 reg[NETXEN_NIC_REGS_COUNT]; | ||
317 | }; | ||
318 | |||
319 | static struct netxen_niu_regs niu_registers[] = { | ||
320 | { | ||
321 | /* GB Mode */ | ||
322 | { | ||
323 | NETXEN_NIU_GB_SERDES_RESET, | ||
324 | NETXEN_NIU_GB0_MII_MODE, | ||
325 | NETXEN_NIU_GB1_MII_MODE, | ||
326 | NETXEN_NIU_GB2_MII_MODE, | ||
327 | NETXEN_NIU_GB3_MII_MODE, | ||
328 | NETXEN_NIU_GB0_GMII_MODE, | ||
329 | NETXEN_NIU_GB1_GMII_MODE, | ||
330 | NETXEN_NIU_GB2_GMII_MODE, | ||
331 | NETXEN_NIU_GB3_GMII_MODE, | ||
332 | NETXEN_NIU_REMOTE_LOOPBACK, | ||
333 | NETXEN_NIU_GB0_HALF_DUPLEX, | ||
334 | NETXEN_NIU_GB1_HALF_DUPLEX, | ||
335 | NETXEN_NIU_RESET_SYS_FIFOS, | ||
336 | NETXEN_NIU_GB_CRC_DROP, | ||
337 | NETXEN_NIU_GB_DROP_WRONGADDR, | ||
338 | NETXEN_NIU_TEST_MUX_CTL, | ||
339 | |||
340 | NETXEN_NIU_GB_MAC_CONFIG_0(0), | ||
341 | NETXEN_NIU_GB_MAC_CONFIG_1(0), | ||
342 | NETXEN_NIU_GB_HALF_DUPLEX_CTRL(0), | ||
343 | NETXEN_NIU_GB_MAX_FRAME_SIZE(0), | ||
344 | NETXEN_NIU_GB_TEST_REG(0), | ||
345 | NETXEN_NIU_GB_MII_MGMT_CONFIG(0), | ||
346 | NETXEN_NIU_GB_MII_MGMT_COMMAND(0), | ||
347 | NETXEN_NIU_GB_MII_MGMT_ADDR(0), | ||
348 | NETXEN_NIU_GB_MII_MGMT_CTRL(0), | ||
349 | NETXEN_NIU_GB_MII_MGMT_STATUS(0), | ||
350 | NETXEN_NIU_GB_MII_MGMT_INDICATE(0), | ||
351 | NETXEN_NIU_GB_INTERFACE_CTRL(0), | ||
352 | NETXEN_NIU_GB_INTERFACE_STATUS(0), | ||
353 | NETXEN_NIU_GB_STATION_ADDR_0(0), | ||
354 | NETXEN_NIU_GB_STATION_ADDR_1(0), | ||
355 | -1, | ||
356 | } | ||
357 | }, | ||
358 | { | ||
359 | /* XG Mode */ | ||
360 | { | ||
361 | NETXEN_NIU_XG_SINGLE_TERM, | ||
362 | NETXEN_NIU_XG_DRIVE_HI, | ||
363 | NETXEN_NIU_XG_DRIVE_LO, | ||
364 | NETXEN_NIU_XG_DTX, | ||
365 | NETXEN_NIU_XG_DEQ, | ||
366 | NETXEN_NIU_XG_WORD_ALIGN, | ||
367 | NETXEN_NIU_XG_RESET, | ||
368 | NETXEN_NIU_XG_POWER_DOWN, | ||
369 | NETXEN_NIU_XG_RESET_PLL, | ||
370 | NETXEN_NIU_XG_SERDES_LOOPBACK, | ||
371 | NETXEN_NIU_XG_DO_BYTE_ALIGN, | ||
372 | NETXEN_NIU_XG_TX_ENABLE, | ||
373 | NETXEN_NIU_XG_RX_ENABLE, | ||
374 | NETXEN_NIU_XG_STATUS, | ||
375 | NETXEN_NIU_XG_PAUSE_THRESHOLD, | ||
376 | NETXEN_NIU_XGE_CONFIG_0, | ||
377 | NETXEN_NIU_XGE_CONFIG_1, | ||
378 | NETXEN_NIU_XGE_IPG, | ||
379 | NETXEN_NIU_XGE_STATION_ADDR_0_HI, | ||
380 | NETXEN_NIU_XGE_STATION_ADDR_0_1, | ||
381 | NETXEN_NIU_XGE_STATION_ADDR_1_LO, | ||
382 | NETXEN_NIU_XGE_STATUS, | ||
383 | NETXEN_NIU_XGE_MAX_FRAME_SIZE, | ||
384 | NETXEN_NIU_XGE_PAUSE_FRAME_VALUE, | ||
385 | NETXEN_NIU_XGE_TX_BYTE_CNT, | ||
386 | NETXEN_NIU_XGE_TX_FRAME_CNT, | ||
387 | NETXEN_NIU_XGE_RX_BYTE_CNT, | ||
388 | NETXEN_NIU_XGE_RX_FRAME_CNT, | ||
389 | NETXEN_NIU_XGE_AGGR_ERROR_CNT, | ||
390 | NETXEN_NIU_XGE_MULTICAST_FRAME_CNT, | ||
391 | NETXEN_NIU_XGE_UNICAST_FRAME_CNT, | ||
392 | NETXEN_NIU_XGE_CRC_ERROR_CNT, | ||
393 | NETXEN_NIU_XGE_OVERSIZE_FRAME_ERR, | ||
394 | NETXEN_NIU_XGE_UNDERSIZE_FRAME_ERR, | ||
395 | NETXEN_NIU_XGE_LOCAL_ERROR_CNT, | ||
396 | NETXEN_NIU_XGE_REMOTE_ERROR_CNT, | ||
397 | NETXEN_NIU_XGE_CONTROL_CHAR_CNT, | ||
398 | NETXEN_NIU_XGE_PAUSE_FRAME_CNT, | ||
399 | -1, | ||
400 | } | ||
401 | } | ||
402 | }; | ||
403 | |||
404 | static void | 315 | static void |
405 | netxen_nic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p) | 316 | netxen_nic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p) |
406 | { | 317 | { |
407 | struct netxen_adapter *adapter = netdev_priv(dev); | 318 | struct netxen_adapter *adapter = netdev_priv(dev); |
408 | __u32 mode, *regs_buff = p; | 319 | struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; |
409 | int i, window; | 320 | struct nx_host_sds_ring *sds_ring; |
321 | u32 *regs_buff = p; | ||
322 | int ring, i = 0; | ||
323 | int port = adapter->physical_port; | ||
410 | 324 | ||
411 | memset(p, 0, NETXEN_NIC_REGS_LEN); | 325 | memset(p, 0, NETXEN_NIC_REGS_LEN); |
326 | |||
412 | regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) | | 327 | regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) | |
413 | (adapter->pdev)->device; | 328 | (adapter->pdev)->device; |
414 | /* which mode */ | ||
415 | regs_buff[0] = NXRD32(adapter, NETXEN_NIU_MODE); | ||
416 | mode = regs_buff[0]; | ||
417 | |||
418 | /* Common registers to all the modes */ | ||
419 | regs_buff[2] = NXRD32(adapter, NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER); | ||
420 | /* GB/XGB Mode */ | ||
421 | mode = (mode / 2) - 1; | ||
422 | window = 0; | ||
423 | if (mode <= 1) { | ||
424 | for (i = 3; niu_registers[mode].reg[i - 3] != -1; i++) { | ||
425 | /* GB: port specific registers */ | ||
426 | if (mode == 0 && i >= 19) | ||
427 | window = adapter->physical_port * | ||
428 | NETXEN_NIC_PORT_WINDOW; | ||
429 | |||
430 | regs_buff[i] = NXRD32(adapter, | ||
431 | niu_registers[mode].reg[i - 3] + window); | ||
432 | } | ||
433 | 329 | ||
330 | if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) | ||
331 | return; | ||
332 | |||
333 | regs_buff[i++] = NXRD32(adapter, CRB_CMDPEG_STATE); | ||
334 | regs_buff[i++] = NXRD32(adapter, CRB_RCVPEG_STATE); | ||
335 | regs_buff[i++] = NXRD32(adapter, CRB_FW_CAPABILITIES_1); | ||
336 | regs_buff[i++] = NXRDIO(adapter, adapter->crb_int_state_reg); | ||
337 | regs_buff[i++] = NXRD32(adapter, NX_CRB_DEV_REF_COUNT); | ||
338 | regs_buff[i++] = NXRD32(adapter, NX_CRB_DEV_STATE); | ||
339 | regs_buff[i++] = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER); | ||
340 | regs_buff[i++] = NXRD32(adapter, NETXEN_PEG_HALT_STATUS1); | ||
341 | regs_buff[i++] = NXRD32(adapter, NETXEN_PEG_HALT_STATUS2); | ||
342 | |||
343 | regs_buff[i++] = NXRD32(adapter, NETXEN_CRB_PEG_NET_0+0x3c); | ||
344 | regs_buff[i++] = NXRD32(adapter, NETXEN_CRB_PEG_NET_1+0x3c); | ||
345 | regs_buff[i++] = NXRD32(adapter, NETXEN_CRB_PEG_NET_2+0x3c); | ||
346 | regs_buff[i++] = NXRD32(adapter, NETXEN_CRB_PEG_NET_3+0x3c); | ||
347 | |||
348 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { | ||
349 | |||
350 | regs_buff[i++] = NXRD32(adapter, NETXEN_CRB_PEG_NET_4+0x3c); | ||
351 | i += 2; | ||
352 | |||
353 | regs_buff[i++] = NXRD32(adapter, CRB_XG_STATE_P3); | ||
354 | regs_buff[i++] = le32_to_cpu(*(adapter->tx_ring->hw_consumer)); | ||
355 | |||
356 | } else { | ||
357 | i++; | ||
358 | |||
359 | regs_buff[i++] = NXRD32(adapter, | ||
360 | NETXEN_NIU_XGE_CONFIG_0+(0x10000*port)); | ||
361 | regs_buff[i++] = NXRD32(adapter, | ||
362 | NETXEN_NIU_XGE_CONFIG_1+(0x10000*port)); | ||
363 | |||
364 | regs_buff[i++] = NXRD32(adapter, CRB_XG_STATE); | ||
365 | regs_buff[i++] = NXRDIO(adapter, | ||
366 | adapter->tx_ring->crb_cmd_consumer); | ||
367 | } | ||
368 | |||
369 | regs_buff[i++] = NXRDIO(adapter, adapter->tx_ring->crb_cmd_producer); | ||
370 | |||
371 | regs_buff[i++] = NXRDIO(adapter, | ||
372 | recv_ctx->rds_rings[0].crb_rcv_producer); | ||
373 | regs_buff[i++] = NXRDIO(adapter, | ||
374 | recv_ctx->rds_rings[1].crb_rcv_producer); | ||
375 | |||
376 | regs_buff[i++] = adapter->max_sds_rings; | ||
377 | |||
378 | for (ring = 0; ring < adapter->max_sds_rings; ring++) { | ||
379 | sds_ring = &(recv_ctx->sds_rings[ring]); | ||
380 | regs_buff[i++] = NXRDIO(adapter, | ||
381 | sds_ring->crb_sts_consumer); | ||
434 | } | 382 | } |
435 | } | 383 | } |
436 | 384 | ||
437 | static u32 netxen_nic_test_link(struct net_device *dev) | 385 | static u32 netxen_nic_test_link(struct net_device *dev) |
438 | { | 386 | { |
439 | struct netxen_adapter *adapter = netdev_priv(dev); | 387 | struct netxen_adapter *adapter = netdev_priv(dev); |
440 | __u32 status; | 388 | u32 val, port; |
441 | int val; | ||
442 | 389 | ||
443 | /* read which mode */ | 390 | port = adapter->physical_port; |
444 | if (adapter->ahw.port_type == NETXEN_NIC_GBE) { | 391 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
445 | if (adapter->phy_read && | 392 | val = NXRD32(adapter, CRB_XG_STATE_P3); |
446 | adapter->phy_read(adapter, | 393 | val = XG_LINK_STATE_P3(adapter->ahw.pci_func, val); |
447 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, | 394 | return (val == XG_LINK_UP_P3) ? 0 : 1; |
448 | &status) != 0) | 395 | } else { |
449 | return -EIO; | ||
450 | else { | ||
451 | val = netxen_get_phy_link(status); | ||
452 | return !val; | ||
453 | } | ||
454 | } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) { | ||
455 | val = NXRD32(adapter, CRB_XG_STATE); | 396 | val = NXRD32(adapter, CRB_XG_STATE); |
397 | val = (val >> port*8) & 0xff; | ||
456 | return (val == XG_LINK_UP) ? 0 : 1; | 398 | return (val == XG_LINK_UP) ? 0 : 1; |
457 | } | 399 | } |
458 | return -EIO; | ||
459 | } | 400 | } |
460 | 401 | ||
461 | static int | 402 | static int |