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path: root/drivers/net/e1000/e1000_hw.h
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-rw-r--r--drivers/net/e1000/e1000_hw.h3231
1 files changed, 1438 insertions, 1793 deletions
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index a8866bdbb671..9acfddb0dafb 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -35,7 +35,6 @@
35 35
36#include "e1000_osdep.h" 36#include "e1000_osdep.h"
37 37
38
39/* Forward declarations of structures used by the shared code */ 38/* Forward declarations of structures used by the shared code */
40struct e1000_hw; 39struct e1000_hw;
41struct e1000_hw_stats; 40struct e1000_hw_stats;
@@ -43,252 +42,231 @@ struct e1000_hw_stats;
43/* Enumerated types specific to the e1000 hardware */ 42/* Enumerated types specific to the e1000 hardware */
44/* Media Access Controlers */ 43/* Media Access Controlers */
45typedef enum { 44typedef enum {
46 e1000_undefined = 0, 45 e1000_undefined = 0,
47 e1000_82542_rev2_0, 46 e1000_82542_rev2_0,
48 e1000_82542_rev2_1, 47 e1000_82542_rev2_1,
49 e1000_82543, 48 e1000_82543,
50 e1000_82544, 49 e1000_82544,
51 e1000_82540, 50 e1000_82540,
52 e1000_82545, 51 e1000_82545,
53 e1000_82545_rev_3, 52 e1000_82545_rev_3,
54 e1000_82546, 53 e1000_82546,
55 e1000_82546_rev_3, 54 e1000_82546_rev_3,
56 e1000_82541, 55 e1000_82541,
57 e1000_82541_rev_2, 56 e1000_82541_rev_2,
58 e1000_82547, 57 e1000_82547,
59 e1000_82547_rev_2, 58 e1000_82547_rev_2,
60 e1000_82571, 59 e1000_num_macs
61 e1000_82572,
62 e1000_82573,
63 e1000_80003es2lan,
64 e1000_ich8lan,
65 e1000_num_macs
66} e1000_mac_type; 60} e1000_mac_type;
67 61
68typedef enum { 62typedef enum {
69 e1000_eeprom_uninitialized = 0, 63 e1000_eeprom_uninitialized = 0,
70 e1000_eeprom_spi, 64 e1000_eeprom_spi,
71 e1000_eeprom_microwire, 65 e1000_eeprom_microwire,
72 e1000_eeprom_flash, 66 e1000_eeprom_flash,
73 e1000_eeprom_ich8, 67 e1000_eeprom_none, /* No NVM support */
74 e1000_eeprom_none, /* No NVM support */ 68 e1000_num_eeprom_types
75 e1000_num_eeprom_types
76} e1000_eeprom_type; 69} e1000_eeprom_type;
77 70
78/* Media Types */ 71/* Media Types */
79typedef enum { 72typedef enum {
80 e1000_media_type_copper = 0, 73 e1000_media_type_copper = 0,
81 e1000_media_type_fiber = 1, 74 e1000_media_type_fiber = 1,
82 e1000_media_type_internal_serdes = 2, 75 e1000_media_type_internal_serdes = 2,
83 e1000_num_media_types 76 e1000_num_media_types
84} e1000_media_type; 77} e1000_media_type;
85 78
86typedef enum { 79typedef enum {
87 e1000_10_half = 0, 80 e1000_10_half = 0,
88 e1000_10_full = 1, 81 e1000_10_full = 1,
89 e1000_100_half = 2, 82 e1000_100_half = 2,
90 e1000_100_full = 3 83 e1000_100_full = 3
91} e1000_speed_duplex_type; 84} e1000_speed_duplex_type;
92 85
93/* Flow Control Settings */ 86/* Flow Control Settings */
94typedef enum { 87typedef enum {
95 E1000_FC_NONE = 0, 88 E1000_FC_NONE = 0,
96 E1000_FC_RX_PAUSE = 1, 89 E1000_FC_RX_PAUSE = 1,
97 E1000_FC_TX_PAUSE = 2, 90 E1000_FC_TX_PAUSE = 2,
98 E1000_FC_FULL = 3, 91 E1000_FC_FULL = 3,
99 E1000_FC_DEFAULT = 0xFF 92 E1000_FC_DEFAULT = 0xFF
100} e1000_fc_type; 93} e1000_fc_type;
101 94
102struct e1000_shadow_ram { 95struct e1000_shadow_ram {
103 u16 eeprom_word; 96 u16 eeprom_word;
104 bool modified; 97 bool modified;
105}; 98};
106 99
107/* PCI bus types */ 100/* PCI bus types */
108typedef enum { 101typedef enum {
109 e1000_bus_type_unknown = 0, 102 e1000_bus_type_unknown = 0,
110 e1000_bus_type_pci, 103 e1000_bus_type_pci,
111 e1000_bus_type_pcix, 104 e1000_bus_type_pcix,
112 e1000_bus_type_pci_express, 105 e1000_bus_type_reserved
113 e1000_bus_type_reserved
114} e1000_bus_type; 106} e1000_bus_type;
115 107
116/* PCI bus speeds */ 108/* PCI bus speeds */
117typedef enum { 109typedef enum {
118 e1000_bus_speed_unknown = 0, 110 e1000_bus_speed_unknown = 0,
119 e1000_bus_speed_33, 111 e1000_bus_speed_33,
120 e1000_bus_speed_66, 112 e1000_bus_speed_66,
121 e1000_bus_speed_100, 113 e1000_bus_speed_100,
122 e1000_bus_speed_120, 114 e1000_bus_speed_120,
123 e1000_bus_speed_133, 115 e1000_bus_speed_133,
124 e1000_bus_speed_2500, 116 e1000_bus_speed_reserved
125 e1000_bus_speed_reserved
126} e1000_bus_speed; 117} e1000_bus_speed;
127 118
128/* PCI bus widths */ 119/* PCI bus widths */
129typedef enum { 120typedef enum {
130 e1000_bus_width_unknown = 0, 121 e1000_bus_width_unknown = 0,
131 /* These PCIe values should literally match the possible return values 122 e1000_bus_width_32,
132 * from config space */ 123 e1000_bus_width_64,
133 e1000_bus_width_pciex_1 = 1, 124 e1000_bus_width_reserved
134 e1000_bus_width_pciex_2 = 2,
135 e1000_bus_width_pciex_4 = 4,
136 e1000_bus_width_32,
137 e1000_bus_width_64,
138 e1000_bus_width_reserved
139} e1000_bus_width; 125} e1000_bus_width;
140 126
141/* PHY status info structure and supporting enums */ 127/* PHY status info structure and supporting enums */
142typedef enum { 128typedef enum {
143 e1000_cable_length_50 = 0, 129 e1000_cable_length_50 = 0,
144 e1000_cable_length_50_80, 130 e1000_cable_length_50_80,
145 e1000_cable_length_80_110, 131 e1000_cable_length_80_110,
146 e1000_cable_length_110_140, 132 e1000_cable_length_110_140,
147 e1000_cable_length_140, 133 e1000_cable_length_140,
148 e1000_cable_length_undefined = 0xFF 134 e1000_cable_length_undefined = 0xFF
149} e1000_cable_length; 135} e1000_cable_length;
150 136
151typedef enum { 137typedef enum {
152 e1000_gg_cable_length_60 = 0, 138 e1000_gg_cable_length_60 = 0,
153 e1000_gg_cable_length_60_115 = 1, 139 e1000_gg_cable_length_60_115 = 1,
154 e1000_gg_cable_length_115_150 = 2, 140 e1000_gg_cable_length_115_150 = 2,
155 e1000_gg_cable_length_150 = 4 141 e1000_gg_cable_length_150 = 4
156} e1000_gg_cable_length; 142} e1000_gg_cable_length;
157 143
158typedef enum { 144typedef enum {
159 e1000_igp_cable_length_10 = 10, 145 e1000_igp_cable_length_10 = 10,
160 e1000_igp_cable_length_20 = 20, 146 e1000_igp_cable_length_20 = 20,
161 e1000_igp_cable_length_30 = 30, 147 e1000_igp_cable_length_30 = 30,
162 e1000_igp_cable_length_40 = 40, 148 e1000_igp_cable_length_40 = 40,
163 e1000_igp_cable_length_50 = 50, 149 e1000_igp_cable_length_50 = 50,
164 e1000_igp_cable_length_60 = 60, 150 e1000_igp_cable_length_60 = 60,
165 e1000_igp_cable_length_70 = 70, 151 e1000_igp_cable_length_70 = 70,
166 e1000_igp_cable_length_80 = 80, 152 e1000_igp_cable_length_80 = 80,
167 e1000_igp_cable_length_90 = 90, 153 e1000_igp_cable_length_90 = 90,
168 e1000_igp_cable_length_100 = 100, 154 e1000_igp_cable_length_100 = 100,
169 e1000_igp_cable_length_110 = 110, 155 e1000_igp_cable_length_110 = 110,
170 e1000_igp_cable_length_115 = 115, 156 e1000_igp_cable_length_115 = 115,
171 e1000_igp_cable_length_120 = 120, 157 e1000_igp_cable_length_120 = 120,
172 e1000_igp_cable_length_130 = 130, 158 e1000_igp_cable_length_130 = 130,
173 e1000_igp_cable_length_140 = 140, 159 e1000_igp_cable_length_140 = 140,
174 e1000_igp_cable_length_150 = 150, 160 e1000_igp_cable_length_150 = 150,
175 e1000_igp_cable_length_160 = 160, 161 e1000_igp_cable_length_160 = 160,
176 e1000_igp_cable_length_170 = 170, 162 e1000_igp_cable_length_170 = 170,
177 e1000_igp_cable_length_180 = 180 163 e1000_igp_cable_length_180 = 180
178} e1000_igp_cable_length; 164} e1000_igp_cable_length;
179 165
180typedef enum { 166typedef enum {
181 e1000_10bt_ext_dist_enable_normal = 0, 167 e1000_10bt_ext_dist_enable_normal = 0,
182 e1000_10bt_ext_dist_enable_lower, 168 e1000_10bt_ext_dist_enable_lower,
183 e1000_10bt_ext_dist_enable_undefined = 0xFF 169 e1000_10bt_ext_dist_enable_undefined = 0xFF
184} e1000_10bt_ext_dist_enable; 170} e1000_10bt_ext_dist_enable;
185 171
186typedef enum { 172typedef enum {
187 e1000_rev_polarity_normal = 0, 173 e1000_rev_polarity_normal = 0,
188 e1000_rev_polarity_reversed, 174 e1000_rev_polarity_reversed,
189 e1000_rev_polarity_undefined = 0xFF 175 e1000_rev_polarity_undefined = 0xFF
190} e1000_rev_polarity; 176} e1000_rev_polarity;
191 177
192typedef enum { 178typedef enum {
193 e1000_downshift_normal = 0, 179 e1000_downshift_normal = 0,
194 e1000_downshift_activated, 180 e1000_downshift_activated,
195 e1000_downshift_undefined = 0xFF 181 e1000_downshift_undefined = 0xFF
196} e1000_downshift; 182} e1000_downshift;
197 183
198typedef enum { 184typedef enum {
199 e1000_smart_speed_default = 0, 185 e1000_smart_speed_default = 0,
200 e1000_smart_speed_on, 186 e1000_smart_speed_on,
201 e1000_smart_speed_off 187 e1000_smart_speed_off
202} e1000_smart_speed; 188} e1000_smart_speed;
203 189
204typedef enum { 190typedef enum {
205 e1000_polarity_reversal_enabled = 0, 191 e1000_polarity_reversal_enabled = 0,
206 e1000_polarity_reversal_disabled, 192 e1000_polarity_reversal_disabled,
207 e1000_polarity_reversal_undefined = 0xFF 193 e1000_polarity_reversal_undefined = 0xFF
208} e1000_polarity_reversal; 194} e1000_polarity_reversal;
209 195
210typedef enum { 196typedef enum {
211 e1000_auto_x_mode_manual_mdi = 0, 197 e1000_auto_x_mode_manual_mdi = 0,
212 e1000_auto_x_mode_manual_mdix, 198 e1000_auto_x_mode_manual_mdix,
213 e1000_auto_x_mode_auto1, 199 e1000_auto_x_mode_auto1,
214 e1000_auto_x_mode_auto2, 200 e1000_auto_x_mode_auto2,
215 e1000_auto_x_mode_undefined = 0xFF 201 e1000_auto_x_mode_undefined = 0xFF
216} e1000_auto_x_mode; 202} e1000_auto_x_mode;
217 203
218typedef enum { 204typedef enum {
219 e1000_1000t_rx_status_not_ok = 0, 205 e1000_1000t_rx_status_not_ok = 0,
220 e1000_1000t_rx_status_ok, 206 e1000_1000t_rx_status_ok,
221 e1000_1000t_rx_status_undefined = 0xFF 207 e1000_1000t_rx_status_undefined = 0xFF
222} e1000_1000t_rx_status; 208} e1000_1000t_rx_status;
223 209
224typedef enum { 210typedef enum {
225 e1000_phy_m88 = 0, 211 e1000_phy_m88 = 0,
226 e1000_phy_igp, 212 e1000_phy_igp,
227 e1000_phy_igp_2,
228 e1000_phy_gg82563,
229 e1000_phy_igp_3,
230 e1000_phy_ife,
231 e1000_phy_undefined = 0xFF 213 e1000_phy_undefined = 0xFF
232} e1000_phy_type; 214} e1000_phy_type;
233 215
234typedef enum { 216typedef enum {
235 e1000_ms_hw_default = 0, 217 e1000_ms_hw_default = 0,
236 e1000_ms_force_master, 218 e1000_ms_force_master,
237 e1000_ms_force_slave, 219 e1000_ms_force_slave,
238 e1000_ms_auto 220 e1000_ms_auto
239} e1000_ms_type; 221} e1000_ms_type;
240 222
241typedef enum { 223typedef enum {
242 e1000_ffe_config_enabled = 0, 224 e1000_ffe_config_enabled = 0,
243 e1000_ffe_config_active, 225 e1000_ffe_config_active,
244 e1000_ffe_config_blocked 226 e1000_ffe_config_blocked
245} e1000_ffe_config; 227} e1000_ffe_config;
246 228
247typedef enum { 229typedef enum {
248 e1000_dsp_config_disabled = 0, 230 e1000_dsp_config_disabled = 0,
249 e1000_dsp_config_enabled, 231 e1000_dsp_config_enabled,
250 e1000_dsp_config_activated, 232 e1000_dsp_config_activated,
251 e1000_dsp_config_undefined = 0xFF 233 e1000_dsp_config_undefined = 0xFF
252} e1000_dsp_config; 234} e1000_dsp_config;
253 235
254struct e1000_phy_info { 236struct e1000_phy_info {
255 e1000_cable_length cable_length; 237 e1000_cable_length cable_length;
256 e1000_10bt_ext_dist_enable extended_10bt_distance; 238 e1000_10bt_ext_dist_enable extended_10bt_distance;
257 e1000_rev_polarity cable_polarity; 239 e1000_rev_polarity cable_polarity;
258 e1000_downshift downshift; 240 e1000_downshift downshift;
259 e1000_polarity_reversal polarity_correction; 241 e1000_polarity_reversal polarity_correction;
260 e1000_auto_x_mode mdix_mode; 242 e1000_auto_x_mode mdix_mode;
261 e1000_1000t_rx_status local_rx; 243 e1000_1000t_rx_status local_rx;
262 e1000_1000t_rx_status remote_rx; 244 e1000_1000t_rx_status remote_rx;
263}; 245};
264 246
265struct e1000_phy_stats { 247struct e1000_phy_stats {
266 u32 idle_errors; 248 u32 idle_errors;
267 u32 receive_errors; 249 u32 receive_errors;
268}; 250};
269 251
270struct e1000_eeprom_info { 252struct e1000_eeprom_info {
271 e1000_eeprom_type type; 253 e1000_eeprom_type type;
272 u16 word_size; 254 u16 word_size;
273 u16 opcode_bits; 255 u16 opcode_bits;
274 u16 address_bits; 256 u16 address_bits;
275 u16 delay_usec; 257 u16 delay_usec;
276 u16 page_size; 258 u16 page_size;
277 bool use_eerd;
278 bool use_eewr;
279}; 259};
280 260
281/* Flex ASF Information */ 261/* Flex ASF Information */
282#define E1000_HOST_IF_MAX_SIZE 2048 262#define E1000_HOST_IF_MAX_SIZE 2048
283 263
284typedef enum { 264typedef enum {
285 e1000_byte_align = 0, 265 e1000_byte_align = 0,
286 e1000_word_align = 1, 266 e1000_word_align = 1,
287 e1000_dword_align = 2 267 e1000_dword_align = 2
288} e1000_align_type; 268} e1000_align_type;
289 269
290
291
292/* Error Codes */ 270/* Error Codes */
293#define E1000_SUCCESS 0 271#define E1000_SUCCESS 0
294#define E1000_ERR_EEPROM 1 272#define E1000_ERR_EEPROM 1
@@ -301,7 +279,6 @@ typedef enum {
301#define E1000_ERR_MASTER_REQUESTS_PENDING 10 279#define E1000_ERR_MASTER_REQUESTS_PENDING 10
302#define E1000_ERR_HOST_INTERFACE_COMMAND 11 280#define E1000_ERR_HOST_INTERFACE_COMMAND 11
303#define E1000_BLK_PHY_RESET 12 281#define E1000_BLK_PHY_RESET 12
304#define E1000_ERR_SWFW_SYNC 13
305 282
306#define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \ 283#define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \
307 (((_value) & 0xff00) >> 8)) 284 (((_value) & 0xff00) >> 8))
@@ -318,19 +295,17 @@ s32 e1000_setup_link(struct e1000_hw *hw);
318s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); 295s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
319void e1000_config_collision_dist(struct e1000_hw *hw); 296void e1000_config_collision_dist(struct e1000_hw *hw);
320s32 e1000_check_for_link(struct e1000_hw *hw); 297s32 e1000_check_for_link(struct e1000_hw *hw);
321s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex); 298s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 * speed, u16 * duplex);
322s32 e1000_force_mac_fc(struct e1000_hw *hw); 299s32 e1000_force_mac_fc(struct e1000_hw *hw);
323 300
324/* PHY */ 301/* PHY */
325s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data); 302s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 * phy_data);
326s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data); 303s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
327s32 e1000_phy_hw_reset(struct e1000_hw *hw); 304s32 e1000_phy_hw_reset(struct e1000_hw *hw);
328s32 e1000_phy_reset(struct e1000_hw *hw); 305s32 e1000_phy_reset(struct e1000_hw *hw);
329s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 306s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
330s32 e1000_validate_mdi_setting(struct e1000_hw *hw); 307s32 e1000_validate_mdi_setting(struct e1000_hw *hw);
331 308
332void e1000_phy_powerdown_workaround(struct e1000_hw *hw);
333
334/* EEPROM Functions */ 309/* EEPROM Functions */
335s32 e1000_init_eeprom_params(struct e1000_hw *hw); 310s32 e1000_init_eeprom_params(struct e1000_hw *hw);
336 311
@@ -338,66 +313,63 @@ s32 e1000_init_eeprom_params(struct e1000_hw *hw);
338u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw); 313u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw);
339 314
340#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 315#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
341#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ 316#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
342 317
343#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ 318#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
344#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ 319#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
345#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ 320#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
346#define E1000_MNG_IAMT_MODE 0x3 321#define E1000_MNG_IAMT_MODE 0x3
347#define E1000_MNG_ICH_IAMT_MODE 0x2 322#define E1000_MNG_ICH_IAMT_MODE 0x2
348#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ 323#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
349 324
350#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */ 325#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
351#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */ 326#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */
352#define E1000_VFTA_ENTRY_SHIFT 0x5 327#define E1000_VFTA_ENTRY_SHIFT 0x5
353#define E1000_VFTA_ENTRY_MASK 0x7F 328#define E1000_VFTA_ENTRY_MASK 0x7F
354#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 329#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
355 330
356struct e1000_host_mng_command_header { 331struct e1000_host_mng_command_header {
357 u8 command_id; 332 u8 command_id;
358 u8 checksum; 333 u8 checksum;
359 u16 reserved1; 334 u16 reserved1;
360 u16 reserved2; 335 u16 reserved2;
361 u16 command_length; 336 u16 command_length;
362}; 337};
363 338
364struct e1000_host_mng_command_info { 339struct e1000_host_mng_command_info {
365 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ 340 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
366 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/ 341 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658 */
367}; 342};
368#ifdef __BIG_ENDIAN 343#ifdef __BIG_ENDIAN
369struct e1000_host_mng_dhcp_cookie{ 344struct e1000_host_mng_dhcp_cookie {
370 u32 signature; 345 u32 signature;
371 u16 vlan_id; 346 u16 vlan_id;
372 u8 reserved0; 347 u8 reserved0;
373 u8 status; 348 u8 status;
374 u32 reserved1; 349 u32 reserved1;
375 u8 checksum; 350 u8 checksum;
376 u8 reserved3; 351 u8 reserved3;
377 u16 reserved2; 352 u16 reserved2;
378}; 353};
379#else 354#else
380struct e1000_host_mng_dhcp_cookie{ 355struct e1000_host_mng_dhcp_cookie {
381 u32 signature; 356 u32 signature;
382 u8 status; 357 u8 status;
383 u8 reserved0; 358 u8 reserved0;
384 u16 vlan_id; 359 u16 vlan_id;
385 u32 reserved1; 360 u32 reserved1;
386 u16 reserved2; 361 u16 reserved2;
387 u8 reserved3; 362 u8 reserved3;
388 u8 checksum; 363 u8 checksum;
389}; 364};
390#endif 365#endif
391 366
392s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer,
393 u16 length);
394bool e1000_check_mng_mode(struct e1000_hw *hw); 367bool e1000_check_mng_mode(struct e1000_hw *hw);
395bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); 368s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
396s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data);
397s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw); 369s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw);
398s32 e1000_update_eeprom_checksum(struct e1000_hw *hw); 370s32 e1000_update_eeprom_checksum(struct e1000_hw *hw);
399s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data); 371s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
400s32 e1000_read_mac_addr(struct e1000_hw * hw); 372s32 e1000_read_mac_addr(struct e1000_hw *hw);
401 373
402/* Filters (multicast, vlan, receive) */ 374/* Filters (multicast, vlan, receive) */
403u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr); 375u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr);
@@ -417,18 +389,15 @@ s32 e1000_blink_led_start(struct e1000_hw *hw);
417/* Everything else */ 389/* Everything else */
418void e1000_reset_adaptive(struct e1000_hw *hw); 390void e1000_reset_adaptive(struct e1000_hw *hw);
419void e1000_update_adaptive(struct e1000_hw *hw); 391void e1000_update_adaptive(struct e1000_hw *hw);
420void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, u32 frame_len, u8 * mac_addr); 392void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
393 u32 frame_len, u8 * mac_addr);
421void e1000_get_bus_info(struct e1000_hw *hw); 394void e1000_get_bus_info(struct e1000_hw *hw);
422void e1000_pci_set_mwi(struct e1000_hw *hw); 395void e1000_pci_set_mwi(struct e1000_hw *hw);
423void e1000_pci_clear_mwi(struct e1000_hw *hw); 396void e1000_pci_clear_mwi(struct e1000_hw *hw);
424s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
425void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc); 397void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc);
426int e1000_pcix_get_mmrbc(struct e1000_hw *hw); 398int e1000_pcix_get_mmrbc(struct e1000_hw *hw);
427/* Port I/O is only supported on 82544 and newer */ 399/* Port I/O is only supported on 82544 and newer */
428void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value); 400void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
429s32 e1000_disable_pciex_master(struct e1000_hw *hw);
430s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
431
432 401
433#define E1000_READ_REG_IO(a, reg) \ 402#define E1000_READ_REG_IO(a, reg) \
434 e1000_read_reg_io((a), E1000_##reg) 403 e1000_read_reg_io((a), E1000_##reg)
@@ -471,36 +440,7 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
471#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 440#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
472#define E1000_DEV_ID_82547EI 0x1019 441#define E1000_DEV_ID_82547EI 0x1019
473#define E1000_DEV_ID_82547EI_MOBILE 0x101A 442#define E1000_DEV_ID_82547EI_MOBILE 0x101A
474#define E1000_DEV_ID_82571EB_COPPER 0x105E
475#define E1000_DEV_ID_82571EB_FIBER 0x105F
476#define E1000_DEV_ID_82571EB_SERDES 0x1060
477#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
478#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
479#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
480#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
481#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
482#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
483#define E1000_DEV_ID_82572EI_COPPER 0x107D
484#define E1000_DEV_ID_82572EI_FIBER 0x107E
485#define E1000_DEV_ID_82572EI_SERDES 0x107F
486#define E1000_DEV_ID_82572EI 0x10B9
487#define E1000_DEV_ID_82573E 0x108B
488#define E1000_DEV_ID_82573E_IAMT 0x108C
489#define E1000_DEV_ID_82573L 0x109A
490#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 443#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
491#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
492#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
493#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
494#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
495
496#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
497#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
498#define E1000_DEV_ID_ICH8_IGP_C 0x104B
499#define E1000_DEV_ID_ICH8_IFE 0x104C
500#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
501#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
502#define E1000_DEV_ID_ICH8_IGP_M 0x104D
503
504 444
505#define NODE_ADDRESS_SIZE 6 445#define NODE_ADDRESS_SIZE 6
506#define ETH_LENGTH_OF_ADDRESS 6 446#define ETH_LENGTH_OF_ADDRESS 6
@@ -523,21 +463,20 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
523 463
524/* The sizes (in bytes) of a ethernet packet */ 464/* The sizes (in bytes) of a ethernet packet */
525#define ENET_HEADER_SIZE 14 465#define ENET_HEADER_SIZE 14
526#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ 466#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
527#define ETHERNET_FCS_SIZE 4 467#define ETHERNET_FCS_SIZE 4
528#define MINIMUM_ETHERNET_PACKET_SIZE \ 468#define MINIMUM_ETHERNET_PACKET_SIZE \
529 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 469 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
530#define CRC_LENGTH ETHERNET_FCS_SIZE 470#define CRC_LENGTH ETHERNET_FCS_SIZE
531#define MAX_JUMBO_FRAME_SIZE 0x3F00 471#define MAX_JUMBO_FRAME_SIZE 0x3F00
532 472
533
534/* 802.1q VLAN Packet Sizes */ 473/* 802.1q VLAN Packet Sizes */
535#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ 474#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
536 475
537/* Ethertype field values */ 476/* Ethertype field values */
538#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 477#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
539#define ETHERNET_IP_TYPE 0x0800 /* IP packets */ 478#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
540#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ 479#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
541 480
542/* Packet Header defines */ 481/* Packet Header defines */
543#define IP_PROTOCOL_TCP 6 482#define IP_PROTOCOL_TCP 6
@@ -567,15 +506,6 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
567 E1000_IMS_RXSEQ | \ 506 E1000_IMS_RXSEQ | \
568 E1000_IMS_LSC) 507 E1000_IMS_LSC)
569 508
570/* Additional interrupts need to be handled for e1000_ich8lan:
571 DSW = The FW changed the status of the DISSW bit in FWSM
572 PHYINT = The LAN connected device generates an interrupt
573 EPRST = Manageability reset event */
574#define IMS_ICH8LAN_ENABLE_MASK (\
575 E1000_IMS_DSW | \
576 E1000_IMS_PHYINT | \
577 E1000_IMS_EPRST)
578
579/* Number of high/low register pairs in the RAR. The RAR (Receive Address 509/* Number of high/low register pairs in the RAR. The RAR (Receive Address
580 * Registers) holds the directed and multicast addresses that we monitor. We 510 * Registers) holds the directed and multicast addresses that we monitor. We
581 * reserve one of these spots for our directed address, allowing us room for 511 * reserve one of these spots for our directed address, allowing us room for
@@ -583,100 +513,98 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
583 */ 513 */
584#define E1000_RAR_ENTRIES 15 514#define E1000_RAR_ENTRIES 15
585 515
586#define E1000_RAR_ENTRIES_ICH8LAN 6
587
588#define MIN_NUMBER_OF_DESCRIPTORS 8 516#define MIN_NUMBER_OF_DESCRIPTORS 8
589#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 517#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
590 518
591/* Receive Descriptor */ 519/* Receive Descriptor */
592struct e1000_rx_desc { 520struct e1000_rx_desc {
593 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 521 __le64 buffer_addr; /* Address of the descriptor's data buffer */
594 __le16 length; /* Length of data DMAed into data buffer */ 522 __le16 length; /* Length of data DMAed into data buffer */
595 __le16 csum; /* Packet checksum */ 523 __le16 csum; /* Packet checksum */
596 u8 status; /* Descriptor status */ 524 u8 status; /* Descriptor status */
597 u8 errors; /* Descriptor Errors */ 525 u8 errors; /* Descriptor Errors */
598 __le16 special; 526 __le16 special;
599}; 527};
600 528
601/* Receive Descriptor - Extended */ 529/* Receive Descriptor - Extended */
602union e1000_rx_desc_extended { 530union e1000_rx_desc_extended {
603 struct { 531 struct {
604 __le64 buffer_addr; 532 __le64 buffer_addr;
605 __le64 reserved; 533 __le64 reserved;
606 } read; 534 } read;
607 struct { 535 struct {
608 struct { 536 struct {
609 __le32 mrq; /* Multiple Rx Queues */ 537 __le32 mrq; /* Multiple Rx Queues */
610 union { 538 union {
611 __le32 rss; /* RSS Hash */ 539 __le32 rss; /* RSS Hash */
612 struct { 540 struct {
613 __le16 ip_id; /* IP id */ 541 __le16 ip_id; /* IP id */
614 __le16 csum; /* Packet Checksum */ 542 __le16 csum; /* Packet Checksum */
615 } csum_ip; 543 } csum_ip;
616 } hi_dword; 544 } hi_dword;
617 } lower; 545 } lower;
618 struct { 546 struct {
619 __le32 status_error; /* ext status/error */ 547 __le32 status_error; /* ext status/error */
620 __le16 length; 548 __le16 length;
621 __le16 vlan; /* VLAN tag */ 549 __le16 vlan; /* VLAN tag */
622 } upper; 550 } upper;
623 } wb; /* writeback */ 551 } wb; /* writeback */
624}; 552};
625 553
626#define MAX_PS_BUFFERS 4 554#define MAX_PS_BUFFERS 4
627/* Receive Descriptor - Packet Split */ 555/* Receive Descriptor - Packet Split */
628union e1000_rx_desc_packet_split { 556union e1000_rx_desc_packet_split {
629 struct { 557 struct {
630 /* one buffer for protocol header(s), three data buffers */ 558 /* one buffer for protocol header(s), three data buffers */
631 __le64 buffer_addr[MAX_PS_BUFFERS]; 559 __le64 buffer_addr[MAX_PS_BUFFERS];
632 } read; 560 } read;
633 struct { 561 struct {
634 struct { 562 struct {
635 __le32 mrq; /* Multiple Rx Queues */ 563 __le32 mrq; /* Multiple Rx Queues */
636 union { 564 union {
637 __le32 rss; /* RSS Hash */ 565 __le32 rss; /* RSS Hash */
638 struct { 566 struct {
639 __le16 ip_id; /* IP id */ 567 __le16 ip_id; /* IP id */
640 __le16 csum; /* Packet Checksum */ 568 __le16 csum; /* Packet Checksum */
641 } csum_ip; 569 } csum_ip;
642 } hi_dword; 570 } hi_dword;
643 } lower; 571 } lower;
644 struct { 572 struct {
645 __le32 status_error; /* ext status/error */ 573 __le32 status_error; /* ext status/error */
646 __le16 length0; /* length of buffer 0 */ 574 __le16 length0; /* length of buffer 0 */
647 __le16 vlan; /* VLAN tag */ 575 __le16 vlan; /* VLAN tag */
648 } middle; 576 } middle;
649 struct { 577 struct {
650 __le16 header_status; 578 __le16 header_status;
651 __le16 length[3]; /* length of buffers 1-3 */ 579 __le16 length[3]; /* length of buffers 1-3 */
652 } upper; 580 } upper;
653 __le64 reserved; 581 __le64 reserved;
654 } wb; /* writeback */ 582 } wb; /* writeback */
655}; 583};
656 584
657/* Receive Decriptor bit definitions */ 585/* Receive Descriptor bit definitions */
658#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 586#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
659#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 587#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
660#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 588#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
661#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 589#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
662#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ 590#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
663#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 591#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
664#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 592#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
665#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 593#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
666#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 594#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
667#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 595#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
668#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 596#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
669#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 597#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
670#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 598#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
671#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 599#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
672#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 600#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
673#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 601#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
674#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 602#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
675#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 603#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
676#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 604#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
677#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 605#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
678#define E1000_RXD_SPC_PRI_SHIFT 13 606#define E1000_RXD_SPC_PRI_SHIFT 13
679#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 607#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
680#define E1000_RXD_SPC_CFI_SHIFT 12 608#define E1000_RXD_SPC_CFI_SHIFT 12
681 609
682#define E1000_RXDEXT_STATERR_CE 0x01000000 610#define E1000_RXDEXT_STATERR_CE 0x01000000
@@ -698,7 +626,6 @@ union e1000_rx_desc_packet_split {
698 E1000_RXD_ERR_CXE | \ 626 E1000_RXD_ERR_CXE | \
699 E1000_RXD_ERR_RXE) 627 E1000_RXD_ERR_RXE)
700 628
701
702/* Same mask, but for extended and packet split descriptors */ 629/* Same mask, but for extended and packet split descriptors */
703#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 630#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
704 E1000_RXDEXT_STATERR_CE | \ 631 E1000_RXDEXT_STATERR_CE | \
@@ -707,152 +634,145 @@ union e1000_rx_desc_packet_split {
707 E1000_RXDEXT_STATERR_CXE | \ 634 E1000_RXDEXT_STATERR_CXE | \
708 E1000_RXDEXT_STATERR_RXE) 635 E1000_RXDEXT_STATERR_RXE)
709 636
710
711/* Transmit Descriptor */ 637/* Transmit Descriptor */
712struct e1000_tx_desc { 638struct e1000_tx_desc {
713 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 639 __le64 buffer_addr; /* Address of the descriptor's data buffer */
714 union { 640 union {
715 __le32 data; 641 __le32 data;
716 struct { 642 struct {
717 __le16 length; /* Data buffer length */ 643 __le16 length; /* Data buffer length */
718 u8 cso; /* Checksum offset */ 644 u8 cso; /* Checksum offset */
719 u8 cmd; /* Descriptor control */ 645 u8 cmd; /* Descriptor control */
720 } flags; 646 } flags;
721 } lower; 647 } lower;
722 union { 648 union {
723 __le32 data; 649 __le32 data;
724 struct { 650 struct {
725 u8 status; /* Descriptor status */ 651 u8 status; /* Descriptor status */
726 u8 css; /* Checksum start */ 652 u8 css; /* Checksum start */
727 __le16 special; 653 __le16 special;
728 } fields; 654 } fields;
729 } upper; 655 } upper;
730}; 656};
731 657
732/* Transmit Descriptor bit definitions */ 658/* Transmit Descriptor bit definitions */
733#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 659#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
734#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 660#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
735#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 661#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
736#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 662#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
737#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 663#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
738#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 664#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
739#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 665#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
740#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 666#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
741#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 667#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
742#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 668#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
743#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 669#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
744#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 670#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
745#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 671#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
746#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 672#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
747#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 673#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
748#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 674#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
749#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 675#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
750#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 676#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
751#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 677#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
752#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 678#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
753 679
754/* Offload Context Descriptor */ 680/* Offload Context Descriptor */
755struct e1000_context_desc { 681struct e1000_context_desc {
756 union { 682 union {
757 __le32 ip_config; 683 __le32 ip_config;
758 struct { 684 struct {
759 u8 ipcss; /* IP checksum start */ 685 u8 ipcss; /* IP checksum start */
760 u8 ipcso; /* IP checksum offset */ 686 u8 ipcso; /* IP checksum offset */
761 __le16 ipcse; /* IP checksum end */ 687 __le16 ipcse; /* IP checksum end */
762 } ip_fields; 688 } ip_fields;
763 } lower_setup; 689 } lower_setup;
764 union { 690 union {
765 __le32 tcp_config; 691 __le32 tcp_config;
766 struct { 692 struct {
767 u8 tucss; /* TCP checksum start */ 693 u8 tucss; /* TCP checksum start */
768 u8 tucso; /* TCP checksum offset */ 694 u8 tucso; /* TCP checksum offset */
769 __le16 tucse; /* TCP checksum end */ 695 __le16 tucse; /* TCP checksum end */
770 } tcp_fields; 696 } tcp_fields;
771 } upper_setup; 697 } upper_setup;
772 __le32 cmd_and_length; /* */ 698 __le32 cmd_and_length; /* */
773 union { 699 union {
774 __le32 data; 700 __le32 data;
775 struct { 701 struct {
776 u8 status; /* Descriptor status */ 702 u8 status; /* Descriptor status */
777 u8 hdr_len; /* Header length */ 703 u8 hdr_len; /* Header length */
778 __le16 mss; /* Maximum segment size */ 704 __le16 mss; /* Maximum segment size */
779 } fields; 705 } fields;
780 } tcp_seg_setup; 706 } tcp_seg_setup;
781}; 707};
782 708
783/* Offload data descriptor */ 709/* Offload data descriptor */
784struct e1000_data_desc { 710struct e1000_data_desc {
785 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 711 __le64 buffer_addr; /* Address of the descriptor's buffer address */
786 union { 712 union {
787 __le32 data; 713 __le32 data;
788 struct { 714 struct {
789 __le16 length; /* Data buffer length */ 715 __le16 length; /* Data buffer length */
790 u8 typ_len_ext; /* */ 716 u8 typ_len_ext; /* */
791 u8 cmd; /* */ 717 u8 cmd; /* */
792 } flags; 718 } flags;
793 } lower; 719 } lower;
794 union { 720 union {
795 __le32 data; 721 __le32 data;
796 struct { 722 struct {
797 u8 status; /* Descriptor status */ 723 u8 status; /* Descriptor status */
798 u8 popts; /* Packet Options */ 724 u8 popts; /* Packet Options */
799 __le16 special; /* */ 725 __le16 special; /* */
800 } fields; 726 } fields;
801 } upper; 727 } upper;
802}; 728};
803 729
804/* Filters */ 730/* Filters */
805#define E1000_NUM_UNICAST 16 /* Unicast filter entries */ 731#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
806#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 732#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
807#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 733#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
808
809#define E1000_NUM_UNICAST_ICH8LAN 7
810#define E1000_MC_TBL_SIZE_ICH8LAN 32
811
812 734
813/* Receive Address Register */ 735/* Receive Address Register */
814struct e1000_rar { 736struct e1000_rar {
815 volatile __le32 low; /* receive address low */ 737 volatile __le32 low; /* receive address low */
816 volatile __le32 high; /* receive address high */ 738 volatile __le32 high; /* receive address high */
817}; 739};
818 740
819/* Number of entries in the Multicast Table Array (MTA). */ 741/* Number of entries in the Multicast Table Array (MTA). */
820#define E1000_NUM_MTA_REGISTERS 128 742#define E1000_NUM_MTA_REGISTERS 128
821#define E1000_NUM_MTA_REGISTERS_ICH8LAN 32
822 743
823/* IPv4 Address Table Entry */ 744/* IPv4 Address Table Entry */
824struct e1000_ipv4_at_entry { 745struct e1000_ipv4_at_entry {
825 volatile u32 ipv4_addr; /* IP Address (RW) */ 746 volatile u32 ipv4_addr; /* IP Address (RW) */
826 volatile u32 reserved; 747 volatile u32 reserved;
827}; 748};
828 749
829/* Four wakeup IP addresses are supported */ 750/* Four wakeup IP addresses are supported */
830#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 751#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
831#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 752#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
832#define E1000_IP4AT_SIZE_ICH8LAN 3
833#define E1000_IP6AT_SIZE 1 753#define E1000_IP6AT_SIZE 1
834 754
835/* IPv6 Address Table Entry */ 755/* IPv6 Address Table Entry */
836struct e1000_ipv6_at_entry { 756struct e1000_ipv6_at_entry {
837 volatile u8 ipv6_addr[16]; 757 volatile u8 ipv6_addr[16];
838}; 758};
839 759
840/* Flexible Filter Length Table Entry */ 760/* Flexible Filter Length Table Entry */
841struct e1000_fflt_entry { 761struct e1000_fflt_entry {
842 volatile u32 length; /* Flexible Filter Length (RW) */ 762 volatile u32 length; /* Flexible Filter Length (RW) */
843 volatile u32 reserved; 763 volatile u32 reserved;
844}; 764};
845 765
846/* Flexible Filter Mask Table Entry */ 766/* Flexible Filter Mask Table Entry */
847struct e1000_ffmt_entry { 767struct e1000_ffmt_entry {
848 volatile u32 mask; /* Flexible Filter Mask (RW) */ 768 volatile u32 mask; /* Flexible Filter Mask (RW) */
849 volatile u32 reserved; 769 volatile u32 reserved;
850}; 770};
851 771
852/* Flexible Filter Value Table Entry */ 772/* Flexible Filter Value Table Entry */
853struct e1000_ffvt_entry { 773struct e1000_ffvt_entry {
854 volatile u32 value; /* Flexible Filter Value (RW) */ 774 volatile u32 value; /* Flexible Filter Value (RW) */
855 volatile u32 reserved; 775 volatile u32 reserved;
856}; 776};
857 777
858/* Four Flexible Filters are supported */ 778/* Four Flexible Filters are supported */
@@ -879,211 +799,211 @@ struct e1000_ffvt_entry {
879 * R/clr - register is read only and is cleared when read 799 * R/clr - register is read only and is cleared when read
880 * A - register array 800 * A - register array
881 */ 801 */
882#define E1000_CTRL 0x00000 /* Device Control - RW */ 802#define E1000_CTRL 0x00000 /* Device Control - RW */
883#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 803#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
884#define E1000_STATUS 0x00008 /* Device Status - RO */ 804#define E1000_STATUS 0x00008 /* Device Status - RO */
885#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 805#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
886#define E1000_EERD 0x00014 /* EEPROM Read - RW */ 806#define E1000_EERD 0x00014 /* EEPROM Read - RW */
887#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 807#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
888#define E1000_FLA 0x0001C /* Flash Access - RW */ 808#define E1000_FLA 0x0001C /* Flash Access - RW */
889#define E1000_MDIC 0x00020 /* MDI Control - RW */ 809#define E1000_MDIC 0x00020 /* MDI Control - RW */
890#define E1000_SCTL 0x00024 /* SerDes Control - RW */ 810#define E1000_SCTL 0x00024 /* SerDes Control - RW */
891#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */ 811#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */
892#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 812#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
893#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 813#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
894#define E1000_FCT 0x00030 /* Flow Control Type - RW */ 814#define E1000_FCT 0x00030 /* Flow Control Type - RW */
895#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 815#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
896#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 816#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
897#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 817#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
898#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 818#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
899#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 819#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
900#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 820#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
901#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 821#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
902#define E1000_RCTL 0x00100 /* RX Control - RW */ 822#define E1000_RCTL 0x00100 /* RX Control - RW */
903#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */ 823#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */
904#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */ 824#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
905#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */ 825#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
906#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */ 826#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
907#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */ 827#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
908#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */ 828#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
909#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 829#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
910#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ 830#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
911#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ 831#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
912#define E1000_TCTL 0x00400 /* TX Control - RW */ 832#define E1000_TCTL 0x00400 /* TX Control - RW */
913#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ 833#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
914#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 834#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
915#define E1000_TBT 0x00448 /* TX Burst Timer - RW */ 835#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
916#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 836#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
917#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 837#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
918#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 838#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
919#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 839#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
920#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ 840#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
921#define FEXTNVM_SW_CONFIG 0x0001 841#define FEXTNVM_SW_CONFIG 0x0001
922#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 842#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
923#define E1000_PBS 0x01008 /* Packet Buffer Size */ 843#define E1000_PBS 0x01008 /* Packet Buffer Size */
924#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 844#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
925#define E1000_FLASH_UPDATES 1000 845#define E1000_FLASH_UPDATES 1000
926#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ 846#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
927#define E1000_FLASHT 0x01028 /* FLASH Timer Register */ 847#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
928#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ 848#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
929#define E1000_FLSWCTL 0x01030 /* FLASH control register */ 849#define E1000_FLSWCTL 0x01030 /* FLASH control register */
930#define E1000_FLSWDATA 0x01034 /* FLASH data register */ 850#define E1000_FLSWDATA 0x01034 /* FLASH data register */
931#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ 851#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
932#define E1000_FLOP 0x0103C /* FLASH Opcode Register */ 852#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
933#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ 853#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
934#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 854#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
935#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 855#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
936#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ 856#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
937#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ 857#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
938#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ 858#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
939#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ 859#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
940#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ 860#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
941#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ 861#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
942#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ 862#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
943#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */ 863#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
944#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */ 864#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */
945#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */ 865#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */
946#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ 866#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
947#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ 867#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
948#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ 868#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
949#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */ 869#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
950#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */ 870#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
951#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 871#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
952#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 872#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
953#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ 873#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
954#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 874#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
955#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ 875#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
956#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 876#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
957#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 877#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
958#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 878#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
959#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ 879#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
960#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ 880#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
961#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ 881#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
962#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ 882#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
963#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ 883#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
964#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ 884#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
965#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ 885#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
966#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ 886#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
967#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ 887#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
968#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ 888#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
969#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ 889#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
970#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ 890#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
971#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ 891#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
972#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ 892#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
973#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ 893#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
974#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ 894#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
975#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ 895#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
976#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ 896#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
977#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ 897#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
978#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 898#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
979#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 899#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
980#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 900#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
981#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 901#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
982#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 902#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
983#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 903#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
984#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 904#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
985#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 905#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
986#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 906#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
987#define E1000_COLC 0x04028 /* Collision Count - R/clr */ 907#define E1000_COLC 0x04028 /* Collision Count - R/clr */
988#define E1000_DC 0x04030 /* Defer Count - R/clr */ 908#define E1000_DC 0x04030 /* Defer Count - R/clr */
989#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ 909#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
990#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 910#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
991#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 911#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
992#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 912#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
993#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ 913#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
994#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ 914#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
995#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ 915#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
996#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ 916#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
997#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ 917#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
998#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ 918#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
999#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ 919#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
1000#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ 920#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
1001#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ 921#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
1002#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ 922#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
1003#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ 923#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
1004#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ 924#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
1005#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ 925#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
1006#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ 926#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
1007#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ 927#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
1008#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ 928#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
1009#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ 929#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
1010#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ 930#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
1011#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ 931#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
1012#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ 932#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
1013#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ 933#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
1014#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ 934#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
1015#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ 935#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
1016#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ 936#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
1017#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ 937#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
1018#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 938#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
1019#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ 939#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
1020#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ 940#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
1021#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ 941#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
1022#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ 942#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
1023#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ 943#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
1024#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ 944#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
1025#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ 945#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
1026#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ 946#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
1027#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ 947#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
1028#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ 948#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
1029#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ 949#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
1030#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ 950#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
1031#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ 951#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
1032#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ 952#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
1033#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ 953#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
1034#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ 954#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
1035#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ 955#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
1036#define E1000_IAC 0x04100 /* Interrupt Assertion Count */ 956#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
1037#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */ 957#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
1038#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */ 958#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
1039#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */ 959#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
1040#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */ 960#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
1041#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ 961#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
1042#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */ 962#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
1043#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ 963#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
1044#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ 964#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
1045#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ 965#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
1046#define E1000_RFCTL 0x05008 /* Receive Filter Control*/ 966#define E1000_RFCTL 0x05008 /* Receive Filter Control */
1047#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 967#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
1048#define E1000_RA 0x05400 /* Receive Address - RW Array */ 968#define E1000_RA 0x05400 /* Receive Address - RW Array */
1049#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 969#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
1050#define E1000_WUC 0x05800 /* Wakeup Control - RW */ 970#define E1000_WUC 0x05800 /* Wakeup Control - RW */
1051#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 971#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
1052#define E1000_WUS 0x05810 /* Wakeup Status - RO */ 972#define E1000_WUS 0x05810 /* Wakeup Status - RO */
1053#define E1000_MANC 0x05820 /* Management Control - RW */ 973#define E1000_MANC 0x05820 /* Management Control - RW */
1054#define E1000_IPAV 0x05838 /* IP Address Valid - RW */ 974#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
1055#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ 975#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
1056#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ 976#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
1057#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 977#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
1058#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ 978#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
1059#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 979#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
1060#define E1000_HOST_IF 0x08800 /* Host Interface */ 980#define E1000_HOST_IF 0x08800 /* Host Interface */
1061#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ 981#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
1062#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ 982#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
1063 983
1064#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 984#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
1065#define E1000_MDPHYA 0x0003C /* PHY address - RW */ 985#define E1000_MDPHYA 0x0003C /* PHY address - RW */
1066#define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */ 986#define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */
1067#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ 987#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
1068 988
1069#define E1000_GCR 0x05B00 /* PCI-Ex Control */ 989#define E1000_GCR 0x05B00 /* PCI-Ex Control */
1070#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ 990#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
1071#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ 991#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
1072#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ 992#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
1073#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ 993#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
1074#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 994#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
1075#define E1000_SWSM 0x05B50 /* SW Semaphore */ 995#define E1000_SWSM 0x05B50 /* SW Semaphore */
1076#define E1000_FWSM 0x05B54 /* FW Semaphore */ 996#define E1000_FWSM 0x05B54 /* FW Semaphore */
1077#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ 997#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
1078#define E1000_HICR 0x08F00 /* Host Inteface Control */ 998#define E1000_HICR 0x08F00 /* Host Interface Control */
1079 999
1080/* RSS registers */ 1000/* RSS registers */
1081#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ 1001#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
1082#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ 1002#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
1083#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */ 1003#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */
1084#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */ 1004#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */
1085#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ 1005#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
1086#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ 1006#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
1087/* Register Set (82542) 1007/* Register Set (82542)
1088 * 1008 *
1089 * Some of the 82542 registers are located at different offsets than they are 1009 * Some of the 82542 registers are located at different offsets than they are
@@ -1123,19 +1043,19 @@ struct e1000_ffvt_entry {
1123#define E1000_82542_RDLEN0 E1000_82542_RDLEN 1043#define E1000_82542_RDLEN0 E1000_82542_RDLEN
1124#define E1000_82542_RDH0 E1000_82542_RDH 1044#define E1000_82542_RDH0 E1000_82542_RDH
1125#define E1000_82542_RDT0 E1000_82542_RDT 1045#define E1000_82542_RDT0 E1000_82542_RDT
1126#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication 1046#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication
1127 * RX Control - RW */ 1047 * RX Control - RW */
1128#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8)) 1048#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
1129#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */ 1049#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */
1130#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */ 1050#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */
1131#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */ 1051#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */
1132#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */ 1052#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */
1133#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */ 1053#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */
1134#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */ 1054#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */
1135#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */ 1055#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */
1136#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */ 1056#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */
1137#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */ 1057#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */
1138#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */ 1058#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */
1139#define E1000_82542_RDTR1 0x00130 1059#define E1000_82542_RDTR1 0x00130
1140#define E1000_82542_RDBAL1 0x00138 1060#define E1000_82542_RDBAL1 0x00138
1141#define E1000_82542_RDBAH1 0x0013C 1061#define E1000_82542_RDBAH1 0x0013C
@@ -1302,288 +1222,281 @@ struct e1000_ffvt_entry {
1302#define E1000_82542_RSSIR E1000_RSSIR 1222#define E1000_82542_RSSIR E1000_RSSIR
1303#define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA 1223#define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA
1304#define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC 1224#define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC
1305#define E1000_82542_MANC2H E1000_MANC2H
1306 1225
1307/* Statistics counters collected by the MAC */ 1226/* Statistics counters collected by the MAC */
1308struct e1000_hw_stats { 1227struct e1000_hw_stats {
1309 u64 crcerrs; 1228 u64 crcerrs;
1310 u64 algnerrc; 1229 u64 algnerrc;
1311 u64 symerrs; 1230 u64 symerrs;
1312 u64 rxerrc; 1231 u64 rxerrc;
1313 u64 txerrc; 1232 u64 txerrc;
1314 u64 mpc; 1233 u64 mpc;
1315 u64 scc; 1234 u64 scc;
1316 u64 ecol; 1235 u64 ecol;
1317 u64 mcc; 1236 u64 mcc;
1318 u64 latecol; 1237 u64 latecol;
1319 u64 colc; 1238 u64 colc;
1320 u64 dc; 1239 u64 dc;
1321 u64 tncrs; 1240 u64 tncrs;
1322 u64 sec; 1241 u64 sec;
1323 u64 cexterr; 1242 u64 cexterr;
1324 u64 rlec; 1243 u64 rlec;
1325 u64 xonrxc; 1244 u64 xonrxc;
1326 u64 xontxc; 1245 u64 xontxc;
1327 u64 xoffrxc; 1246 u64 xoffrxc;
1328 u64 xofftxc; 1247 u64 xofftxc;
1329 u64 fcruc; 1248 u64 fcruc;
1330 u64 prc64; 1249 u64 prc64;
1331 u64 prc127; 1250 u64 prc127;
1332 u64 prc255; 1251 u64 prc255;
1333 u64 prc511; 1252 u64 prc511;
1334 u64 prc1023; 1253 u64 prc1023;
1335 u64 prc1522; 1254 u64 prc1522;
1336 u64 gprc; 1255 u64 gprc;
1337 u64 bprc; 1256 u64 bprc;
1338 u64 mprc; 1257 u64 mprc;
1339 u64 gptc; 1258 u64 gptc;
1340 u64 gorcl; 1259 u64 gorcl;
1341 u64 gorch; 1260 u64 gorch;
1342 u64 gotcl; 1261 u64 gotcl;
1343 u64 gotch; 1262 u64 gotch;
1344 u64 rnbc; 1263 u64 rnbc;
1345 u64 ruc; 1264 u64 ruc;
1346 u64 rfc; 1265 u64 rfc;
1347 u64 roc; 1266 u64 roc;
1348 u64 rlerrc; 1267 u64 rlerrc;
1349 u64 rjc; 1268 u64 rjc;
1350 u64 mgprc; 1269 u64 mgprc;
1351 u64 mgpdc; 1270 u64 mgpdc;
1352 u64 mgptc; 1271 u64 mgptc;
1353 u64 torl; 1272 u64 torl;
1354 u64 torh; 1273 u64 torh;
1355 u64 totl; 1274 u64 totl;
1356 u64 toth; 1275 u64 toth;
1357 u64 tpr; 1276 u64 tpr;
1358 u64 tpt; 1277 u64 tpt;
1359 u64 ptc64; 1278 u64 ptc64;
1360 u64 ptc127; 1279 u64 ptc127;
1361 u64 ptc255; 1280 u64 ptc255;
1362 u64 ptc511; 1281 u64 ptc511;
1363 u64 ptc1023; 1282 u64 ptc1023;
1364 u64 ptc1522; 1283 u64 ptc1522;
1365 u64 mptc; 1284 u64 mptc;
1366 u64 bptc; 1285 u64 bptc;
1367 u64 tsctc; 1286 u64 tsctc;
1368 u64 tsctfc; 1287 u64 tsctfc;
1369 u64 iac; 1288 u64 iac;
1370 u64 icrxptc; 1289 u64 icrxptc;
1371 u64 icrxatc; 1290 u64 icrxatc;
1372 u64 ictxptc; 1291 u64 ictxptc;
1373 u64 ictxatc; 1292 u64 ictxatc;
1374 u64 ictxqec; 1293 u64 ictxqec;
1375 u64 ictxqmtc; 1294 u64 ictxqmtc;
1376 u64 icrxdmtc; 1295 u64 icrxdmtc;
1377 u64 icrxoc; 1296 u64 icrxoc;
1378}; 1297};
1379 1298
1380/* Structure containing variables used by the shared code (e1000_hw.c) */ 1299/* Structure containing variables used by the shared code (e1000_hw.c) */
1381struct e1000_hw { 1300struct e1000_hw {
1382 u8 __iomem *hw_addr; 1301 u8 __iomem *hw_addr;
1383 u8 __iomem *flash_address; 1302 u8 __iomem *flash_address;
1384 e1000_mac_type mac_type; 1303 e1000_mac_type mac_type;
1385 e1000_phy_type phy_type; 1304 e1000_phy_type phy_type;
1386 u32 phy_init_script; 1305 u32 phy_init_script;
1387 e1000_media_type media_type; 1306 e1000_media_type media_type;
1388 void *back; 1307 void *back;
1389 struct e1000_shadow_ram *eeprom_shadow_ram; 1308 struct e1000_shadow_ram *eeprom_shadow_ram;
1390 u32 flash_bank_size; 1309 u32 flash_bank_size;
1391 u32 flash_base_addr; 1310 u32 flash_base_addr;
1392 e1000_fc_type fc; 1311 e1000_fc_type fc;
1393 e1000_bus_speed bus_speed; 1312 e1000_bus_speed bus_speed;
1394 e1000_bus_width bus_width; 1313 e1000_bus_width bus_width;
1395 e1000_bus_type bus_type; 1314 e1000_bus_type bus_type;
1396 struct e1000_eeprom_info eeprom; 1315 struct e1000_eeprom_info eeprom;
1397 e1000_ms_type master_slave; 1316 e1000_ms_type master_slave;
1398 e1000_ms_type original_master_slave; 1317 e1000_ms_type original_master_slave;
1399 e1000_ffe_config ffe_config_state; 1318 e1000_ffe_config ffe_config_state;
1400 u32 asf_firmware_present; 1319 u32 asf_firmware_present;
1401 u32 eeprom_semaphore_present; 1320 u32 eeprom_semaphore_present;
1402 u32 swfw_sync_present; 1321 unsigned long io_base;
1403 u32 swfwhw_semaphore_present; 1322 u32 phy_id;
1404 unsigned long io_base; 1323 u32 phy_revision;
1405 u32 phy_id; 1324 u32 phy_addr;
1406 u32 phy_revision; 1325 u32 original_fc;
1407 u32 phy_addr; 1326 u32 txcw;
1408 u32 original_fc; 1327 u32 autoneg_failed;
1409 u32 txcw; 1328 u32 max_frame_size;
1410 u32 autoneg_failed; 1329 u32 min_frame_size;
1411 u32 max_frame_size; 1330 u32 mc_filter_type;
1412 u32 min_frame_size; 1331 u32 num_mc_addrs;
1413 u32 mc_filter_type; 1332 u32 collision_delta;
1414 u32 num_mc_addrs; 1333 u32 tx_packet_delta;
1415 u32 collision_delta; 1334 u32 ledctl_default;
1416 u32 tx_packet_delta; 1335 u32 ledctl_mode1;
1417 u32 ledctl_default; 1336 u32 ledctl_mode2;
1418 u32 ledctl_mode1; 1337 bool tx_pkt_filtering;
1419 u32 ledctl_mode2;
1420 bool tx_pkt_filtering;
1421 struct e1000_host_mng_dhcp_cookie mng_cookie; 1338 struct e1000_host_mng_dhcp_cookie mng_cookie;
1422 u16 phy_spd_default; 1339 u16 phy_spd_default;
1423 u16 autoneg_advertised; 1340 u16 autoneg_advertised;
1424 u16 pci_cmd_word; 1341 u16 pci_cmd_word;
1425 u16 fc_high_water; 1342 u16 fc_high_water;
1426 u16 fc_low_water; 1343 u16 fc_low_water;
1427 u16 fc_pause_time; 1344 u16 fc_pause_time;
1428 u16 current_ifs_val; 1345 u16 current_ifs_val;
1429 u16 ifs_min_val; 1346 u16 ifs_min_val;
1430 u16 ifs_max_val; 1347 u16 ifs_max_val;
1431 u16 ifs_step_size; 1348 u16 ifs_step_size;
1432 u16 ifs_ratio; 1349 u16 ifs_ratio;
1433 u16 device_id; 1350 u16 device_id;
1434 u16 vendor_id; 1351 u16 vendor_id;
1435 u16 subsystem_id; 1352 u16 subsystem_id;
1436 u16 subsystem_vendor_id; 1353 u16 subsystem_vendor_id;
1437 u8 revision_id; 1354 u8 revision_id;
1438 u8 autoneg; 1355 u8 autoneg;
1439 u8 mdix; 1356 u8 mdix;
1440 u8 forced_speed_duplex; 1357 u8 forced_speed_duplex;
1441 u8 wait_autoneg_complete; 1358 u8 wait_autoneg_complete;
1442 u8 dma_fairness; 1359 u8 dma_fairness;
1443 u8 mac_addr[NODE_ADDRESS_SIZE]; 1360 u8 mac_addr[NODE_ADDRESS_SIZE];
1444 u8 perm_mac_addr[NODE_ADDRESS_SIZE]; 1361 u8 perm_mac_addr[NODE_ADDRESS_SIZE];
1445 bool disable_polarity_correction; 1362 bool disable_polarity_correction;
1446 bool speed_downgraded; 1363 bool speed_downgraded;
1447 e1000_smart_speed smart_speed; 1364 e1000_smart_speed smart_speed;
1448 e1000_dsp_config dsp_config_state; 1365 e1000_dsp_config dsp_config_state;
1449 bool get_link_status; 1366 bool get_link_status;
1450 bool serdes_link_down; 1367 bool serdes_has_link;
1451 bool tbi_compatibility_en; 1368 bool tbi_compatibility_en;
1452 bool tbi_compatibility_on; 1369 bool tbi_compatibility_on;
1453 bool laa_is_present; 1370 bool laa_is_present;
1454 bool phy_reset_disable; 1371 bool phy_reset_disable;
1455 bool initialize_hw_bits_disable; 1372 bool initialize_hw_bits_disable;
1456 bool fc_send_xon; 1373 bool fc_send_xon;
1457 bool fc_strict_ieee; 1374 bool fc_strict_ieee;
1458 bool report_tx_early; 1375 bool report_tx_early;
1459 bool adaptive_ifs; 1376 bool adaptive_ifs;
1460 bool ifs_params_forced; 1377 bool ifs_params_forced;
1461 bool in_ifs_mode; 1378 bool in_ifs_mode;
1462 bool mng_reg_access_disabled; 1379 bool mng_reg_access_disabled;
1463 bool leave_av_bit_off; 1380 bool leave_av_bit_off;
1464 bool kmrn_lock_loss_workaround_disabled; 1381 bool bad_tx_carr_stats_fd;
1465 bool bad_tx_carr_stats_fd; 1382 bool has_smbus;
1466 bool has_manc2h;
1467 bool rx_needs_kicking;
1468 bool has_smbus;
1469}; 1383};
1470 1384
1471 1385#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1472#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ 1386#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
1473#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ 1387#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
1474#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ 1388#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1475#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1389#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */
1476#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */ 1390#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1477#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1391#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */
1478#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */ 1392#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1479#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1480/* Register Bit Masks */ 1393/* Register Bit Masks */
1481/* Device Control */ 1394/* Device Control */
1482#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 1395#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1483#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 1396#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1484#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 1397#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1485#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 1398#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
1486#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 1399#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1487#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 1400#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1488#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 1401#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1489#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 1402#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1490#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 1403#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1491#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 1404#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1492#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 1405#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1493#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 1406#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1494#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 1407#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1495#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 1408#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1496#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 1409#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1497#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 1410#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1498#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 1411#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1499#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ 1412#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
1500#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ 1413#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
1501#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */ 1414#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
1502#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */ 1415#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
1503#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 1416#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1504#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 1417#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1505#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 1418#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1506#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 1419#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1507#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 1420#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1508#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ 1421#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1509#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 1422#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1510#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 1423#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1511#define E1000_CTRL_RST 0x04000000 /* Global reset */ 1424#define E1000_CTRL_RST 0x04000000 /* Global reset */
1512#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 1425#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1513#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 1426#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1514#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 1427#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1515#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 1428#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1516#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 1429#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1517#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */ 1430#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
1518 1431
1519/* Device Status */ 1432/* Device Status */
1520#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 1433#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1521#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 1434#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1522#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 1435#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
1523#define E1000_STATUS_FUNC_SHIFT 2 1436#define E1000_STATUS_FUNC_SHIFT 2
1524#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 1437#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1525#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 1438#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1526#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 1439#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1527#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ 1440#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1528#define E1000_STATUS_SPEED_MASK 0x000000C0 1441#define E1000_STATUS_SPEED_MASK 0x000000C0
1529#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 1442#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1530#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 1443#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1531#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 1444#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1532#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion 1445#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion
1533 by EEPROM/Flash */ 1446 by EEPROM/Flash */
1534#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 1447#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1535#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ 1448#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1536#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 1449#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
1537#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 1450#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1538#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 1451#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1539#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 1452#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1540#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 1453#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1541#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 1454#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1542#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ 1455#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
1543#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ 1456#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
1544#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ 1457#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
1545#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ 1458#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
1546#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */ 1459#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */
1547#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ 1460#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
1548#define E1000_STATUS_FUSE_8 0x04000000 1461#define E1000_STATUS_FUSE_8 0x04000000
1549#define E1000_STATUS_FUSE_9 0x08000000 1462#define E1000_STATUS_FUSE_9 0x08000000
1550#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ 1463#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
1551#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ 1464#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
1552 1465
1553/* Constants used to intrepret the masked PCI-X bus speed. */ 1466/* Constants used to interpret the masked PCI-X bus speed. */
1554#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ 1467#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1555#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ 1468#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1556#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ 1469#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1557 1470
1558/* EEPROM/Flash Control */ 1471/* EEPROM/Flash Control */
1559#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ 1472#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1560#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ 1473#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1561#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ 1474#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1562#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ 1475#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1563#define E1000_EECD_FWE_MASK 0x00000030 1476#define E1000_EECD_FWE_MASK 0x00000030
1564#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1477#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1565#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ 1478#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1566#define E1000_EECD_FWE_SHIFT 4 1479#define E1000_EECD_FWE_SHIFT 4
1567#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ 1480#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1568#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ 1481#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1569#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ 1482#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1570#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ 1483#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1571#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type 1484#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1572 * (0-small, 1-large) */ 1485 * (0-small, 1-large) */
1573#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ 1486#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1574#ifndef E1000_EEPROM_GRANT_ATTEMPTS 1487#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1575#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 1488#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1576#endif 1489#endif
1577#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ 1490#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1578#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ 1491#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
1579#define E1000_EECD_SIZE_EX_SHIFT 11 1492#define E1000_EECD_SIZE_EX_SHIFT 11
1580#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ 1493#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1581#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ 1494#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1582#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ 1495#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1583#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1496#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1584#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 1497#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1585#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ 1498#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1586#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1499#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1587#define E1000_EECD_SECVAL_SHIFT 22 1500#define E1000_EECD_SECVAL_SHIFT 22
1588#define E1000_STM_OPCODE 0xDB00 1501#define E1000_STM_OPCODE 0xDB00
1589#define E1000_HICR_FW_RESET 0xC0 1502#define E1000_HICR_FW_RESET 0xC0
@@ -1593,12 +1506,12 @@ struct e1000_hw {
1593#define E1000_ICH_NVM_SIG_MASK 0xC0 1506#define E1000_ICH_NVM_SIG_MASK 0xC0
1594 1507
1595/* EEPROM Read */ 1508/* EEPROM Read */
1596#define E1000_EERD_START 0x00000001 /* Start Read */ 1509#define E1000_EERD_START 0x00000001 /* Start Read */
1597#define E1000_EERD_DONE 0x00000010 /* Read Done */ 1510#define E1000_EERD_DONE 0x00000010 /* Read Done */
1598#define E1000_EERD_ADDR_SHIFT 8 1511#define E1000_EERD_ADDR_SHIFT 8
1599#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ 1512#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1600#define E1000_EERD_DATA_SHIFT 16 1513#define E1000_EERD_DATA_SHIFT 16
1601#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ 1514#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1602 1515
1603/* SPI EEPROM Status Register */ 1516/* SPI EEPROM Status Register */
1604#define EEPROM_STATUS_RDY_SPI 0x01 1517#define EEPROM_STATUS_RDY_SPI 0x01
@@ -1608,25 +1521,25 @@ struct e1000_hw {
1608#define EEPROM_STATUS_WPEN_SPI 0x80 1521#define EEPROM_STATUS_WPEN_SPI 0x80
1609 1522
1610/* Extended Device Control */ 1523/* Extended Device Control */
1611#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ 1524#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1612#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ 1525#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1613#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 1526#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1614#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ 1527#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1615#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ 1528#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1616#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ 1529#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
1617#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ 1530#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
1618#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 1531#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1619#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ 1532#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1620#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ 1533#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1621#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 1534#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1622#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ 1535#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1623#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 1536#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1624#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ 1537#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1625#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ 1538#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1626#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 1539#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1627#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ 1540#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1628#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 1541#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
1629#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 1542#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
1630#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 1543#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1631#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 1544#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1632#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 1545#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
@@ -1638,11 +1551,11 @@ struct e1000_hw {
1638#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 1551#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1639#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 1552#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1640#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 1553#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1641#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1554#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1642#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 1555#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1643#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 1556#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
1644#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */ 1557#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */
1645#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */ 1558#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */
1646#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 1559#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
1647 1560
1648/* MDI Control */ 1561/* MDI Control */
@@ -1742,167 +1655,167 @@ struct e1000_hw {
1742#define E1000_LEDCTL_MODE_LED_OFF 0xF 1655#define E1000_LEDCTL_MODE_LED_OFF 0xF
1743 1656
1744/* Receive Address */ 1657/* Receive Address */
1745#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 1658#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1746 1659
1747/* Interrupt Cause Read */ 1660/* Interrupt Cause Read */
1748#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 1661#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1749#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 1662#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1750#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 1663#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1751#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 1664#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1752#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 1665#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1753#define E1000_ICR_RXO 0x00000040 /* rx overrun */ 1666#define E1000_ICR_RXO 0x00000040 /* rx overrun */
1754#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 1667#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1755#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 1668#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1756#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ 1669#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1757#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 1670#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1758#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 1671#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1759#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 1672#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1760#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 1673#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1761#define E1000_ICR_TXD_LOW 0x00008000 1674#define E1000_ICR_TXD_LOW 0x00008000
1762#define E1000_ICR_SRPD 0x00010000 1675#define E1000_ICR_SRPD 0x00010000
1763#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ 1676#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
1764#define E1000_ICR_MNG 0x00040000 /* Manageability event */ 1677#define E1000_ICR_MNG 0x00040000 /* Manageability event */
1765#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ 1678#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
1766#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ 1679#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
1767#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */ 1680#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
1768#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */ 1681#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */
1769#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */ 1682#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */
1770#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ 1683#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
1771#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ 1684#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
1772#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ 1685#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
1773#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ 1686#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
1774#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */ 1687#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
1775#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ 1688#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
1776#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ 1689#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */
1777 1690
1778/* Interrupt Cause Set */ 1691/* Interrupt Cause Set */
1779#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1692#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1780#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1693#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1781#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 1694#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1782#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1695#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1783#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1696#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1784#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ 1697#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1785#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1698#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1786#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1699#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1787#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1700#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1788#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1701#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1789#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1702#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1790#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1703#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1791#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1704#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1792#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 1705#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1793#define E1000_ICS_SRPD E1000_ICR_SRPD 1706#define E1000_ICS_SRPD E1000_ICR_SRPD
1794#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ 1707#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
1795#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ 1708#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
1796#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1709#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1797#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1710#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1798#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1711#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1799#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1712#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1800#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1713#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1801#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1714#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1802#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1715#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1803#define E1000_ICS_DSW E1000_ICR_DSW 1716#define E1000_ICS_DSW E1000_ICR_DSW
1804#define E1000_ICS_PHYINT E1000_ICR_PHYINT 1717#define E1000_ICS_PHYINT E1000_ICR_PHYINT
1805#define E1000_ICS_EPRST E1000_ICR_EPRST 1718#define E1000_ICS_EPRST E1000_ICR_EPRST
1806 1719
1807/* Interrupt Mask Set */ 1720/* Interrupt Mask Set */
1808#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1721#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1809#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1722#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1810#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 1723#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1811#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1724#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1812#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1725#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1813#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ 1726#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1814#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1727#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1815#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1728#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1816#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1729#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1817#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1730#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1818#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1731#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1819#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1732#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1820#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1733#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1821#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 1734#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1822#define E1000_IMS_SRPD E1000_ICR_SRPD 1735#define E1000_IMS_SRPD E1000_ICR_SRPD
1823#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ 1736#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
1824#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ 1737#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
1825#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1738#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1826#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1739#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1827#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1740#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1828#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1741#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1829#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1742#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1830#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1743#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1831#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1744#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1832#define E1000_IMS_DSW E1000_ICR_DSW 1745#define E1000_IMS_DSW E1000_ICR_DSW
1833#define E1000_IMS_PHYINT E1000_ICR_PHYINT 1746#define E1000_IMS_PHYINT E1000_ICR_PHYINT
1834#define E1000_IMS_EPRST E1000_ICR_EPRST 1747#define E1000_IMS_EPRST E1000_ICR_EPRST
1835 1748
1836/* Interrupt Mask Clear */ 1749/* Interrupt Mask Clear */
1837#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1750#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1838#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1751#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1839#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ 1752#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1840#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1753#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1841#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1754#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1842#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ 1755#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1843#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1756#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1844#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1757#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1845#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1758#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1846#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1759#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1847#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1760#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1848#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1761#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1849#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1762#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1850#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW 1763#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1851#define E1000_IMC_SRPD E1000_ICR_SRPD 1764#define E1000_IMC_SRPD E1000_ICR_SRPD
1852#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */ 1765#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */
1853#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */ 1766#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */
1854#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1767#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */
1855#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1768#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1856#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1769#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1857#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1770#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1858#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1771#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1859#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1772#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1860#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1773#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1861#define E1000_IMC_DSW E1000_ICR_DSW 1774#define E1000_IMC_DSW E1000_ICR_DSW
1862#define E1000_IMC_PHYINT E1000_ICR_PHYINT 1775#define E1000_IMC_PHYINT E1000_ICR_PHYINT
1863#define E1000_IMC_EPRST E1000_ICR_EPRST 1776#define E1000_IMC_EPRST E1000_ICR_EPRST
1864 1777
1865/* Receive Control */ 1778/* Receive Control */
1866#define E1000_RCTL_RST 0x00000001 /* Software reset */ 1779#define E1000_RCTL_RST 0x00000001 /* Software reset */
1867#define E1000_RCTL_EN 0x00000002 /* enable */ 1780#define E1000_RCTL_EN 0x00000002 /* enable */
1868#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 1781#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1869#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 1782#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1870#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 1783#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1871#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 1784#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1872#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 1785#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1873#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 1786#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1874#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 1787#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1875#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 1788#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1876#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ 1789#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
1877#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 1790#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
1878#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 1791#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1879#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ 1792#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1880#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ 1793#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1881#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 1794#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1882#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ 1795#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1883#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ 1796#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1884#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ 1797#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1885#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 1798#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1886#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ 1799#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1887#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 1800#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1888/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 1801/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1889#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ 1802#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1890#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ 1803#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1891#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 1804#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1892#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 1805#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1893/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 1806/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1894#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ 1807#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1895#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ 1808#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1896#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ 1809#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1897#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 1810#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1898#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 1811#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1899#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 1812#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1900#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 1813#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1901#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 1814#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1902#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 1815#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1903#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 1816#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
1904#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ 1817#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
1905#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ 1818#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
1906 1819
1907/* Use byte values for the following shift parameters 1820/* Use byte values for the following shift parameters
1908 * Usage: 1821 * Usage:
@@ -1925,10 +1838,10 @@ struct e1000_hw {
1925#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 1838#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1926#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 1839#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1927 1840
1928#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 1841#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
1929#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 1842#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
1930#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 1843#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
1931#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 1844#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
1932 1845
1933/* SW_W_SYNC definitions */ 1846/* SW_W_SYNC definitions */
1934#define E1000_SWFW_EEP_SM 0x0001 1847#define E1000_SWFW_EEP_SM 0x0001
@@ -1937,17 +1850,17 @@ struct e1000_hw {
1937#define E1000_SWFW_MAC_CSR_SM 0x0008 1850#define E1000_SWFW_MAC_CSR_SM 0x0008
1938 1851
1939/* Receive Descriptor */ 1852/* Receive Descriptor */
1940#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ 1853#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1941#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ 1854#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1942#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ 1855#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1943#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ 1856#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1944#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ 1857#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1945 1858
1946/* Flow Control */ 1859/* Flow Control */
1947#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 1860#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1948#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ 1861#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1949#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 1862#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1950#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 1863#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1951 1864
1952/* Header split receive */ 1865/* Header split receive */
1953#define E1000_RFCTL_ISCSI_DIS 0x00000001 1866#define E1000_RFCTL_ISCSI_DIS 0x00000001
@@ -1967,66 +1880,64 @@ struct e1000_hw {
1967#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 1880#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1968 1881
1969/* Receive Descriptor Control */ 1882/* Receive Descriptor Control */
1970#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ 1883#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1971#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ 1884#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1972#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ 1885#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1973#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ 1886#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1974 1887
1975/* Transmit Descriptor Control */ 1888/* Transmit Descriptor Control */
1976#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 1889#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
1977#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 1890#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
1978#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 1891#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
1979#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 1892#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1980#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ 1893#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1981#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 1894#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1982#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. 1895#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1983 still to be processed. */ 1896 still to be processed. */
1984/* Transmit Configuration Word */ 1897/* Transmit Configuration Word */
1985#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 1898#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1986#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ 1899#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1987#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 1900#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1988#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 1901#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1989#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 1902#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1990#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ 1903#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1991#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ 1904#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1992#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ 1905#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1993#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ 1906#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1994#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 1907#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1995 1908
1996/* Receive Configuration Word */ 1909/* Receive Configuration Word */
1997#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 1910#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1998#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ 1911#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1999#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 1912#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
2000#define E1000_RXCW_CC 0x10000000 /* Receive config change */ 1913#define E1000_RXCW_CC 0x10000000 /* Receive config change */
2001#define E1000_RXCW_C 0x20000000 /* Receive config */ 1914#define E1000_RXCW_C 0x20000000 /* Receive config */
2002#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 1915#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
2003#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ 1916#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
2004 1917
2005/* Transmit Control */ 1918/* Transmit Control */
2006#define E1000_TCTL_RST 0x00000001 /* software reset */ 1919#define E1000_TCTL_RST 0x00000001 /* software reset */
2007#define E1000_TCTL_EN 0x00000002 /* enable tx */ 1920#define E1000_TCTL_EN 0x00000002 /* enable tx */
2008#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ 1921#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
2009#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 1922#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
2010#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 1923#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
2011#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 1924#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
2012#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ 1925#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
2013#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 1926#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
2014#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 1927#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
2015#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 1928#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
2016#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 1929#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
2017/* Extended Transmit Control */ 1930/* Extended Transmit Control */
2018#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ 1931#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
2019#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ 1932#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
2020
2021#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
2022 1933
2023/* Receive Checksum Control */ 1934/* Receive Checksum Control */
2024#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ 1935#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
2025#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 1936#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
2026#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 1937#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
2027#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ 1938#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
2028#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 1939#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
2029#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 1940#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
2030 1941
2031/* Multiple Receive Queue Control */ 1942/* Multiple Receive Queue Control */
2032#define E1000_MRQC_ENABLE_MASK 0x00000003 1943#define E1000_MRQC_ENABLE_MASK 0x00000003
@@ -2042,141 +1953,141 @@ struct e1000_hw {
2042 1953
2043/* Definitions for power management and wakeup registers */ 1954/* Definitions for power management and wakeup registers */
2044/* Wake Up Control */ 1955/* Wake Up Control */
2045#define E1000_WUC_APME 0x00000001 /* APM Enable */ 1956#define E1000_WUC_APME 0x00000001 /* APM Enable */
2046#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 1957#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
2047#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 1958#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
2048#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 1959#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
2049#define E1000_WUC_SPM 0x80000000 /* Enable SPM */ 1960#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
2050 1961
2051/* Wake Up Filter Control */ 1962/* Wake Up Filter Control */
2052#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 1963#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
2053#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 1964#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
2054#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 1965#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
2055#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 1966#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
2056#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 1967#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
2057#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 1968#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
2058#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 1969#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
2059#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 1970#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
2060#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 1971#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
2061#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 1972#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
2062#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 1973#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
2063#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 1974#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
2064#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 1975#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
2065#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ 1976#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
2066#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 1977#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
2067#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 1978#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
2068 1979
2069/* Wake Up Status */ 1980/* Wake Up Status */
2070#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ 1981#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
2071#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ 1982#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
2072#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ 1983#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
2073#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ 1984#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
2074#define E1000_WUS_BC 0x00000010 /* Broadcast Received */ 1985#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
2075#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ 1986#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
2076#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ 1987#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
2077#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ 1988#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
2078#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ 1989#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
2079#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ 1990#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
2080#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ 1991#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
2081#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ 1992#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
2082#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 1993#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
2083 1994
2084/* Management Control */ 1995/* Management Control */
2085#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 1996#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
2086#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 1997#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
2087#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ 1998#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
2088#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ 1999#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
2089#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ 2000#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
2090#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ 2001#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
2091#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ 2002#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
2092#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ 2003#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
2093#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 2004#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
2094#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery 2005#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
2095 * Filtering */ 2006 * Filtering */
2096#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ 2007#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
2097#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 2008#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
2098#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 2009#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
2099#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 2010#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
2100#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ 2011#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
2101#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 2012#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
2102#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address 2013#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
2103 * filtering */ 2014 * filtering */
2104#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host 2015#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
2105 * memory */ 2016 * memory */
2106#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address 2017#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
2107 * filtering */ 2018 * filtering */
2108#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ 2019#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
2109#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ 2020#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
2110#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 2021#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
2111#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 2022#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
2112#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 2023#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
2113#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ 2024#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
2114#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ 2025#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
2115#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ 2026#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
2116 2027
2117#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 2028#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
2118#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 2029#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
2119 2030
2120/* SW Semaphore Register */ 2031/* SW Semaphore Register */
2121#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 2032#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
2122#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 2033#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
2123#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 2034#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
2124#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 2035#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
2125 2036
2126/* FW Semaphore Register */ 2037/* FW Semaphore Register */
2127#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */ 2038#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
2128#define E1000_FWSM_MODE_SHIFT 1 2039#define E1000_FWSM_MODE_SHIFT 1
2129#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ 2040#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
2130 2041
2131#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */ 2042#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
2132#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */ 2043#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
2133#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */ 2044#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
2134#define E1000_FWSM_SKUEL_SHIFT 29 2045#define E1000_FWSM_SKUEL_SHIFT 29
2135#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */ 2046#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
2136#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */ 2047#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
2137#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */ 2048#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
2138#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */ 2049#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
2139 2050
2140/* FFLT Debug Register */ 2051/* FFLT Debug Register */
2141#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */ 2052#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
2142 2053
2143typedef enum { 2054typedef enum {
2144 e1000_mng_mode_none = 0, 2055 e1000_mng_mode_none = 0,
2145 e1000_mng_mode_asf, 2056 e1000_mng_mode_asf,
2146 e1000_mng_mode_pt, 2057 e1000_mng_mode_pt,
2147 e1000_mng_mode_ipmi, 2058 e1000_mng_mode_ipmi,
2148 e1000_mng_mode_host_interface_only 2059 e1000_mng_mode_host_interface_only
2149} e1000_mng_mode; 2060} e1000_mng_mode;
2150 2061
2151/* Host Inteface Control Register */ 2062/* Host Interface Control Register */
2152#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */ 2063#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
2153#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done 2064#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done
2154 * to put command in RAM */ 2065 * to put command in RAM */
2155#define E1000_HICR_SV 0x00000004 /* Status Validity */ 2066#define E1000_HICR_SV 0x00000004 /* Status Validity */
2156#define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */ 2067#define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */
2157 2068
2158/* Host Interface Command Interface - Address range 0x8800-0x8EFF */ 2069/* Host Interface Command Interface - Address range 0x8800-0x8EFF */
2159#define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */ 2070#define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */
2160#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */ 2071#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */
2161#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */ 2072#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */
2162#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */ 2073#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
2163 2074
2164struct e1000_host_command_header { 2075struct e1000_host_command_header {
2165 u8 command_id; 2076 u8 command_id;
2166 u8 command_length; 2077 u8 command_length;
2167 u8 command_options; /* I/F bits for command, status for return */ 2078 u8 command_options; /* I/F bits for command, status for return */
2168 u8 checksum; 2079 u8 checksum;
2169}; 2080};
2170struct e1000_host_command_info { 2081struct e1000_host_command_info {
2171 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ 2082 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
2172 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */ 2083 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
2173}; 2084};
2174 2085
2175/* Host SMB register #0 */ 2086/* Host SMB register #0 */
2176#define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */ 2087#define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */
2177#define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */ 2088#define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */
2178#define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */ 2089#define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */
2179#define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */ 2090#define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */
2180 2091
2181/* Host SMB register #1 */ 2092/* Host SMB register #1 */
2182#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN 2093#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN
@@ -2185,10 +2096,10 @@ struct e1000_host_command_info {
2185#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT 2096#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT
2186 2097
2187/* FW Status Register */ 2098/* FW Status Register */
2188#define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */ 2099#define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */
2189 2100
2190/* Wake Up Packet Length */ 2101/* Wake Up Packet Length */
2191#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ 2102#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
2192 2103
2193#define E1000_MDALIGN 4096 2104#define E1000_MDALIGN 4096
2194 2105
@@ -2242,24 +2153,24 @@ struct e1000_host_command_info {
2242#define PCI_EX_LINK_WIDTH_SHIFT 4 2153#define PCI_EX_LINK_WIDTH_SHIFT 4
2243 2154
2244/* EEPROM Commands - Microwire */ 2155/* EEPROM Commands - Microwire */
2245#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ 2156#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
2246#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ 2157#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
2247#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ 2158#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
2248#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ 2159#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
2249#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ 2160#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erase/write disable */
2250 2161
2251/* EEPROM Commands - SPI */ 2162/* EEPROM Commands - SPI */
2252#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 2163#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
2253#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 2164#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
2254#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 2165#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
2255#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 2166#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
2256#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */ 2167#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
2257#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */ 2168#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
2258#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */ 2169#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
2259#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */ 2170#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
2260#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 2171#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
2261#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 2172#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
2262#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 2173#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
2263 2174
2264/* EEPROM Size definitions */ 2175/* EEPROM Size definitions */
2265#define EEPROM_WORD_SIZE_SHIFT 6 2176#define EEPROM_WORD_SIZE_SHIFT 6
@@ -2270,7 +2181,7 @@ struct e1000_host_command_info {
2270#define EEPROM_COMPAT 0x0003 2181#define EEPROM_COMPAT 0x0003
2271#define EEPROM_ID_LED_SETTINGS 0x0004 2182#define EEPROM_ID_LED_SETTINGS 0x0004
2272#define EEPROM_VERSION 0x0005 2183#define EEPROM_VERSION 0x0005
2273#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ 2184#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
2274#define EEPROM_PHY_CLASS_WORD 0x0007 2185#define EEPROM_PHY_CLASS_WORD 0x0007
2275#define EEPROM_INIT_CONTROL1_REG 0x000A 2186#define EEPROM_INIT_CONTROL1_REG 0x000A
2276#define EEPROM_INIT_CONTROL2_REG 0x000F 2187#define EEPROM_INIT_CONTROL2_REG 0x000F
@@ -2283,22 +2194,16 @@ struct e1000_host_command_info {
2283#define EEPROM_FLASH_VERSION 0x0032 2194#define EEPROM_FLASH_VERSION 0x0032
2284#define EEPROM_CHECKSUM_REG 0x003F 2195#define EEPROM_CHECKSUM_REG 0x003F
2285 2196
2286#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ 2197#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
2287#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ 2198#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
2288 2199
2289/* Word definitions for ID LED Settings */ 2200/* Word definitions for ID LED Settings */
2290#define ID_LED_RESERVED_0000 0x0000 2201#define ID_LED_RESERVED_0000 0x0000
2291#define ID_LED_RESERVED_FFFF 0xFFFF 2202#define ID_LED_RESERVED_FFFF 0xFFFF
2292#define ID_LED_RESERVED_82573 0xF746
2293#define ID_LED_DEFAULT_82573 0x1811
2294#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 2203#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
2295 (ID_LED_OFF1_OFF2 << 8) | \ 2204 (ID_LED_OFF1_OFF2 << 8) | \
2296 (ID_LED_DEF1_DEF2 << 4) | \ 2205 (ID_LED_DEF1_DEF2 << 4) | \
2297 (ID_LED_DEF1_DEF2)) 2206 (ID_LED_DEF1_DEF2))
2298#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
2299 (ID_LED_DEF1_OFF2 << 8) | \
2300 (ID_LED_DEF1_ON2 << 4) | \
2301 (ID_LED_DEF1_DEF2))
2302#define ID_LED_DEF1_DEF2 0x1 2207#define ID_LED_DEF1_DEF2 0x1
2303#define ID_LED_DEF1_ON2 0x2 2208#define ID_LED_DEF1_ON2 0x2
2304#define ID_LED_DEF1_OFF2 0x3 2209#define ID_LED_DEF1_OFF2 0x3
@@ -2313,7 +2218,6 @@ struct e1000_host_command_info {
2313#define IGP_ACTIVITY_LED_ENABLE 0x0300 2218#define IGP_ACTIVITY_LED_ENABLE 0x0300
2314#define IGP_LED3_MODE 0x07000000 2219#define IGP_LED3_MODE 0x07000000
2315 2220
2316
2317/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */ 2221/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
2318#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F 2222#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
2319 2223
@@ -2384,11 +2288,8 @@ struct e1000_host_command_info {
2384 2288
2385#define DEFAULT_82542_TIPG_IPGR2 10 2289#define DEFAULT_82542_TIPG_IPGR2 10
2386#define DEFAULT_82543_TIPG_IPGR2 6 2290#define DEFAULT_82543_TIPG_IPGR2 6
2387#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
2388#define E1000_TIPG_IPGR2_SHIFT 20 2291#define E1000_TIPG_IPGR2_SHIFT 20
2389 2292
2390#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
2391#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008
2392#define E1000_TXDMAC_DPP 0x00000001 2293#define E1000_TXDMAC_DPP 0x00000001
2393 2294
2394/* Adaptive IFS defines */ 2295/* Adaptive IFS defines */
@@ -2421,9 +2322,9 @@ struct e1000_host_command_info {
2421#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 2322#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
2422 2323
2423/* PBA constants */ 2324/* PBA constants */
2424#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */ 2325#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */
2425#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ 2326#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
2426#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 2327#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
2427#define E1000_PBA_20K 0x0014 2328#define E1000_PBA_20K 0x0014
2428#define E1000_PBA_22K 0x0016 2329#define E1000_PBA_22K 0x0016
2429#define E1000_PBA_24K 0x0018 2330#define E1000_PBA_24K 0x0018
@@ -2432,7 +2333,7 @@ struct e1000_host_command_info {
2432#define E1000_PBA_34K 0x0022 2333#define E1000_PBA_34K 0x0022
2433#define E1000_PBA_38K 0x0026 2334#define E1000_PBA_38K 0x0026
2434#define E1000_PBA_40K 0x0028 2335#define E1000_PBA_40K 0x0028
2435#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ 2336#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2436 2337
2437#define E1000_PBS_16K E1000_PBA_16K 2338#define E1000_PBS_16K E1000_PBA_16K
2438 2339
@@ -2442,9 +2343,9 @@ struct e1000_host_command_info {
2442#define FLOW_CONTROL_TYPE 0x8808 2343#define FLOW_CONTROL_TYPE 0x8808
2443 2344
2444/* The historical defaults for the flow control values are given below. */ 2345/* The historical defaults for the flow control values are given below. */
2445#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ 2346#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
2446#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ 2347#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
2447#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ 2348#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
2448 2349
2449/* PCIX Config space */ 2350/* PCIX Config space */
2450#define PCIX_COMMAND_REGISTER 0xE6 2351#define PCIX_COMMAND_REGISTER 0xE6
@@ -2458,7 +2359,6 @@ struct e1000_host_command_info {
2458#define PCIX_STATUS_HI_MMRBC_4K 0x3 2359#define PCIX_STATUS_HI_MMRBC_4K 0x3
2459#define PCIX_STATUS_HI_MMRBC_2K 0x2 2360#define PCIX_STATUS_HI_MMRBC_2K 0x2
2460 2361
2461
2462/* Number of bits required to shift right the "pause" bits from the 2362/* Number of bits required to shift right the "pause" bits from the
2463 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register. 2363 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
2464 */ 2364 */
@@ -2479,14 +2379,11 @@ struct e1000_host_command_info {
2479 */ 2379 */
2480#define ILOS_SHIFT 3 2380#define ILOS_SHIFT 3
2481 2381
2482
2483#define RECEIVE_BUFFER_ALIGN_SIZE (256) 2382#define RECEIVE_BUFFER_ALIGN_SIZE (256)
2484 2383
2485/* Number of milliseconds we wait for auto-negotiation to complete */ 2384/* Number of milliseconds we wait for auto-negotiation to complete */
2486#define LINK_UP_TIMEOUT 500 2385#define LINK_UP_TIMEOUT 500
2487 2386
2488/* Number of 100 microseconds we wait for PCI Express master disable */
2489#define MASTER_DISABLE_TIMEOUT 800
2490/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */ 2387/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2491#define AUTO_READ_DONE_TIMEOUT 10 2388#define AUTO_READ_DONE_TIMEOUT 10
2492/* Number of milliseconds we wait for PHY configuration done after MAC reset */ 2389/* Number of milliseconds we wait for PHY configuration done after MAC reset */
@@ -2534,7 +2431,6 @@ struct e1000_host_command_info {
2534 (((length) > (adapter)->min_frame_size) && \ 2431 (((length) > (adapter)->min_frame_size) && \
2535 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) 2432 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
2536 2433
2537
2538/* Structures, enums, and macros for the PHY */ 2434/* Structures, enums, and macros for the PHY */
2539 2435
2540/* Bit definitions for the Management Data IO (MDIO) and Management Data 2436/* Bit definitions for the Management Data IO (MDIO) and Management Data
@@ -2551,49 +2447,49 @@ struct e1000_host_command_info {
2551 2447
2552/* PHY 1000 MII Register/Bit Definitions */ 2448/* PHY 1000 MII Register/Bit Definitions */
2553/* PHY Registers defined by IEEE */ 2449/* PHY Registers defined by IEEE */
2554#define PHY_CTRL 0x00 /* Control Register */ 2450#define PHY_CTRL 0x00 /* Control Register */
2555#define PHY_STATUS 0x01 /* Status Regiser */ 2451#define PHY_STATUS 0x01 /* Status Register */
2556#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 2452#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
2557#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 2453#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
2558#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 2454#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
2559#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 2455#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
2560#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 2456#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
2561#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ 2457#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
2562#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 2458#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
2563#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 2459#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
2564#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 2460#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
2565#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 2461#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
2566 2462
2567#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 2463#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
2568#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */ 2464#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
2569 2465
2570/* M88E1000 Specific Registers */ 2466/* M88E1000 Specific Registers */
2571#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 2467#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
2572#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 2468#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
2573#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ 2469#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
2574#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ 2470#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
2575#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 2471#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
2576#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 2472#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
2577 2473
2578#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 2474#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
2579#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 2475#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
2580#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 2476#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
2581#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 2477#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
2582#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 2478#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
2583 2479
2584#define IGP01E1000_IEEE_REGS_PAGE 0x0000 2480#define IGP01E1000_IEEE_REGS_PAGE 0x0000
2585#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 2481#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
2586#define IGP01E1000_IEEE_FORCE_GIGA 0x0140 2482#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
2587 2483
2588/* IGP01E1000 Specific Registers */ 2484/* IGP01E1000 Specific Registers */
2589#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ 2485#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
2590#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ 2486#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
2591#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ 2487#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
2592#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ 2488#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
2593#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ 2489#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
2594#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ 2490#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
2595#define IGP02E1000_PHY_POWER_MGMT 0x19 2491#define IGP02E1000_PHY_POWER_MGMT 0x19
2596#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ 2492#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
2597 2493
2598/* IGP01E1000 AGC Registers - stores the cable length values*/ 2494/* IGP01E1000 AGC Registers - stores the cable length values*/
2599#define IGP01E1000_PHY_AGC_A 0x1172 2495#define IGP01E1000_PHY_AGC_A 0x1172
@@ -2636,192 +2532,119 @@ struct e1000_host_command_info {
2636 2532
2637#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 2533#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
2638 2534
2639/* Bits...
2640 * 15-5: page
2641 * 4-0: register offset
2642 */
2643#define GG82563_PAGE_SHIFT 5
2644#define GG82563_REG(page, reg) \
2645 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2646#define GG82563_MIN_ALT_REG 30
2647
2648/* GG82563 Specific Registers */
2649#define GG82563_PHY_SPEC_CTRL \
2650 GG82563_REG(0, 16) /* PHY Specific Control */
2651#define GG82563_PHY_SPEC_STATUS \
2652 GG82563_REG(0, 17) /* PHY Specific Status */
2653#define GG82563_PHY_INT_ENABLE \
2654 GG82563_REG(0, 18) /* Interrupt Enable */
2655#define GG82563_PHY_SPEC_STATUS_2 \
2656 GG82563_REG(0, 19) /* PHY Specific Status 2 */
2657#define GG82563_PHY_RX_ERR_CNTR \
2658 GG82563_REG(0, 21) /* Receive Error Counter */
2659#define GG82563_PHY_PAGE_SELECT \
2660 GG82563_REG(0, 22) /* Page Select */
2661#define GG82563_PHY_SPEC_CTRL_2 \
2662 GG82563_REG(0, 26) /* PHY Specific Control 2 */
2663#define GG82563_PHY_PAGE_SELECT_ALT \
2664 GG82563_REG(0, 29) /* Alternate Page Select */
2665#define GG82563_PHY_TEST_CLK_CTRL \
2666 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
2667
2668#define GG82563_PHY_MAC_SPEC_CTRL \
2669 GG82563_REG(2, 21) /* MAC Specific Control Register */
2670#define GG82563_PHY_MAC_SPEC_CTRL_2 \
2671 GG82563_REG(2, 26) /* MAC Specific Control 2 */
2672
2673#define GG82563_PHY_DSP_DISTANCE \
2674 GG82563_REG(5, 26) /* DSP Distance */
2675
2676/* Page 193 - Port Control Registers */
2677#define GG82563_PHY_KMRN_MODE_CTRL \
2678 GG82563_REG(193, 16) /* Kumeran Mode Control */
2679#define GG82563_PHY_PORT_RESET \
2680 GG82563_REG(193, 17) /* Port Reset */
2681#define GG82563_PHY_REVISION_ID \
2682 GG82563_REG(193, 18) /* Revision ID */
2683#define GG82563_PHY_DEVICE_ID \
2684 GG82563_REG(193, 19) /* Device ID */
2685#define GG82563_PHY_PWR_MGMT_CTRL \
2686 GG82563_REG(193, 20) /* Power Management Control */
2687#define GG82563_PHY_RATE_ADAPT_CTRL \
2688 GG82563_REG(193, 25) /* Rate Adaptation Control */
2689
2690/* Page 194 - KMRN Registers */
2691#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
2692 GG82563_REG(194, 16) /* FIFO's Control/Status */
2693#define GG82563_PHY_KMRN_CTRL \
2694 GG82563_REG(194, 17) /* Control */
2695#define GG82563_PHY_INBAND_CTRL \
2696 GG82563_REG(194, 18) /* Inband Control */
2697#define GG82563_PHY_KMRN_DIAGNOSTIC \
2698 GG82563_REG(194, 19) /* Diagnostic */
2699#define GG82563_PHY_ACK_TIMEOUTS \
2700 GG82563_REG(194, 20) /* Acknowledge Timeouts */
2701#define GG82563_PHY_ADV_ABILITY \
2702 GG82563_REG(194, 21) /* Advertised Ability */
2703#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
2704 GG82563_REG(194, 23) /* Link Partner Advertised Ability */
2705#define GG82563_PHY_ADV_NEXT_PAGE \
2706 GG82563_REG(194, 24) /* Advertised Next Page */
2707#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
2708 GG82563_REG(194, 25) /* Link Partner Advertised Next page */
2709#define GG82563_PHY_KMRN_MISC \
2710 GG82563_REG(194, 26) /* Misc. */
2711
2712/* PHY Control Register */ 2535/* PHY Control Register */
2713#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 2536#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
2714#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 2537#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
2715#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 2538#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
2716#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 2539#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
2717#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 2540#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
2718#define MII_CR_POWER_DOWN 0x0800 /* Power down */ 2541#define MII_CR_POWER_DOWN 0x0800 /* Power down */
2719#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 2542#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
2720#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 2543#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
2721#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 2544#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
2722#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 2545#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
2723 2546
2724/* PHY Status Register */ 2547/* PHY Status Register */
2725#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 2548#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
2726#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 2549#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
2727#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 2550#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
2728#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 2551#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
2729#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 2552#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
2730#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 2553#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
2731#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 2554#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
2732#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 2555#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
2733#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 2556#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
2734#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 2557#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
2735#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 2558#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
2736#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 2559#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
2737#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 2560#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
2738#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 2561#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
2739#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 2562#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
2740 2563
2741/* Autoneg Advertisement Register */ 2564/* Autoneg Advertisement Register */
2742#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 2565#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
2743#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 2566#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
2744#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 2567#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
2745#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 2568#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
2746#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 2569#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
2747#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 2570#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
2748#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 2571#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
2749#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 2572#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
2750#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 2573#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
2751#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 2574#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2752 2575
2753/* Link Partner Ability Register (Base Page) */ 2576/* Link Partner Ability Register (Base Page) */
2754#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 2577#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
2755#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ 2578#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
2756#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ 2579#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
2757#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ 2580#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
2758#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ 2581#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
2759#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 2582#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
2760#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 2583#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
2761#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 2584#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
2762#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ 2585#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
2763#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ 2586#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
2764#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 2587#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2765 2588
2766/* Autoneg Expansion Register */ 2589/* Autoneg Expansion Register */
2767#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 2590#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
2768#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ 2591#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
2769#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ 2592#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
2770#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ 2593#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
2771#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ 2594#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
2772 2595
2773/* Next Page TX Register */ 2596/* Next Page TX Register */
2774#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 2597#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2775#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges 2598#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
2776 * of different NP 2599 * of different NP
2777 */ 2600 */
2778#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 2601#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2779 * 0 = cannot comply with msg 2602 * 0 = cannot comply with msg
2780 */ 2603 */
2781#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 2604#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2782#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 2605#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2783 * 0 = sending last NP 2606 * 0 = sending last NP
2784 */ 2607 */
2785 2608
2786/* Link Partner Next Page Register */ 2609/* Link Partner Next Page Register */
2787#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 2610#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2788#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges 2611#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
2789 * of different NP 2612 * of different NP
2790 */ 2613 */
2791#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 2614#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2792 * 0 = cannot comply with msg 2615 * 0 = cannot comply with msg
2793 */ 2616 */
2794#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 2617#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2795#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ 2618#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
2796#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 2619#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2797 * 0 = sending last NP 2620 * 0 = sending last NP
2798 */ 2621 */
2799 2622
2800/* 1000BASE-T Control Register */ 2623/* 1000BASE-T Control Register */
2801#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 2624#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
2802#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 2625#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
2803#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 2626#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
2804#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ 2627#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
2805 /* 0=DTE device */ 2628 /* 0=DTE device */
2806#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 2629#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
2807 /* 0=Configure PHY as Slave */ 2630 /* 0=Configure PHY as Slave */
2808#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 2631#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
2809 /* 0=Automatic Master/Slave config */ 2632 /* 0=Automatic Master/Slave config */
2810#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 2633#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
2811#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 2634#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
2812#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 2635#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
2813#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 2636#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
2814#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 2637#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
2815 2638
2816/* 1000BASE-T Status Register */ 2639/* 1000BASE-T Status Register */
2817#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ 2640#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
2818#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ 2641#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
2819#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 2642#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
2820#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 2643#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
2821#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 2644#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
2822#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 2645#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
2823#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ 2646#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
2824#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 2647#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
2825#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 2648#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
2826#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 2649#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
2827#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 2650#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
@@ -2829,64 +2652,64 @@ struct e1000_host_command_info {
2829#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 2652#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
2830 2653
2831/* Extended Status Register */ 2654/* Extended Status Register */
2832#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 2655#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
2833#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 2656#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
2834#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 2657#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
2835#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 2658#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
2836 2659
2837#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ 2660#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
2838#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ 2661#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
2839 2662
2840#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ 2663#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
2841 /* (0=enable, 1=disable) */ 2664 /* (0=enable, 1=disable) */
2842 2665
2843/* M88E1000 PHY Specific Control Register */ 2666/* M88E1000 PHY Specific Control Register */
2844#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ 2667#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
2845#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 2668#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
2846#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ 2669#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
2847#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 2670#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
2848 * 0=CLK125 toggling 2671 * 0=CLK125 toggling
2849 */ 2672 */
2850#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 2673#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
2851 /* Manual MDI configuration */ 2674 /* Manual MDI configuration */
2852#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 2675#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
2853#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 2676#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2854 * 100BASE-TX/10BASE-T: 2677 * 100BASE-TX/10BASE-T:
2855 * MDI Mode 2678 * MDI Mode
2856 */ 2679 */
2857#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled 2680#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
2858 * all speeds. 2681 * all speeds.
2859 */ 2682 */
2860#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 2683#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
2861 /* 1=Enable Extended 10BASE-T distance 2684 /* 1=Enable Extended 10BASE-T distance
2862 * (Lower 10BASE-T RX Threshold) 2685 * (Lower 10BASE-T RX Threshold)
2863 * 0=Normal 10BASE-T RX Threshold */ 2686 * 0=Normal 10BASE-T RX Threshold */
2864#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 2687#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
2865 /* 1=5-Bit interface in 100BASE-TX 2688 /* 1=5-Bit interface in 100BASE-TX
2866 * 0=MII interface in 100BASE-TX */ 2689 * 0=MII interface in 100BASE-TX */
2867#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ 2690#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
2868#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ 2691#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
2869#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 2692#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
2870 2693
2871#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 2694#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2872#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 2695#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
2873#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 2696#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2874 2697
2875/* M88E1000 PHY Specific Status Register */ 2698/* M88E1000 PHY Specific Status Register */
2876#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ 2699#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
2877#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 2700#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
2878#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 2701#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
2879#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 2702#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
2880#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; 2703#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2881 * 3=110-140M;4=>140M */ 2704 * 3=110-140M;4=>140M */
2882#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 2705#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
2883#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 2706#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
2884#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ 2707#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
2885#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 2708#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
2886#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 2709#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
2887#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ 2710#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
2888#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 2711#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
2889#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 2712#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
2890 2713
2891#define M88E1000_PSSR_REV_POLARITY_SHIFT 1 2714#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2892#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5 2715#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
@@ -2894,12 +2717,12 @@ struct e1000_host_command_info {
2894#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 2717#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2895 2718
2896/* M88E1000 Extended PHY Specific Control Register */ 2719/* M88E1000 Extended PHY Specific Control Register */
2897#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ 2720#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
2898#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. 2721#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
2899 * Will assert lost lock and bring 2722 * Will assert lost lock and bring
2900 * link down if idle not seen 2723 * link down if idle not seen
2901 * within 1ms in 1000BASE-T 2724 * within 1ms in 1000BASE-T
2902 */ 2725 */
2903/* Number of times we will attempt to autonegotiate before downshifting if we 2726/* Number of times we will attempt to autonegotiate before downshifting if we
2904 * are the master */ 2727 * are the master */
2905#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 2728#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
@@ -2914,9 +2737,9 @@ struct e1000_host_command_info {
2914#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 2737#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2915#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 2738#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2916#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 2739#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2917#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ 2740#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2918#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 2741#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2919#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 2742#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2920 2743
2921/* M88EC018 Rev 2 specific DownShift settings */ 2744/* M88EC018 Rev 2 specific DownShift settings */
2922#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 2745#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
@@ -2938,18 +2761,18 @@ struct e1000_host_command_info {
2938#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000 2761#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
2939 2762
2940/* IGP01E1000 Specific Port Status Register - R/O */ 2763/* IGP01E1000 Specific Port Status Register - R/O */
2941#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */ 2764#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
2942#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 2765#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
2943#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C 2766#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
2944#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200 2767#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
2945#define IGP01E1000_PSSR_LINK_UP 0x0400 2768#define IGP01E1000_PSSR_LINK_UP 0x0400
2946#define IGP01E1000_PSSR_MDIX 0x0800 2769#define IGP01E1000_PSSR_MDIX 0x0800
2947#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */ 2770#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
2948#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000 2771#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
2949#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000 2772#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
2950#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 2773#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
2951#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */ 2774#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
2952#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */ 2775#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
2953 2776
2954/* IGP01E1000 Specific Port Control Register - R/W */ 2777/* IGP01E1000 Specific Port Control Register - R/W */
2955#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010 2778#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
@@ -2957,16 +2780,16 @@ struct e1000_host_command_info {
2957#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400 2780#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2958#define IGP01E1000_PSCR_FLIP_CHIP 0x0800 2781#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2959#define IGP01E1000_PSCR_AUTO_MDIX 0x1000 2782#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2960#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ 2783#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2961 2784
2962/* IGP01E1000 Specific Port Link Health Register */ 2785/* IGP01E1000 Specific Port Link Health Register */
2963#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 2786#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
2964#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000 2787#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
2965#define IGP01E1000_PLHR_MASTER_FAULT 0x2000 2788#define IGP01E1000_PLHR_MASTER_FAULT 0x2000
2966#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000 2789#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
2967#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */ 2790#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
2968#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */ 2791#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
2969#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */ 2792#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
2970#define IGP01E1000_PLHR_DATA_ERR_0 0x0100 2793#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
2971#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040 2794#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
2972#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010 2795#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
@@ -2981,9 +2804,9 @@ struct e1000_host_command_info {
2981#define IGP01E1000_MSE_CHANNEL_B 0x0F00 2804#define IGP01E1000_MSE_CHANNEL_B 0x0F00
2982#define IGP01E1000_MSE_CHANNEL_A 0xF000 2805#define IGP01E1000_MSE_CHANNEL_A 0xF000
2983 2806
2984#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 2807#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
2985#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */ 2808#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */
2986#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */ 2809#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */
2987 2810
2988/* IGP01E1000 DSP reset macros */ 2811/* IGP01E1000 DSP reset macros */
2989#define DSP_RESET_ENABLE 0x0 2812#define DSP_RESET_ENABLE 0x0
@@ -2992,8 +2815,8 @@ struct e1000_host_command_info {
2992 2815
2993/* IGP01E1000 & IGP02E1000 AGC Registers */ 2816/* IGP01E1000 & IGP02E1000 AGC Registers */
2994 2817
2995#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ 2818#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2996#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */ 2819#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */
2997 2820
2998/* IGP02E1000 AGC Register Length 9-bit mask */ 2821/* IGP02E1000 AGC Register Length 9-bit mask */
2999#define IGP02E1000_AGC_LENGTH_MASK 0x7F 2822#define IGP02E1000_AGC_LENGTH_MASK 0x7F
@@ -3011,9 +2834,9 @@ struct e1000_host_command_info {
3011#define IGP01E1000_PHY_POLARITY_MASK 0x0078 2834#define IGP01E1000_PHY_POLARITY_MASK 0x0078
3012 2835
3013/* IGP01E1000 GMII FIFO Register */ 2836/* IGP01E1000 GMII FIFO Register */
3014#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed 2837#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
3015 * on Link-Up */ 2838 * on Link-Up */
3016#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */ 2839#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
3017 2840
3018/* IGP01E1000 Analog Register */ 2841/* IGP01E1000 Analog Register */
3019#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 2842#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
@@ -3032,114 +2855,6 @@ struct e1000_host_command_info {
3032#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 2855#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
3033#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 2856#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
3034 2857
3035/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
3036#define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */
3037#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal Disabled */
3038#define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */
3039#define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter Disabled */
3040#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
3041#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI configuration */
3042#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX configuration */
3043#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic crossover */
3044#define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended Distance */
3045#define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300
3046#define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */
3047#define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only (Energy Detect) */
3048#define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */
3049#define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */
3050#define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */
3051#define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000
3052#define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12
3053
3054/* PHY Specific Status Register (Page 0, Register 17) */
3055#define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */
3056#define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */
3057#define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */
3058#define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */
3059#define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */
3060#define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */
3061#define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */
3062#define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */
3063#define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */
3064#define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */
3065#define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */
3066#define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */
3067#define GG82563_PSSR_SPEED_MASK 0xC000
3068#define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */
3069#define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */
3070#define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */
3071
3072/* PHY Specific Status Register 2 (Page 0, Register 19) */
3073#define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */
3074#define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */
3075#define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
3076#define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */
3077#define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */
3078#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */
3079#define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */
3080#define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */
3081#define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
3082#define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */
3083#define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */
3084#define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */
3085#define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */
3086
3087/* PHY Specific Control Register 2 (Page 0, Register 26) */
3088#define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative Polarity */
3089#define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C
3090#define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal Operation */
3091#define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns Sequence */
3092#define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns Sequence */
3093#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Negotiation */
3094#define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable 1000BASE-T */
3095#define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000
3096#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */
3097#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */
3098
3099/* MAC Specific Control Register (Page 2, Register 21) */
3100/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
3101#define GG82563_MSCR_TX_CLK_MASK 0x0007
3102#define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004
3103#define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005
3104#define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006
3105#define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007
3106
3107#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
3108
3109/* DSP Distance Register (Page 5, Register 26) */
3110#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
3111 1 = 50-80M;
3112 2 = 80-110M;
3113 3 = 110-140M;
3114 4 = >140M */
3115
3116/* Kumeran Mode Control Register (Page 193, Register 16) */
3117#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */
3118#define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */
3119#define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080
3120#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400
3121#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz, 0=0.8MHz */
3122#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
3123
3124/* Power Management Control Register (Page 193, Register 20) */
3125#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES Electrical Idle */
3126#define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */
3127#define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */
3128#define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse Auto-Negotiation */
3129#define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps Auto-Neg in non D0 */
3130#define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps Auto-Neg Always */
3131#define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a Reverse Auto-Negotiation */
3132#define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */
3133#define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300
3134#define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */
3135#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */
3136#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */
3137#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */
3138
3139/* In-Band Control Register (Page 194, Register 18) */
3140#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */
3141
3142
3143/* Bit definitions for valid PHY IDs. */ 2858/* Bit definitions for valid PHY IDs. */
3144/* I = Integrated 2859/* I = Integrated
3145 * E = External 2860 * E = External
@@ -3154,8 +2869,6 @@ struct e1000_host_command_info {
3154#define M88E1011_I_REV_4 0x04 2869#define M88E1011_I_REV_4 0x04
3155#define M88E1111_I_PHY_ID 0x01410CC0 2870#define M88E1111_I_PHY_ID 0x01410CC0
3156#define L1LXT971A_PHY_ID 0x001378E0 2871#define L1LXT971A_PHY_ID 0x001378E0
3157#define GG82563_E_PHY_ID 0x01410CA0
3158
3159 2872
3160/* Bits... 2873/* Bits...
3161 * 15-5: page 2874 * 15-5: page
@@ -3166,41 +2879,41 @@ struct e1000_host_command_info {
3166 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 2879 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
3167 2880
3168#define IGP3_PHY_PORT_CTRL \ 2881#define IGP3_PHY_PORT_CTRL \
3169 PHY_REG(769, 17) /* Port General Configuration */ 2882 PHY_REG(769, 17) /* Port General Configuration */
3170#define IGP3_PHY_RATE_ADAPT_CTRL \ 2883#define IGP3_PHY_RATE_ADAPT_CTRL \
3171 PHY_REG(769, 25) /* Rate Adapter Control Register */ 2884 PHY_REG(769, 25) /* Rate Adapter Control Register */
3172 2885
3173#define IGP3_KMRN_FIFO_CTRL_STATS \ 2886#define IGP3_KMRN_FIFO_CTRL_STATS \
3174 PHY_REG(770, 16) /* KMRN FIFO's control/status register */ 2887 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
3175#define IGP3_KMRN_POWER_MNG_CTRL \ 2888#define IGP3_KMRN_POWER_MNG_CTRL \
3176 PHY_REG(770, 17) /* KMRN Power Management Control Register */ 2889 PHY_REG(770, 17) /* KMRN Power Management Control Register */
3177#define IGP3_KMRN_INBAND_CTRL \ 2890#define IGP3_KMRN_INBAND_CTRL \
3178 PHY_REG(770, 18) /* KMRN Inband Control Register */ 2891 PHY_REG(770, 18) /* KMRN Inband Control Register */
3179#define IGP3_KMRN_DIAG \ 2892#define IGP3_KMRN_DIAG \
3180 PHY_REG(770, 19) /* KMRN Diagnostic register */ 2893 PHY_REG(770, 19) /* KMRN Diagnostic register */
3181#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */ 2894#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */
3182#define IGP3_KMRN_ACK_TIMEOUT \ 2895#define IGP3_KMRN_ACK_TIMEOUT \
3183 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */ 2896 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
3184 2897
3185#define IGP3_VR_CTRL \ 2898#define IGP3_VR_CTRL \
3186 PHY_REG(776, 18) /* Voltage regulator control register */ 2899 PHY_REG(776, 18) /* Voltage regulator control register */
3187#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */ 2900#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
3188#define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */ 2901#define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */
3189 2902
3190#define IGP3_CAPABILITY \ 2903#define IGP3_CAPABILITY \
3191 PHY_REG(776, 19) /* IGP3 Capability Register */ 2904 PHY_REG(776, 19) /* IGP3 Capability Register */
3192 2905
3193/* Capabilities for SKU Control */ 2906/* Capabilities for SKU Control */
3194#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */ 2907#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */
3195#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */ 2908#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */
3196#define IGP3_CAP_ASF 0x0004 /* Support ASF */ 2909#define IGP3_CAP_ASF 0x0004 /* Support ASF */
3197#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */ 2910#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */
3198#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */ 2911#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */
3199#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */ 2912#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */
3200#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */ 2913#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */
3201#define IGP3_CAP_RSS 0x0080 /* Support RSS */ 2914#define IGP3_CAP_RSS 0x0080 /* Support RSS */
3202#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */ 2915#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */
3203#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */ 2916#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */
3204 2917
3205#define IGP3_PPC_JORDAN_EN 0x0001 2918#define IGP3_PPC_JORDAN_EN 0x0001
3206#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002 2919#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002
@@ -3210,69 +2923,69 @@ struct e1000_host_command_info {
3210#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020 2923#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020
3211#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040 2924#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040
3212 2925
3213#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */ 2926#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */
3214#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */ 2927#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */
3215 2928
3216#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18) 2929#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)
3217#define IGP3_KMRN_EC_DIS_INBAND 0x0080 2930#define IGP3_KMRN_EC_DIS_INBAND 0x0080
3218 2931
3219#define IGP03E1000_E_PHY_ID 0x02A80390 2932#define IGP03E1000_E_PHY_ID 0x02A80390
3220#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */ 2933#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
3221#define IFE_PLUS_E_PHY_ID 0x02A80320 2934#define IFE_PLUS_E_PHY_ID 0x02A80320
3222#define IFE_C_E_PHY_ID 0x02A80310 2935#define IFE_C_E_PHY_ID 0x02A80310
3223 2936
3224#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */ 2937#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */
3225#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */ 2938#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */
3226#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */ 2939#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */
3227#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */ 2940#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnect Counter */
3228#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */ 2941#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */
3229#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */ 2942#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */
3230#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */ 2943#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */
3231#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */ 2944#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */
3232#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */ 2945#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */
3233#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */ 2946#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */
3234#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */ 2947#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */
3235#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */ 2948#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
3236#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */ 2949#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */
3237 2950
3238#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */ 2951#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Default 1 = Disable auto reduced power down */
3239#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */ 2952#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */
3240#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */ 2953#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */
3241#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */ 2954#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */
3242#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */ 2955#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */
3243#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */ 2956#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
3244#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */ 2957#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */
3245#define IFE_PESC_POLARITY_REVERSED_SHIFT 8 2958#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
3246 2959
3247#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */ 2960#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dynamic Power Down disabled */
3248#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */ 2961#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */
3249#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */ 2962#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */
3250#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */ 2963#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */
3251#define IFE_PSC_FORCE_POLARITY_SHIFT 5 2964#define IFE_PSC_FORCE_POLARITY_SHIFT 5
3252#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4 2965#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
3253 2966
3254#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */ 2967#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */
3255#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */ 2968#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */
3256#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 2969#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
3257#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm is completed */ 2970#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm is completed */
3258#define IFE_PMC_MDIX_MODE_SHIFT 6 2971#define IFE_PMC_MDIX_MODE_SHIFT 6
3259#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */ 2972#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
3260 2973
3261#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */ 2974#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */
3262#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */ 2975#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */
3263#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */ 2976#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */
3264#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */ 2977#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
3265#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */ 2978#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
3266#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */ 2979#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */
3267#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */ 2980#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */
3268#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */ 2981#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
3269#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */ 2982#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
3270#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 2983#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
3271#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 2984#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
3272 2985
3273#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ 2986#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */
3274#define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ 2987#define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */
3275#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ 2988#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */
3276#define ICH_FLASH_SEG_SIZE_256 256 2989#define ICH_FLASH_SEG_SIZE_256 256
3277#define ICH_FLASH_SEG_SIZE_4K 4096 2990#define ICH_FLASH_SEG_SIZE_4K 4096
3278#define ICH_FLASH_SEG_SIZE_64K 65536 2991#define ICH_FLASH_SEG_SIZE_64K 65536
@@ -3305,74 +3018,6 @@ struct e1000_host_command_info {
3305#define ICH_GFPREG_BASE_MASK 0x1FFF 3018#define ICH_GFPREG_BASE_MASK 0x1FFF
3306#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 3019#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
3307 3020
3308/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
3309/* Offset 04h HSFSTS */
3310union ich8_hws_flash_status {
3311 struct ich8_hsfsts {
3312#ifdef __BIG_ENDIAN
3313 u16 reserved2 :6;
3314 u16 fldesvalid :1;
3315 u16 flockdn :1;
3316 u16 flcdone :1;
3317 u16 flcerr :1;
3318 u16 dael :1;
3319 u16 berasesz :2;
3320 u16 flcinprog :1;
3321 u16 reserved1 :2;
3322#else
3323 u16 flcdone :1; /* bit 0 Flash Cycle Done */
3324 u16 flcerr :1; /* bit 1 Flash Cycle Error */
3325 u16 dael :1; /* bit 2 Direct Access error Log */
3326 u16 berasesz :2; /* bit 4:3 Block/Sector Erase Size */
3327 u16 flcinprog :1; /* bit 5 flash SPI cycle in Progress */
3328 u16 reserved1 :2; /* bit 13:6 Reserved */
3329 u16 reserved2 :6; /* bit 13:6 Reserved */
3330 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
3331 u16 flockdn :1; /* bit 15 Flash Configuration Lock-Down */
3332#endif
3333 } hsf_status;
3334 u16 regval;
3335};
3336
3337/* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */
3338/* Offset 06h FLCTL */
3339union ich8_hws_flash_ctrl {
3340 struct ich8_hsflctl {
3341#ifdef __BIG_ENDIAN
3342 u16 fldbcount :2;
3343 u16 flockdn :6;
3344 u16 flcgo :1;
3345 u16 flcycle :2;
3346 u16 reserved :5;
3347#else
3348 u16 flcgo :1; /* 0 Flash Cycle Go */
3349 u16 flcycle :2; /* 2:1 Flash Cycle */
3350 u16 reserved :5; /* 7:3 Reserved */
3351 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
3352 u16 flockdn :6; /* 15:10 Reserved */
3353#endif
3354 } hsf_ctrl;
3355 u16 regval;
3356};
3357
3358/* ICH8 Flash Region Access Permissions */
3359union ich8_hws_flash_regacc {
3360 struct ich8_flracc {
3361#ifdef __BIG_ENDIAN
3362 u32 gmwag :8;
3363 u32 gmrag :8;
3364 u32 grwa :8;
3365 u32 grra :8;
3366#else
3367 u32 grra :8; /* 0:7 GbE region Read Access */
3368 u32 grwa :8; /* 8:15 GbE region Write Access */
3369 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
3370 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
3371#endif
3372 } hsf_flregacc;
3373 u16 regval;
3374};
3375
3376/* Miscellaneous PHY bit definitions. */ 3021/* Miscellaneous PHY bit definitions. */
3377#define PHY_PREAMBLE 0xFFFFFFFF 3022#define PHY_PREAMBLE 0xFFFFFFFF
3378#define PHY_SOF 0x01 3023#define PHY_SOF 0x01
@@ -3384,10 +3029,10 @@ union ich8_hws_flash_regacc {
3384#define MII_CR_SPEED_100 0x2000 3029#define MII_CR_SPEED_100 0x2000
3385#define MII_CR_SPEED_10 0x0000 3030#define MII_CR_SPEED_10 0x0000
3386#define E1000_PHY_ADDRESS 0x01 3031#define E1000_PHY_ADDRESS 0x01
3387#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 3032#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
3388#define PHY_FORCE_TIME 20 /* 2.0 Seconds */ 3033#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
3389#define PHY_REVISION_MASK 0xFFFFFFF0 3034#define PHY_REVISION_MASK 0xFFFFFFF0
3390#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ 3035#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
3391#define REG4_SPEED_MASK 0x01E0 3036#define REG4_SPEED_MASK 0x01E0
3392#define REG9_SPEED_MASK 0x0300 3037#define REG9_SPEED_MASK 0x0300
3393#define ADVERTISE_10_HALF 0x0001 3038#define ADVERTISE_10_HALF 0x0001
@@ -3396,8 +3041,8 @@ union ich8_hws_flash_regacc {
3396#define ADVERTISE_100_FULL 0x0008 3041#define ADVERTISE_100_FULL 0x0008
3397#define ADVERTISE_1000_HALF 0x0010 3042#define ADVERTISE_1000_HALF 0x0010
3398#define ADVERTISE_1000_FULL 0x0020 3043#define ADVERTISE_1000_FULL 0x0020
3399#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ 3044#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
3400#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ 3045#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
3401#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ 3046#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
3402 3047
3403#endif /* _E1000_HW_H_ */ 3048#endif /* _E1000_HW_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-20 20:57:36 -0500