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Diffstat (limited to 'drivers/net/bnx2x/bnx2x_reg.h')
-rw-r--r--drivers/net/bnx2x/bnx2x_reg.h906
1 files changed, 804 insertions, 102 deletions
diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h
index 86bba25d2d3f..53da4ef19928 100644
--- a/drivers/net/bnx2x/bnx2x_reg.h
+++ b/drivers/net/bnx2x/bnx2x_reg.h
@@ -54,16 +54,20 @@
54/* [RW 10] The number of free blocks below which the full signal to class 0 54/* [RW 10] The number of free blocks below which the full signal to class 0
55 * is asserted */ 55 * is asserted */
56#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0 56#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0
57/* [RW 10] The number of free blocks above which the full signal to class 0 57#define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230
58/* [RW 11] The number of free blocks above which the full signal to class 0
58 * is de-asserted */ 59 * is de-asserted */
59#define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4 60#define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4
60/* [RW 10] The number of free blocks below which the full signal to class 1 61#define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234
62/* [RW 11] The number of free blocks below which the full signal to class 1
61 * is asserted */ 63 * is asserted */
62#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8 64#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8
63/* [RW 10] The number of free blocks above which the full signal to class 1 65#define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238
66/* [RW 11] The number of free blocks above which the full signal to class 1
64 * is de-asserted */ 67 * is de-asserted */
65#define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc 68#define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc
66/* [RW 10] The number of free blocks below which the full signal to the LB 69#define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c
70/* [RW 11] The number of free blocks below which the full signal to the LB
67 * port is asserted */ 71 * port is asserted */
68#define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0 72#define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0
69/* [RW 10] The number of free blocks above which the full signal to the LB 73/* [RW 10] The number of free blocks above which the full signal to the LB
@@ -75,15 +79,49 @@
75/* [RW 10] The number of free blocks below which the High_llfc signal to 79/* [RW 10] The number of free blocks below which the High_llfc signal to
76 interface #n is asserted. */ 80 interface #n is asserted. */
77#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c 81#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
78/* [RW 23] LL RAM data. */ 82/* [RW 11] The number of blocks guarantied for the LB port */
79#define BRB1_REG_LL_RAM 0x61000 83#define BRB1_REG_LB_GUARANTIED 0x601ec
84/* [RW 11] The hysteresis on the guarantied buffer space for the Lb port
85 * before signaling XON. */
86#define BRB1_REG_LB_GUARANTIED_HYST 0x60264
87/* [RW 24] LL RAM data. */
88#define BRB1_REG_LL_RAM 0x61000
80/* [RW 10] The number of free blocks above which the Low_llfc signal to 89/* [RW 10] The number of free blocks above which the Low_llfc signal to
81 interface #n is de-asserted. */ 90 interface #n is de-asserted. */
82#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c 91#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
83/* [RW 10] The number of free blocks below which the Low_llfc signal to 92/* [RW 10] The number of free blocks below which the Low_llfc signal to
84 interface #n is asserted. */ 93 interface #n is asserted. */
85#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c 94#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
86/* [RW 10] The number of blocks guarantied for the MAC port */ 95/* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The
96 * register is applicable only when per_class_guaranty_mode is set. */
97#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244
98/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
99 * 1 before signaling XON. The register is applicable only when
100 * per_class_guaranty_mode is set. */
101#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254
102/* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The
103 * register is applicable only when per_class_guaranty_mode is set. */
104#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248
105/* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0
106 * before signaling XON. The register is applicable only when
107 * per_class_guaranty_mode is set. */
108#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258
109/* [RW 11] The number of blocks guarantied for class 0in MAC1.The register
110 * is applicable only when per_class_guaranty_mode is set. */
111#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c
112/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
113 * 1 before signaling XON. The register is applicable only when
114 * per_class_guaranty_mode is set. */
115#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c
116/* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The
117 * register is applicable only when per_class_guaranty_mode is set. */
118#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250
119/* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC
120 * 1 before signaling XON. The register is applicable only when
121 * per_class_guaranty_mode is set. */
122#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260
123/* [RW 11] The number of blocks guarantied for the MAC port. The register is
124 * applicable only when per_class_guaranty_mode is reset. */
87#define BRB1_REG_MAC_GUARANTIED_0 0x601e8 125#define BRB1_REG_MAC_GUARANTIED_0 0x601e8
88#define BRB1_REG_MAC_GUARANTIED_1 0x60240 126#define BRB1_REG_MAC_GUARANTIED_1 0x60240
89/* [R 24] The number of full blocks. */ 127/* [R 24] The number of full blocks. */
@@ -100,15 +138,19 @@
100/* [RW 10] The number of free blocks below which the pause signal to class 0 138/* [RW 10] The number of free blocks below which the pause signal to class 0
101 * is asserted */ 139 * is asserted */
102#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0 140#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0
103/* [RW 10] The number of free blocks above which the pause signal to class 0 141#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220
142/* [RW 11] The number of free blocks above which the pause signal to class 0
104 * is de-asserted */ 143 * is de-asserted */
105#define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4 144#define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4
106/* [RW 10] The number of free blocks below which the pause signal to class 1 145#define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224
146/* [RW 11] The number of free blocks below which the pause signal to class 1
107 * is asserted */ 147 * is asserted */
108#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8 148#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8
109/* [RW 10] The number of free blocks above which the pause signal to class 1 149#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228
150/* [RW 11] The number of free blocks above which the pause signal to class 1
110 * is de-asserted */ 151 * is de-asserted */
111#define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc 152#define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc
153#define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c
112/* [RW 10] Write client 0: De-assert pause threshold. Not Functional */ 154/* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
113#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078 155#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
114#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c 156#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
@@ -422,6 +464,7 @@
422#define CFC_REG_NUM_LCIDS_ALLOC 0x104020 464#define CFC_REG_NUM_LCIDS_ALLOC 0x104020
423/* [R 9] Number of Arriving LCIDs in Link List Block */ 465/* [R 9] Number of Arriving LCIDs in Link List Block */
424#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004 466#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
467#define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120
425/* [R 9] Number of Leaving LCIDs in Link List Block */ 468/* [R 9] Number of Leaving LCIDs in Link List Block */
426#define CFC_REG_NUM_LCIDS_LEAVING 0x104018 469#define CFC_REG_NUM_LCIDS_LEAVING 0x104018
427#define CFC_REG_WEAK_ENABLE_PF 0x104124 470#define CFC_REG_WEAK_ENABLE_PF 0x104124
@@ -783,6 +826,7 @@
783/* [RW 3] The number of simultaneous outstanding requests to Context Fetch 826/* [RW 3] The number of simultaneous outstanding requests to Context Fetch
784 Interface. */ 827 Interface. */
785#define DORQ_REG_OUTST_REQ 0x17003c 828#define DORQ_REG_OUTST_REQ 0x17003c
829#define DORQ_REG_PF_USAGE_CNT 0x1701d0
786#define DORQ_REG_REGN 0x170038 830#define DORQ_REG_REGN 0x170038
787/* [R 4] Current value of response A counter credit. Initial credit is 831/* [R 4] Current value of response A counter credit. Initial credit is
788 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 832 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
@@ -802,10 +846,12 @@
802/* [RW 28] TCM Header when both ULP and TCP context is loaded. */ 846/* [RW 28] TCM Header when both ULP and TCP context is loaded. */
803#define DORQ_REG_SHRT_CMHEAD 0x170054 847#define DORQ_REG_SHRT_CMHEAD 0x170054
804#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4) 848#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
849#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)
805#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3) 850#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
806#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7) 851#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
807#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2) 852#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
808#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1) 853#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
854#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0)
809#define HC_REG_AGG_INT_0 0x108050 855#define HC_REG_AGG_INT_0 0x108050
810#define HC_REG_AGG_INT_1 0x108054 856#define HC_REG_AGG_INT_1 0x108054
811#define HC_REG_ATTN_BIT 0x108120 857#define HC_REG_ATTN_BIT 0x108120
@@ -844,6 +890,7 @@
844#define HC_REG_VQID_0 0x108008 890#define HC_REG_VQID_0 0x108008
845#define HC_REG_VQID_1 0x10800c 891#define HC_REG_VQID_1 0x10800c
846#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1) 892#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
893#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0)
847#define IGU_REG_ATTENTION_ACK_BITS 0x130108 894#define IGU_REG_ATTENTION_ACK_BITS 0x130108
848/* [R 4] Debug: attn_fsm */ 895/* [R 4] Debug: attn_fsm */
849#define IGU_REG_ATTN_FSM 0x130054 896#define IGU_REG_ATTN_FSM 0x130054
@@ -933,6 +980,14 @@
933 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */ 980 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
934#define IGU_REG_WRITE_DONE_PENDING 0x130480 981#define IGU_REG_WRITE_DONE_PENDING 0x130480
935#define MCP_A_REG_MCPR_SCRATCH 0x3a0000 982#define MCP_A_REG_MCPR_SCRATCH 0x3a0000
983#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
984#define MCP_REG_MCPR_GP_INPUTS 0x800c0
985#define MCP_REG_MCPR_GP_OENABLE 0x800c8
986#define MCP_REG_MCPR_GP_OUTPUTS 0x800c4
987#define MCP_REG_MCPR_IMC_COMMAND 0x85900
988#define MCP_REG_MCPR_IMC_DATAREG0 0x85920
989#define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904
990#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
936#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424 991#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
937#define MCP_REG_MCPR_NVM_ADDR 0x8640c 992#define MCP_REG_MCPR_NVM_ADDR 0x8640c
938#define MCP_REG_MCPR_NVM_CFG4 0x8642c 993#define MCP_REG_MCPR_NVM_CFG4 0x8642c
@@ -1429,11 +1484,37 @@
1429/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 1484/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1430 only. */ 1485 only. */
1431#define MISC_REG_E1HMF_MODE 0xa5f8 1486#define MISC_REG_E1HMF_MODE 0xa5f8
1487/* [R 1] Status of four port mode path swap input pin. */
1488#define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c
1489/* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
1490 the path_swap output is equal to 4 port mode path swap input pin; if it
1491 is 1 - the path_swap output is equal to bit[1] of this register; [1] -
1492 Overwrite value. If bit[0] of this register is 1 this is the value that
1493 receives the path_swap output. Reset on Hard reset. */
1494#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738
1495/* [R 1] Status of 4 port mode port swap input pin. */
1496#define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754
1497/* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
1498 the port_swap output is equal to 4 port mode port swap input pin; if it
1499 is 1 - the port_swap output is equal to bit[1] of this register; [1] -
1500 Overwrite value. If bit[0] of this register is 1 this is the value that
1501 receives the port_swap output. Reset on Hard reset. */
1502#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734
1432/* [RW 32] Debug only: spare RW register reset by core reset */ 1503/* [RW 32] Debug only: spare RW register reset by core reset */
1433#define MISC_REG_GENERIC_CR_0 0xa460 1504#define MISC_REG_GENERIC_CR_0 0xa460
1434#define MISC_REG_GENERIC_CR_1 0xa464 1505#define MISC_REG_GENERIC_CR_1 0xa464
1435/* [RW 32] Debug only: spare RW register reset by por reset */ 1506/* [RW 32] Debug only: spare RW register reset by por reset */
1436#define MISC_REG_GENERIC_POR_1 0xa474 1507#define MISC_REG_GENERIC_POR_1 0xa474
1508/* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
1509 use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO
1510 can not be configured as an output. Each output has its output enable in
1511 the MCP register space; but this bit needs to be set to make use of that.
1512 Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When
1513 set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.
1514 When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
1515 the i/o to an output and will drive the TimeSync output. Bit[31:7]:
1516 spare. Global register. Reset by hard reset. */
1517#define MISC_REG_GEN_PURP_HWG 0xa9a0
1437/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of 1518/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1438 these bits is written as a '1'; the corresponding SPIO bit will turn off 1519 these bits is written as a '1'; the corresponding SPIO bit will turn off
1439 it's drivers and become an input. This is the reset state of all GPIO 1520 it's drivers and become an input. This is the reset state of all GPIO
@@ -1636,6 +1717,14 @@
1636 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 - 1717 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 -
1637 timer 8 */ 1718 timer 8 */
1638#define MISC_REG_SW_TIMER_VAL 0xa5c0 1719#define MISC_REG_SW_TIMER_VAL 0xa5c0
1720/* [R 1] Status of two port mode path swap input pin. */
1721#define MISC_REG_TWO_PORT_PATH_SWAP 0xa758
1722/* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
1723 path_swap output is equal to 2 port mode path swap input pin; if it is 1
1724 - the path_swap output is equal to bit[1] of this register; [1] -
1725 Overwrite value. If bit[0] of this register is 1 this is the value that
1726 receives the path_swap output. Reset on Hard reset. */
1727#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c
1639/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are 1728/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1640 loaded; 0-prepare; -unprepare */ 1729 loaded; 0-prepare; -unprepare */
1641#define MISC_REG_UNPREPARED 0xa424 1730#define MISC_REG_UNPREPARED 0xa424
@@ -1644,6 +1733,36 @@
1644#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4) 1733#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1645#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2) 1734#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1646#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3) 1735#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1736/* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
1737 * not it is the recipient of the message on the MDIO interface. The value
1738 * is compared to the value on ctrl_md_devad. Drives output
1739 * misc_xgxs0_phy_addr. Global register. */
1740#define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc
1741/* [RW 2] XMAC Core port mode. Indicates the number of ports on the system
1742 side. This should be less than or equal to phy_port_mode; if some of the
1743 ports are not used. This enables reduction of frequency on the core side.
1744 This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
1745 Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
1746 input for the XMAC_MP core; and should be changed only while reset is
1747 held low. Reset on Hard reset. */
1748#define MISC_REG_XMAC_CORE_PORT_MODE 0xa964
1749/* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
1750 Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
1751 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
1752 XMAC_MP core; and should be changed only while reset is held low. Reset
1753 on Hard reset. */
1754#define MISC_REG_XMAC_PHY_PORT_MODE 0xa960
1755/* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
1756 * Reads from this register will clear bits 31:0. */
1757#define MSTAT_REG_RX_STAT_GR64_LO 0x200
1758/* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
1759 * 31:0. Reads from this register will clear bits 31:0. */
1760#define MSTAT_REG_TX_STAT_GTXPOK_LO 0
1761#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1762#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1763#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1764#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1765#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1647#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0) 1766#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
1648#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0) 1767#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
1649#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0) 1768#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
@@ -1837,6 +1956,10 @@
1837#define NIG_REG_LLH1_FUNC_MEM 0x161c0 1956#define NIG_REG_LLH1_FUNC_MEM 0x161c0
1838#define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160 1957#define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160
1839#define NIG_REG_LLH1_FUNC_MEM_SIZE 16 1958#define NIG_REG_LLH1_FUNC_MEM_SIZE 16
1959/* [RW 1] When this bit is set; the LLH will classify the packet before
1960 * sending it to the BRB or calculating WoL on it. This bit controls port 1
1961 * only. The legacy llh_multi_function_mode bit controls port 0. */
1962#define NIG_REG_LLH1_MF_MODE 0x18614
1840/* [RW 8] init credit counter for port1 in LLH */ 1963/* [RW 8] init credit counter for port1 in LLH */
1841#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564 1964#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1842#define NIG_REG_LLH1_XCM_MASK 0x10134 1965#define NIG_REG_LLH1_XCM_MASK 0x10134
@@ -1858,11 +1981,25 @@
1858/* [R 32] Interrupt register #0 read */ 1981/* [R 32] Interrupt register #0 read */
1859#define NIG_REG_NIG_INT_STS_0 0x103b0 1982#define NIG_REG_NIG_INT_STS_0 0x103b0
1860#define NIG_REG_NIG_INT_STS_1 0x103c0 1983#define NIG_REG_NIG_INT_STS_1 0x103c0
1984/* [R 32] Legacy E1 and E1H location for parity error mask register. */
1985#define NIG_REG_NIG_PRTY_MASK 0x103dc
1986/* [RW 32] Parity mask register #0 read/write */
1987#define NIG_REG_NIG_PRTY_MASK_0 0x183c8
1988#define NIG_REG_NIG_PRTY_MASK_1 0x183d8
1861/* [R 32] Legacy E1 and E1H location for parity error status register. */ 1989/* [R 32] Legacy E1 and E1H location for parity error status register. */
1862#define NIG_REG_NIG_PRTY_STS 0x103d0 1990#define NIG_REG_NIG_PRTY_STS 0x103d0
1863/* [R 32] Parity register #0 read */ 1991/* [R 32] Parity register #0 read */
1864#define NIG_REG_NIG_PRTY_STS_0 0x183bc 1992#define NIG_REG_NIG_PRTY_STS_0 0x183bc
1865#define NIG_REG_NIG_PRTY_STS_1 0x183cc 1993#define NIG_REG_NIG_PRTY_STS_1 0x183cc
1994/* [R 32] Legacy E1 and E1H location for parity error status clear register. */
1995#define NIG_REG_NIG_PRTY_STS_CLR 0x103d4
1996/* [RC 32] Parity register #0 read clear */
1997#define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0
1998#define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0
1999#define MCPR_IMC_COMMAND_ENABLE (1L<<31)
2000#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
2001#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
2002#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
1866/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2003/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
1867 * Ethernet header. */ 2004 * Ethernet header. */
1868#define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038 2005#define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
@@ -1872,6 +2009,12 @@
1872#define NIG_REG_P0_HWPFC_ENABLE 0x18078 2009#define NIG_REG_P0_HWPFC_ENABLE 0x18078
1873#define NIG_REG_P0_LLH_FUNC_MEM2 0x18480 2010#define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
1874#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440 2011#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440
2012/* [RW 1] Input enable for RX MAC interface. */
2013#define NIG_REG_P0_MAC_IN_EN 0x185ac
2014/* [RW 1] Output enable for TX MAC interface */
2015#define NIG_REG_P0_MAC_OUT_EN 0x185b0
2016/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2017#define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4
1875/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for 2018/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
1876 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the 2019 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
1877 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit 2020 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
@@ -1888,11 +2031,52 @@
1888 * than one bit may be set; allowing multiple priorities to be mapped to one 2031 * than one bit may be set; allowing multiple priorities to be mapped to one
1889 * COS. */ 2032 * COS. */
1890#define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c 2033#define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c
2034/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2035 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2036 * than one bit may be set; allowing multiple priorities to be mapped to one
2037 * COS. */
2038#define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0
2039/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
2040 * priority is mapped to COS 3 when the corresponding mask bit is 1. More
2041 * than one bit may be set; allowing multiple priorities to be mapped to one
2042 * COS. */
2043#define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4
2044/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
2045 * priority is mapped to COS 4 when the corresponding mask bit is 1. More
2046 * than one bit may be set; allowing multiple priorities to be mapped to one
2047 * COS. */
2048#define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8
2049/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
2050 * priority is mapped to COS 5 when the corresponding mask bit is 1. More
2051 * than one bit may be set; allowing multiple priorities to be mapped to one
2052 * COS. */
2053#define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc
2054/* [R 1] RX FIFO for receiving data from MAC is empty. */
1891/* [RW 15] Specify which of the credit registers the client is to be mapped 2055/* [RW 15] Specify which of the credit registers the client is to be mapped
1892 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For 2056 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
1893 * clients that are not subject to WFQ credit blocking - their 2057 * clients that are not subject to WFQ credit blocking - their
1894 * specifications here are not used. */ 2058 * specifications here are not used. */
1895#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0 2059#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0
2060/* [RW 32] Specify which of the credit registers the client is to be mapped
2061 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2062 * for client 0; bits [35:32] are for client 8. For clients that are not
2063 * subject to WFQ credit blocking - their specifications here are not used.
2064 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2065 * input clients to ETS arbiter. The reset default is set for management and
2066 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2067 * use credit registers 0-5 respectively (0x543210876). Note that credit
2068 * registers can not be shared between clients. */
2069#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688
2070/* [RW 4] Specify which of the credit registers the client is to be mapped
2071 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2072 * for client 0; bits [35:32] are for client 8. For clients that are not
2073 * subject to WFQ credit blocking - their specifications here are not used.
2074 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2075 * input clients to ETS arbiter. The reset default is set for management and
2076 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2077 * use credit registers 0-5 respectively (0x543210876). Note that credit
2078 * registers can not be shared between clients. */
2079#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c
1896/* [RW 5] Specify whether the client competes directly in the strict 2080/* [RW 5] Specify whether the client competes directly in the strict
1897 * priority arbiter. The bits are mapped according to client ID (client IDs 2081 * priority arbiter. The bits are mapped according to client ID (client IDs
1898 * are defined in tx_arb_priority_client). Default value is set to enable 2082 * are defined in tx_arb_priority_client). Default value is set to enable
@@ -1907,10 +2091,24 @@
1907 * reach. */ 2091 * reach. */
1908#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c 2092#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c
1909#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110 2093#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110
2094#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114
2095#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118
2096#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c
2097#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0
2098#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4
2099#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8
2100#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac
1910/* [RW 32] Specify the weight (in bytes) to be added to credit register 0 2101/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
1911 * when it is time to increment. */ 2102 * when it is time to increment. */
1912#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8 2103#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8
1913#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc 2104#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc
2105#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100
2106#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104
2107#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108
2108#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690
2109#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694
2110#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698
2111#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c
1914/* [RW 12] Specify the number of strict priority arbitration slots between 2112/* [RW 12] Specify the number of strict priority arbitration slots between
1915 * two round-robin arbitration slots to avoid starvation. A value of 0 means 2113 * two round-robin arbitration slots to avoid starvation. A value of 0 means
1916 * no strict priority cycles - the strict priority with anti-starvation 2114 * no strict priority cycles - the strict priority with anti-starvation
@@ -1925,8 +2123,36 @@
1925 * for management at priority 0; debug traffic at priorities 1 and 2; COS0 2123 * for management at priority 0; debug traffic at priorities 1 and 2; COS0
1926 * traffic at priority 3; and COS1 traffic at priority 4. */ 2124 * traffic at priority 3; and COS1 traffic at priority 4. */
1927#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4 2125#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4
2126/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2127 * Ethernet header. */
2128#define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c
1928#define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0 2129#define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
1929#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460 2130#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460
2131/* [RW 32] Specify the client number to be assigned to each priority of the
2132 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2133 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2134 * client; bits [35-32] are for priority 8 client. The clients are assigned
2135 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2136 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2137 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2138 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2139 * accommodate the 9 input clients to ETS arbiter. */
2140#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680
2141/* [RW 4] Specify the client number to be assigned to each priority of the
2142 * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2143 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2144 * client; bits [35-32] are for priority 8 client. The clients are assigned
2145 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2146 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2147 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2148 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2149 * accommodate the 9 input clients to ETS arbiter. */
2150#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684
2151#define NIG_REG_P1_MAC_IN_EN 0x185c0
2152/* [RW 1] Output enable for TX MAC interface */
2153#define NIG_REG_P1_MAC_OUT_EN 0x185c4
2154/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2155#define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8
1930/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for 2156/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
1931 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the 2157 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
1932 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit 2158 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
@@ -1943,6 +2169,105 @@
1943 * than one bit may be set; allowing multiple priorities to be mapped to one 2169 * than one bit may be set; allowing multiple priorities to be mapped to one
1944 * COS. */ 2170 * COS. */
1945#define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0 2171#define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0
2172/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2173 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2174 * than one bit may be set; allowing multiple priorities to be mapped to one
2175 * COS. */
2176#define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8
2177/* [R 1] RX FIFO for receiving data from MAC is empty. */
2178#define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c
2179/* [R 1] TLLH FIFO is empty. */
2180#define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338
2181/* [RW 32] Specify which of the credit registers the client is to be mapped
2182 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2183 * for client 0; bits [35:32] are for client 8. For clients that are not
2184 * subject to WFQ credit blocking - their specifications here are not used.
2185 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2186 * input clients to ETS arbiter. The reset default is set for management and
2187 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2188 * use credit registers 0-5 respectively (0x543210876). Note that credit
2189 * registers can not be shared between clients. Note also that there are
2190 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2191 * credit registers 0-5 are valid. This register should be configured
2192 * appropriately before enabling WFQ. */
2193#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8
2194/* [RW 4] Specify which of the credit registers the client is to be mapped
2195 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2196 * for client 0; bits [35:32] are for client 8. For clients that are not
2197 * subject to WFQ credit blocking - their specifications here are not used.
2198 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2199 * input clients to ETS arbiter. The reset default is set for management and
2200 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2201 * use credit registers 0-5 respectively (0x543210876). Note that credit
2202 * registers can not be shared between clients. Note also that there are
2203 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2204 * credit registers 0-5 are valid. This register should be configured
2205 * appropriately before enabling WFQ. */
2206#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec
2207/* [RW 9] Specify whether the client competes directly in the strict
2208 * priority arbiter. The bits are mapped according to client ID (client IDs
2209 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
2210 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2211 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
2212 * Default value is set to enable strict priorities for all clients. */
2213#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234
2214/* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
2215 * bits are mapped according to client ID (client IDs are defined in
2216 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
2217 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
2218 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
2219 * 0 for not using WFQ credit blocking. */
2220#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238
2221#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258
2222#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c
2223#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260
2224#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264
2225#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268
2226#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4
2227/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2228 * when it is time to increment. */
2229#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244
2230#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248
2231#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c
2232#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250
2233#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254
2234#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0
2235/* [RW 12] Specify the number of strict priority arbitration slots between
2236 two round-robin arbitration slots to avoid starvation. A value of 0 means
2237 no strict priority cycles - the strict priority with anti-starvation
2238 arbiter becomes a round-robin arbiter. */
2239#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240
2240/* [RW 32] Specify the client number to be assigned to each priority of the
2241 strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2242 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2243 client; bits [35-32] are for priority 8 client. The clients are assigned
2244 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2245 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2246 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2247 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2248 accommodate the 9 input clients to ETS arbiter. Note that this register
2249 is the same as the one for port 0, except that port 1 only has COS 0-2
2250 traffic. There is no traffic for COS 3-5 of port 1. */
2251#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0
2252/* [RW 4] Specify the client number to be assigned to each priority of the
2253 strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2254 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2255 client; bits [35-32] are for priority 8 client. The clients are assigned
2256 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2257 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2258 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2259 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2260 accommodate the 9 input clients to ETS arbiter. Note that this register
2261 is the same as the one for port 0, except that port 1 only has COS 0-2
2262 traffic. There is no traffic for COS 3-5 of port 1. */
2263#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4
2264/* [R 1] TX FIFO for transmitting data to MAC is empty. */
2265#define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594
2266/* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets
2267 forwarded to the host. */
2268#define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8
2269/* [RW 32] Specify the upper bound that credit register 0 is allowed to
2270 * reach. */
1946/* [RW 1] Pause enable for port0. This register may get 1 only when 2271/* [RW 1] Pause enable for port0. This register may get 1 only when
1947 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same 2272 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
1948 port */ 2273 port */
@@ -2026,12 +2351,45 @@
2026#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18 2351#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
2027/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */ 2352/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */
2028#define PBF_REG_COS0_UPPER_BOUND 0x15c05c 2353#define PBF_REG_COS0_UPPER_BOUND 0x15c05c
2354/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2355 * of port 0. */
2356#define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc
2357/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2358 * of port 1. */
2359#define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4
2029/* [RW 31] The weight of COS0 in the ETS command arbiter. */ 2360/* [RW 31] The weight of COS0 in the ETS command arbiter. */
2030#define PBF_REG_COS0_WEIGHT 0x15c054 2361#define PBF_REG_COS0_WEIGHT 0x15c054
2362/* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */
2363#define PBF_REG_COS0_WEIGHT_P0 0x15c2a8
2364/* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */
2365#define PBF_REG_COS0_WEIGHT_P1 0x15c2c0
2031/* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */ 2366/* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */
2032#define PBF_REG_COS1_UPPER_BOUND 0x15c060 2367#define PBF_REG_COS1_UPPER_BOUND 0x15c060
2033/* [RW 31] The weight of COS1 in the ETS command arbiter. */ 2368/* [RW 31] The weight of COS1 in the ETS command arbiter. */
2034#define PBF_REG_COS1_WEIGHT 0x15c058 2369#define PBF_REG_COS1_WEIGHT 0x15c058
2370/* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */
2371#define PBF_REG_COS1_WEIGHT_P0 0x15c2ac
2372/* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */
2373#define PBF_REG_COS1_WEIGHT_P1 0x15c2c4
2374/* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */
2375#define PBF_REG_COS2_WEIGHT_P0 0x15c2b0
2376/* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */
2377#define PBF_REG_COS2_WEIGHT_P1 0x15c2c8
2378/* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */
2379#define PBF_REG_COS3_WEIGHT_P0 0x15c2b4
2380/* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */
2381#define PBF_REG_COS4_WEIGHT_P0 0x15c2b8
2382/* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */
2383#define PBF_REG_COS5_WEIGHT_P0 0x15c2bc
2384/* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte
2385 * lines. */
2386#define PBF_REG_CREDIT_LB_Q 0x140338
2387/* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte
2388 * lines. */
2389#define PBF_REG_CREDIT_Q0 0x14033c
2390/* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte
2391 * lines. */
2392#define PBF_REG_CREDIT_Q1 0x140340
2035/* [RW 1] Disable processing further tasks from port 0 (after ending the 2393/* [RW 1] Disable processing further tasks from port 0 (after ending the
2036 current task in process). */ 2394 current task in process). */
2037#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c 2395#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
@@ -2042,6 +2400,52 @@
2042 current task in process). */ 2400 current task in process). */
2043#define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c 2401#define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
2044#define PBF_REG_DISABLE_PF 0x1402e8 2402#define PBF_REG_DISABLE_PF 0x1402e8
2403/* [RW 18] For port 0: For each client that is subject to WFQ (the
2404 * corresponding bit is 1); indicates to which of the credit registers this
2405 * client is mapped. For clients which are not credit blocked; their mapping
2406 * is dont care. */
2407#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288
2408/* [RW 9] For port 1: For each client that is subject to WFQ (the
2409 * corresponding bit is 1); indicates to which of the credit registers this
2410 * client is mapped. For clients which are not credit blocked; their mapping
2411 * is dont care. */
2412#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c
2413/* [RW 6] For port 0: Bit per client to indicate if the client competes in
2414 * the strict priority arbiter directly (corresponding bit = 1); or first
2415 * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2416 * lowest priority in the strict-priority arbiter. */
2417#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278
2418/* [RW 3] For port 1: Bit per client to indicate if the client competes in
2419 * the strict priority arbiter directly (corresponding bit = 1); or first
2420 * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2421 * lowest priority in the strict-priority arbiter. */
2422#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c
2423/* [RW 6] For port 0: Bit per client to indicate if the client is subject to
2424 * WFQ credit blocking (corresponding bit = 1). */
2425#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280
2426/* [RW 3] For port 0: Bit per client to indicate if the client is subject to
2427 * WFQ credit blocking (corresponding bit = 1). */
2428#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284
2429/* [RW 16] For port 0: The number of strict priority arbitration slots
2430 * between 2 RR arbitration slots. A value of 0 means no strict priority
2431 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2432 * arbiter. */
2433#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0
2434/* [RW 16] For port 1: The number of strict priority arbitration slots
2435 * between 2 RR arbitration slots. A value of 0 means no strict priority
2436 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2437 * arbiter. */
2438#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4
2439/* [RW 18] For port 0: Indicates which client is connected to each priority
2440 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2441 * priority 5 is the lowest; to which the RR output is connected to (this is
2442 * not configurable). */
2443#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270
2444/* [RW 9] For port 1: Indicates which client is connected to each priority
2445 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2446 * priority 5 is the lowest; to which the RR output is connected to (this is
2447 * not configurable). */
2448#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274
2045/* [RW 1] Indicates that ETS is performed between the COSes in the command 2449/* [RW 1] Indicates that ETS is performed between the COSes in the command
2046 * arbiter. If reset strict priority w/ anti-starvation will be performed 2450 * arbiter. If reset strict priority w/ anti-starvation will be performed
2047 * w/o WFQ. */ 2451 * w/o WFQ. */
@@ -2049,14 +2453,25 @@
2049/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2453/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2050 * Ethernet header. */ 2454 * Ethernet header. */
2051#define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8 2455#define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8
2052/* [RW 1] Indicates which COS is conncted to the highest priority in the 2456/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2053 * command arbiter. */ 2457#define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8
2458/* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
2459 * priority in the command arbiter. */
2054#define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c 2460#define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c
2055#define PBF_REG_IF_ENABLE_REG 0x140044 2461#define PBF_REG_IF_ENABLE_REG 0x140044
2056/* [RW 1] Init bit. When set the initial credits are copied to the credit 2462/* [RW 1] Init bit. When set the initial credits are copied to the credit
2057 registers (except the port credits). Should be set and then reset after 2463 registers (except the port credits). Should be set and then reset after
2058 the configuration of the block has ended. */ 2464 the configuration of the block has ended. */
2059#define PBF_REG_INIT 0x140000 2465#define PBF_REG_INIT 0x140000
2466/* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte
2467 * lines. */
2468#define PBF_REG_INIT_CRD_LB_Q 0x15c248
2469/* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
2470 * lines. */
2471#define PBF_REG_INIT_CRD_Q0 0x15c230
2472/* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte
2473 * lines. */
2474#define PBF_REG_INIT_CRD_Q1 0x15c234
2060/* [RW 1] Init bit for port 0. When set the initial credit of port 0 is 2475/* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
2061 copied to the credit register. Should be set and then reset after the 2476 copied to the credit register. Should be set and then reset after the
2062 configuration of the port has ended. */ 2477 configuration of the port has ended. */
@@ -2069,6 +2484,15 @@
2069 copied to the credit register. Should be set and then reset after the 2484 copied to the credit register. Should be set and then reset after the
2070 configuration of the port has ended. */ 2485 configuration of the port has ended. */
2071#define PBF_REG_INIT_P4 0x14000c 2486#define PBF_REG_INIT_P4 0x14000c
2487/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2488 * the LB queue. Reset upon init. */
2489#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354
2490/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2491 * queue 0. Reset upon init. */
2492#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358
2493/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2494 * queue 1. Reset upon init. */
2495#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c
2072/* [RW 1] Enable for mac interface 0. */ 2496/* [RW 1] Enable for mac interface 0. */
2073#define PBF_REG_MAC_IF0_ENABLE 0x140030 2497#define PBF_REG_MAC_IF0_ENABLE 0x140030
2074/* [RW 1] Enable for mac interface 1. */ 2498/* [RW 1] Enable for mac interface 1. */
@@ -2089,24 +2513,49 @@
2089/* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte 2513/* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
2090 lines. */ 2514 lines. */
2091#define PBF_REG_P0_INIT_CRD 0x1400d0 2515#define PBF_REG_P0_INIT_CRD 0x1400d0
2092/* [RW 1] Indication that pause is enabled for port 0. */ 2516/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2093#define PBF_REG_P0_PAUSE_ENABLE 0x140014 2517 * port 0. Reset upon init. */
2094/* [R 8] Number of tasks in port 0 task queue. */ 2518#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308
2519/* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
2520#define PBF_REG_P0_PAUSE_ENABLE 0x140014
2521/* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
2095#define PBF_REG_P0_TASK_CNT 0x140204 2522#define PBF_REG_P0_TASK_CNT 0x140204
2096/* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */ 2523/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2524 * freed from the task queue of port 0. Reset upon init. */
2525#define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0
2526/* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */
2527#define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc
2528/* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
2529 * buffers in 16 byte lines. */
2097#define PBF_REG_P1_CREDIT 0x140208 2530#define PBF_REG_P1_CREDIT 0x140208
2098/* [RW 11] Initial credit for port 1 in the tx port buffers in 16 byte 2531/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
2099 lines. */ 2532 * buffers in 16 byte lines. */
2100#define PBF_REG_P1_INIT_CRD 0x1400d4 2533#define PBF_REG_P1_INIT_CRD 0x1400d4
2101/* [R 8] Number of tasks in port 1 task queue. */ 2534/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2535 * port 1. Reset upon init. */
2536#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c
2537/* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
2102#define PBF_REG_P1_TASK_CNT 0x14020c 2538#define PBF_REG_P1_TASK_CNT 0x14020c
2539/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2540 * freed from the task queue of port 1. Reset upon init. */
2541#define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4
2542/* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */
2543#define PBF_REG_P1_TQ_OCCUPANCY 0x140300
2103/* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */ 2544/* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
2104#define PBF_REG_P4_CREDIT 0x140210 2545#define PBF_REG_P4_CREDIT 0x140210
2105/* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte 2546/* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
2106 lines. */ 2547 lines. */
2107#define PBF_REG_P4_INIT_CRD 0x1400e0 2548#define PBF_REG_P4_INIT_CRD 0x1400e0
2108/* [R 8] Number of tasks in port 4 task queue. */ 2549/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2550 * port 4. Reset upon init. */
2551#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310
2552/* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
2109#define PBF_REG_P4_TASK_CNT 0x140214 2553#define PBF_REG_P4_TASK_CNT 0x140214
2554/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2555 * freed from the task queue of port 4. Reset upon init. */
2556#define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8
2557/* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */
2558#define PBF_REG_P4_TQ_OCCUPANCY 0x140304
2110/* [RW 5] Interrupt mask register #0 read/write */ 2559/* [RW 5] Interrupt mask register #0 read/write */
2111#define PBF_REG_PBF_INT_MASK 0x1401d4 2560#define PBF_REG_PBF_INT_MASK 0x1401d4
2112/* [R 5] Interrupt register #0 read */ 2561/* [R 5] Interrupt register #0 read */
@@ -2115,6 +2564,27 @@
2115#define PBF_REG_PBF_PRTY_MASK 0x1401e4 2564#define PBF_REG_PBF_PRTY_MASK 0x1401e4
2116/* [RC 20] Parity register #0 read clear */ 2565/* [RC 20] Parity register #0 read clear */
2117#define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc 2566#define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
2567/* [RW 16] The Ethernet type value for L2 tag 0 */
2568#define PBF_REG_TAG_ETHERTYPE_0 0x15c090
2569/* [RW 4] The length of the info field for L2 tag 0. The length is between
2570 * 2B and 14B; in 2B granularity */
2571#define PBF_REG_TAG_LEN_0 0x15c09c
2572/* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task
2573 * queue. Reset upon init. */
2574#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c
2575/* [R 32] Cyclic counter for number of 8 byte lines freed from the task
2576 * queue 0. Reset upon init. */
2577#define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390
2578/* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1.
2579 * Reset upon init. */
2580#define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394
2581/* [R 13] Number of 8 bytes lines occupied in the task queue of the LB
2582 * queue. */
2583#define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8
2584/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */
2585#define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac
2586/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
2587#define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0
2118#define PB_REG_CONTROL 0 2588#define PB_REG_CONTROL 0
2119/* [RW 2] Interrupt mask register #0 read/write */ 2589/* [RW 2] Interrupt mask register #0 read/write */
2120#define PB_REG_PB_INT_MASK 0x28 2590#define PB_REG_PB_INT_MASK 0x28
@@ -2444,10 +2914,24 @@
2444/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2914/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2445 * Ethernet header. */ 2915 * Ethernet header. */
2446#define PRS_REG_HDRS_AFTER_BASIC 0x40238 2916#define PRS_REG_HDRS_AFTER_BASIC 0x40238
2917/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2918 * Ethernet header for port 0 packets. */
2919#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270
2920#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290
2921/* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2922#define PRS_REG_HDRS_AFTER_TAG_0 0x40248
2923/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
2924 * port 0 packets */
2925#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280
2926#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0
2447/* [RW 4] The increment value to send in the CFC load request message */ 2927/* [RW 4] The increment value to send in the CFC load request message */
2448#define PRS_REG_INC_VALUE 0x40048 2928#define PRS_REG_INC_VALUE 0x40048
2449/* [RW 6] Bit-map indicating which headers must appear in the packet */ 2929/* [RW 6] Bit-map indicating which headers must appear in the packet */
2450#define PRS_REG_MUST_HAVE_HDRS 0x40254 2930#define PRS_REG_MUST_HAVE_HDRS 0x40254
2931/* [RW 6] Bit-map indicating which headers must appear in the packet for
2932 * port 0 packets */
2933#define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c
2934#define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac
2451#define PRS_REG_NIC_MODE 0x40138 2935#define PRS_REG_NIC_MODE 0x40138
2452/* [RW 8] The 8-bit event ID for cases where there is no match on the 2936/* [RW 8] The 8-bit event ID for cases where there is no match on the
2453 connection. Used in packet start message to TCM. */ 2937 connection. Used in packet start message to TCM. */
@@ -2496,6 +2980,11 @@
2496#define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158 2980#define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
2497/* [R 4] debug only: SRC current credit. Transaction based. */ 2981/* [R 4] debug only: SRC current credit. Transaction based. */
2498#define PRS_REG_SRC_CURRENT_CREDIT 0x4016c 2982#define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
2983/* [RW 16] The Ethernet type value for L2 tag 0 */
2984#define PRS_REG_TAG_ETHERTYPE_0 0x401d4
2985/* [RW 4] The length of the info field for L2 tag 0. The length is between
2986 * 2B and 14B; in 2B granularity */
2987#define PRS_REG_TAG_LEN_0 0x4022c
2499/* [R 8] debug only: TCM current credit. Cycle based. */ 2988/* [R 8] debug only: TCM current credit. Cycle based. */
2500#define PRS_REG_TCM_CURRENT_CREDIT 0x40160 2989#define PRS_REG_TCM_CURRENT_CREDIT 0x40160
2501/* [R 8] debug only: TSDM current credit. Transaction based. */ 2990/* [R 8] debug only: TSDM current credit. Transaction based. */
@@ -3080,6 +3569,7 @@
3080#define QM_REG_BYTECREDITAFULLTHR 0x168094 3569#define QM_REG_BYTECREDITAFULLTHR 0x168094
3081/* [RW 4] The initial credit for interface */ 3570/* [RW 4] The initial credit for interface */
3082#define QM_REG_CMINITCRD_0 0x1680cc 3571#define QM_REG_CMINITCRD_0 0x1680cc
3572#define QM_REG_BYTECRDCMDQ_0 0x16e6e8
3083#define QM_REG_CMINITCRD_1 0x1680d0 3573#define QM_REG_CMINITCRD_1 0x1680d0
3084#define QM_REG_CMINITCRD_2 0x1680d4 3574#define QM_REG_CMINITCRD_2 0x1680d4
3085#define QM_REG_CMINITCRD_3 0x1680d8 3575#define QM_REG_CMINITCRD_3 0x1680d8
@@ -3170,7 +3660,10 @@
3170/* [RW 2] The PCI attributes field used in the PCI request. */ 3660/* [RW 2] The PCI attributes field used in the PCI request. */
3171#define QM_REG_PCIREQAT 0x168054 3661#define QM_REG_PCIREQAT 0x168054
3172#define QM_REG_PF_EN 0x16e70c 3662#define QM_REG_PF_EN 0x16e70c
3173/* [R 16] The byte credit of port 0 */ 3663/* [R 24] The number of tasks stored in the QM for the PF. only even
3664 * functions are valid in E2 (odd I registers will be hard wired to 0) */
3665#define QM_REG_PF_USG_CNT_0 0x16e040
3666/* [R 16] NOT USED */
3174#define QM_REG_PORT0BYTECRD 0x168300 3667#define QM_REG_PORT0BYTECRD 0x168300
3175/* [R 16] The byte credit of port 1 */ 3668/* [R 16] The byte credit of port 1 */
3176#define QM_REG_PORT1BYTECRD 0x168304 3669#define QM_REG_PORT1BYTECRD 0x168304
@@ -3782,6 +4275,8 @@
3782#define TM_REG_LIN0_LOGIC_ADDR 0x164240 4275#define TM_REG_LIN0_LOGIC_ADDR 0x164240
3783/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */ 4276/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
3784#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048 4277#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
4278/* [ST 16] Linear0 Number of scans counter. */
4279#define TM_REG_LIN0_NUM_SCANS 0x1640a0
3785/* [WB 64] Linear0 phy address. */ 4280/* [WB 64] Linear0 phy address. */
3786#define TM_REG_LIN0_PHY_ADDR 0x164270 4281#define TM_REG_LIN0_PHY_ADDR 0x164270
3787/* [RW 1] Linear0 physical address valid. */ 4282/* [RW 1] Linear0 physical address valid. */
@@ -3789,6 +4284,7 @@
3789#define TM_REG_LIN0_SCAN_ON 0x1640d0 4284#define TM_REG_LIN0_SCAN_ON 0x1640d0
3790/* [RW 24] Linear0 array scan timeout. */ 4285/* [RW 24] Linear0 array scan timeout. */
3791#define TM_REG_LIN0_SCAN_TIME 0x16403c 4286#define TM_REG_LIN0_SCAN_TIME 0x16403c
4287#define TM_REG_LIN0_VNIC_UC 0x164128
3792/* [RW 32] Linear1 logic address. */ 4288/* [RW 32] Linear1 logic address. */
3793#define TM_REG_LIN1_LOGIC_ADDR 0x164250 4289#define TM_REG_LIN1_LOGIC_ADDR 0x164250
3794/* [WB 64] Linear1 phy address. */ 4290/* [WB 64] Linear1 phy address. */
@@ -4175,6 +4671,8 @@
4175#define UCM_REG_UCM_INT_MASK 0xe01d4 4671#define UCM_REG_UCM_INT_MASK 0xe01d4
4176/* [R 11] Interrupt register #0 read */ 4672/* [R 11] Interrupt register #0 read */
4177#define UCM_REG_UCM_INT_STS 0xe01c8 4673#define UCM_REG_UCM_INT_STS 0xe01c8
4674/* [RW 27] Parity mask register #0 read/write */
4675#define UCM_REG_UCM_PRTY_MASK 0xe01e4
4178/* [R 27] Parity register #0 read */ 4676/* [R 27] Parity register #0 read */
4179#define UCM_REG_UCM_PRTY_STS 0xe01d8 4677#define UCM_REG_UCM_PRTY_STS 0xe01d8
4180/* [RC 27] Parity register #0 read clear */ 4678/* [RC 27] Parity register #0 read clear */
@@ -4265,6 +4763,17 @@
4265 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] - 4763 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
4266 header pointer. */ 4764 header pointer. */
4267#define UCM_REG_XX_TABLE 0xe0300 4765#define UCM_REG_XX_TABLE 0xe0300
4766#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15)
4767#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24)
4768#define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5)
4769#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4)
4770#define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1)
4771#define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13)
4772#define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0)
4773#define UMAC_REG_COMMAND_CONFIG 0x8
4774/* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive
4775 * logic to check frames. */
4776#define UMAC_REG_MAXFR 0x14
4268/* [RW 8] The event id for aggregated interrupt 0 */ 4777/* [RW 8] The event id for aggregated interrupt 0 */
4269#define USDM_REG_AGG_INT_EVENT_0 0xc4038 4778#define USDM_REG_AGG_INT_EVENT_0 0xc4038
4270#define USDM_REG_AGG_INT_EVENT_1 0xc403c 4779#define USDM_REG_AGG_INT_EVENT_1 0xc403c
@@ -4696,8 +5205,13 @@
4696#define XCM_REG_XCM_INT_MASK 0x202b4 5205#define XCM_REG_XCM_INT_MASK 0x202b4
4697/* [R 14] Interrupt register #0 read */ 5206/* [R 14] Interrupt register #0 read */
4698#define XCM_REG_XCM_INT_STS 0x202a8 5207#define XCM_REG_XCM_INT_STS 0x202a8
5208/* [RW 30] Parity mask register #0 read/write */
5209#define XCM_REG_XCM_PRTY_MASK 0x202c4
4699/* [R 30] Parity register #0 read */ 5210/* [R 30] Parity register #0 read */
4700#define XCM_REG_XCM_PRTY_STS 0x202b8 5211#define XCM_REG_XCM_PRTY_STS 0x202b8
5212/* [RC 30] Parity register #0 read clear */
5213#define XCM_REG_XCM_PRTY_STS_CLR 0x202bc
5214
4701/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS 5215/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
4702 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 5216 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4703 Is used to determine the number of the AG context REG-pairs written back; 5217 Is used to determine the number of the AG context REG-pairs written back;
@@ -4772,6 +5286,28 @@
4772#define XCM_REG_XX_MSG_NUM 0x20428 5286#define XCM_REG_XX_MSG_NUM 0x20428
4773/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 5287/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4774#define XCM_REG_XX_OVFL_EVNT_ID 0x20058 5288#define XCM_REG_XX_OVFL_EVNT_ID 0x20058
5289#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0)
5290#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1)
5291#define XMAC_CTRL_REG_CORE_LOCAL_LPBK (0x1<<3)
5292#define XMAC_CTRL_REG_RX_EN (0x1<<1)
5293#define XMAC_CTRL_REG_SOFT_RESET (0x1<<6)
5294#define XMAC_CTRL_REG_TX_EN (0x1<<0)
5295#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18)
5296#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17)
5297#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0)
5298#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3)
5299#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4)
5300#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5)
5301#define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60
5302#define XMAC_REG_CTRL 0
5303#define XMAC_REG_PAUSE_CTRL 0x68
5304#define XMAC_REG_PFC_CTRL 0x70
5305#define XMAC_REG_PFC_CTRL_HI 0x74
5306#define XMAC_REG_RX_LSS_STATUS 0x58
5307/* [RW 14] Maximum packet size in receive direction; exclusive of preamble &
5308 * CRC in strip mode */
5309#define XMAC_REG_RX_MAX_SIZE 0x40
5310#define XMAC_REG_TX_CTRL 0x20
4775/* [RW 16] Indirect access to the XX table of the XX protection mechanism. 5311/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4776 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] - 5312 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
4777 header pointer. */ 5313 header pointer. */
@@ -4846,6 +5382,10 @@
4846#define XSDM_REG_NUM_OF_Q9_CMD 0x166268 5382#define XSDM_REG_NUM_OF_Q9_CMD 0x166268
4847/* [RW 13] The start address in the internal RAM for queue counters */ 5383/* [RW 13] The start address in the internal RAM for queue counters */
4848#define XSDM_REG_Q_COUNTER_START_ADDR 0x166010 5384#define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
5385/* [W 17] Generate an operation after completion; bit-16 is
5386 * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and
5387 * bits 4:0 are the T124Param[4:0] */
5388#define XSDM_REG_OPERATION_GEN 0x1664c4
4849/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 5389/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4850#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548 5390#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
4851/* [R 1] parser fifo empty in sdm_sync block */ 5391/* [R 1] parser fifo empty in sdm_sync block */
@@ -5019,6 +5559,7 @@
5019#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3) 5559#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
5020#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3) 5560#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
5021#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3) 5561#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
5562#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)
5022#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3) 5563#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
5023#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3) 5564#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
5024#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3) 5565#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
@@ -5034,6 +5575,7 @@
5034#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3) 5575#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
5035#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3) 5576#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
5036#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3) 5577#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
5578#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)
5037#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3) 5579#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
5038#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3) 5580#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
5039#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3) 5581#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
@@ -5052,7 +5594,9 @@
5052#define EMAC_LED_OVERRIDE (1L<<0) 5594#define EMAC_LED_OVERRIDE (1L<<0)
5053#define EMAC_LED_TRAFFIC (1L<<6) 5595#define EMAC_LED_TRAFFIC (1L<<6)
5054#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26) 5596#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
5597#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
5055#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26) 5598#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
5599#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
5056#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26) 5600#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
5057#define EMAC_MDIO_COMM_DATA (0xffffL<<0) 5601#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
5058#define EMAC_MDIO_COMM_START_BUSY (1L<<29) 5602#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
@@ -5128,16 +5672,24 @@
5128#define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27) 5672#define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
5129#define MISC_REGISTERS_RESET_REG_1_SET 0x584 5673#define MISC_REGISTERS_RESET_REG_1_SET 0x584
5130#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 5674#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
5675#define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24)
5676#define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25)
5131#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0) 5677#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
5132#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14) 5678#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
5133#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15) 5679#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
5134#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4) 5680#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
5135#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6) 5681#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
5682#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
5683#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
5136#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5) 5684#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
5137#define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13) 5685#define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
5138#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11) 5686#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
5687#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13)
5139#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9) 5688#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
5140#define MISC_REGISTERS_RESET_REG_2_SET 0x594 5689#define MISC_REGISTERS_RESET_REG_2_SET 0x594
5690#define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20)
5691#define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22)
5692#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23)
5141#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8 5693#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
5142#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1) 5694#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
5143#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2) 5695#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
@@ -5160,74 +5712,86 @@
5160#define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1 5712#define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
5161#define MISC_REGISTERS_SPIO_OUTPUT_LOW 0 5713#define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
5162#define MISC_REGISTERS_SPIO_SET_POS 8 5714#define MISC_REGISTERS_SPIO_SET_POS 8
5715#define HW_LOCK_DRV_FLAGS 10
5163#define HW_LOCK_MAX_RESOURCE_VALUE 31 5716#define HW_LOCK_MAX_RESOURCE_VALUE 31
5164#define HW_LOCK_RESOURCE_GPIO 1 5717#define HW_LOCK_RESOURCE_GPIO 1
5165#define HW_LOCK_RESOURCE_MDIO 0 5718#define HW_LOCK_RESOURCE_MDIO 0
5166#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 5719#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
5167#define HW_LOCK_RESOURCE_RESERVED_08 8 5720#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
5721#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
5168#define HW_LOCK_RESOURCE_SPIO 2 5722#define HW_LOCK_RESOURCE_SPIO 2
5169#define HW_LOCK_RESOURCE_UNDI 5 5723#define HW_LOCK_RESOURCE_UNDI 5
5170#define PRS_FLAG_OVERETH_IPV4 1 5724#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
5171#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4) 5725#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
5172#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5) 5726#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
5173#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18) 5727#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31)
5174#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31) 5728#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
5175#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9) 5729#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
5176#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8) 5730#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
5177#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7) 5731#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
5178#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6) 5732#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
5179#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29) 5733#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
5180#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28) 5734#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
5181#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1) 5735#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
5182#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0) 5736#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
5183#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18) 5737#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
5184#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11) 5738#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
5185#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13) 5739#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
5186#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12) 5740#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
5187#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (1<<5) 5741#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
5188#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (1<<9) 5742#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
5189#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12) 5743#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
5190#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (1<<28) 5744#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
5191#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (1<<31) 5745#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1<<31)
5192#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (1<<29) 5746#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
5193#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (1<<30) 5747#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
5194#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15) 5748#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
5195#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14) 5749#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
5196#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20) 5750#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
5197#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0) 5751#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
5198#define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31) 5752#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31)
5199#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2) 5753#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
5200#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3) 5754#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
5201#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3) 5755#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
5202#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2) 5756#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
5203#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5) 5757#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
5204#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4) 5758#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
5205#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3) 5759#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
5206#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2) 5760#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
5207#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22) 5761#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
5208#define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15) 5762#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
5209#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27) 5763#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
5210#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5) 5764#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
5211#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25) 5765#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
5212#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24) 5766#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
5213#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29) 5767#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
5214#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28) 5768#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
5215#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23) 5769#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
5216#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27) 5770#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
5217#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26) 5771#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
5218#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21) 5772#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
5219#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20) 5773#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
5220#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25) 5774#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
5221#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24) 5775#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
5222#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16) 5776#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
5223#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9) 5777#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
5224#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7) 5778#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
5225#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6) 5779#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
5226#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11) 5780#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
5227#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10) 5781#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
5782#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
5783#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
5784#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
5785#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
5786#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
5787#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
5788
5789#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5)
5790#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9)
5791
5228#define RESERVED_GENERAL_ATTENTION_BIT_0 0 5792#define RESERVED_GENERAL_ATTENTION_BIT_0 0
5229 5793
5230#define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0 5794#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
5231#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000 5795#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
5232 5796
5233#define RESERVED_GENERAL_ATTENTION_BIT_6 6 5797#define RESERVED_GENERAL_ATTENTION_BIT_6 6
@@ -5317,7 +5881,13 @@
5317#define GRCBASE_HC 0x108000 5881#define GRCBASE_HC 0x108000
5318#define GRCBASE_PXP2 0x120000 5882#define GRCBASE_PXP2 0x120000
5319#define GRCBASE_PBF 0x140000 5883#define GRCBASE_PBF 0x140000
5884#define GRCBASE_UMAC0 0x160000
5885#define GRCBASE_UMAC1 0x160400
5320#define GRCBASE_XPB 0x161000 5886#define GRCBASE_XPB 0x161000
5887#define GRCBASE_MSTAT0 0x162000
5888#define GRCBASE_MSTAT1 0x162800
5889#define GRCBASE_XMAC0 0x163000
5890#define GRCBASE_XMAC1 0x163800
5321#define GRCBASE_TIMERS 0x164000 5891#define GRCBASE_TIMERS 0x164000
5322#define GRCBASE_XSDM 0x166000 5892#define GRCBASE_XSDM 0x166000
5323#define GRCBASE_QM 0x168000 5893#define GRCBASE_QM 0x168000
@@ -5883,6 +6453,10 @@
5883#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 6453#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
5884#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 6454#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
5885#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 6455#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
6456#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
6457#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
6458#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
6459#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
5886 6460
5887 6461
5888#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 6462#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
@@ -6036,11 +6610,6 @@ Theotherbitsarereservedandshouldbezero*/
6036/*bcm*/ 6610/*bcm*/
6037#define MDIO_PMA_REG_BCM_CTRL 0x0096 6611#define MDIO_PMA_REG_BCM_CTRL 0x0096
6038#define MDIO_PMA_REG_FEC_CTRL 0x00ab 6612#define MDIO_PMA_REG_FEC_CTRL 0x00ab
6039#define MDIO_PMA_REG_RX_ALARM_CTRL 0x9000
6040#define MDIO_PMA_REG_LASI_CTRL 0x9002
6041#define MDIO_PMA_REG_RX_ALARM 0x9003
6042#define MDIO_PMA_REG_TX_ALARM 0x9004
6043#define MDIO_PMA_REG_LASI_STATUS 0x9005
6044#define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800 6613#define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
6045#define MDIO_PMA_REG_DIGITAL_CTRL 0xc808 6614#define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
6046#define MDIO_PMA_REG_DIGITAL_STATUS 0xc809 6615#define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
@@ -6201,6 +6770,153 @@ Theotherbitsarereservedandshouldbezero*/
6201#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3 6770#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
6202#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080 6771#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
6203 6772
6773/* BCM84833 only */
6774#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
6775#define MDIO_84833_SUPER_ISOLATE 0x8000
6776/* These are mailbox register set used by 84833. */
6777#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
6778#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
6779#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
6780#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
6781#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
6782
6783/* Mailbox command set used by 84833. */
6784#define PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE 0x2
6785/* Mailbox status set used by 84833. */
6786#define PHY84833_CMD_RECEIVED 0x0001
6787#define PHY84833_CMD_IN_PROGRESS 0x0002
6788#define PHY84833_CMD_COMPLETE_PASS 0x0004
6789#define PHY84833_CMD_COMPLETE_ERROR 0x0008
6790#define PHY84833_CMD_OPEN_FOR_CMDS 0x0010
6791#define PHY84833_CMD_SYSTEM_BOOT 0x0020
6792#define PHY84833_CMD_NOT_OPEN_FOR_CMDS 0x0040
6793#define PHY84833_CMD_CLEAR_COMPLETE 0x0080
6794#define PHY84833_CMD_OPEN_OVERRIDE 0xa5a5
6795
6796/* Warpcore clause 45 addressing */
6797#define MDIO_WC_DEVAD 0x3
6798#define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
6799#define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
6800#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
6801#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
6802#define MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150 0x96
6803#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
6804#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
6805#define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
6806#define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
6807#define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
6808#define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
6809#define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
6810#define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
6811#define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
6812#define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
6813#define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
6814#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
6815#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
6816#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
6817#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6818#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
6819#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
6820#define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
6821#define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
6822#define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
6823#define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
6824#define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
6825#define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
6826#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
6827#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
6828#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
6829#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
6830#define MDIO_WC_REG_XGXS_STATUS3 0x8129
6831#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
6832#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
6833#define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
6834#define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
6835#define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
6836#define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
6837#define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
6838#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
6839#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
6840#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
6841#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
6842#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
6843#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
6844#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
6845#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
6846#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
6847#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
6848#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
6849#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
6850#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
6851#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
6852#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
6853#define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
6854#define MDIO_WC_REG_DSC_SMC 0x8213
6855#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
6856#define MDIO_WC_REG_TX_FIR_TAP 0x82e2
6857#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
6858#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
6859#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
6860#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
6861#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
6862#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
6863#define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
6864#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
6865#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
6866#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
6867#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
6868#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
6869#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
6870#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
6871#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
6872#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
6873#define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
6874#define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
6875#define MDIO_WC_REG_DIGITAL3_UP1 0x8329
6876#define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
6877#define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
6878#define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
6879#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
6880#define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
6881#define MDIO_WC_REG_TX66_CONTROL 0x83b0
6882#define MDIO_WC_REG_RX66_CONTROL 0x83c0
6883#define MDIO_WC_REG_RX66_SCW0 0x83c2
6884#define MDIO_WC_REG_RX66_SCW1 0x83c3
6885#define MDIO_WC_REG_RX66_SCW2 0x83c4
6886#define MDIO_WC_REG_RX66_SCW3 0x83c5
6887#define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
6888#define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
6889#define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
6890#define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
6891#define MDIO_WC_REG_FX100_CTRL1 0x8400
6892#define MDIO_WC_REG_FX100_CTRL3 0x8402
6893
6894#define MDIO_WC_REG_MICROBLK_CMD 0xffc2
6895#define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
6896#define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
6897
6898#define MDIO_WC_REG_AERBLK_AER 0xffde
6899#define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
6900#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
6901
6902#define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
6903#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
6904#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
6905
6906#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
6907
6908#define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
6909
6910/* 54616s */
6911#define MDIO_REG_INTR_STATUS 0x1a
6912#define MDIO_REG_INTR_MASK 0x1b
6913#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
6914#define MDIO_REG_GPHY_SHADOW 0x1c
6915#define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
6916#define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
6917#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
6918#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
6919
6204#define IGU_FUNC_BASE 0x0400 6920#define IGU_FUNC_BASE 0x0400
6205 6921
6206#define IGU_ADDR_MSIX 0x0000 6922#define IGU_ADDR_MSIX 0x0000
@@ -6217,11 +6933,6 @@ Theotherbitsarereservedandshouldbezero*/
6217#define IGU_ADDR_MSI_ADDR_HI 0x0212 6933#define IGU_ADDR_MSI_ADDR_HI 0x0212
6218#define IGU_ADDR_MSI_DATA 0x0213 6934#define IGU_ADDR_MSI_DATA 0x0213
6219 6935
6220#define IGU_INT_ENABLE 0
6221#define IGU_INT_DISABLE 1
6222#define IGU_INT_NOP 2
6223#define IGU_INT_NOP2 3
6224
6225#define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0 6936#define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0
6226#define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1 6937#define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1
6227#define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2 6938#define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2
@@ -6292,15 +7003,6 @@ Theotherbitsarereservedandshouldbezero*/
6292#define IGU_BC_BASE_DSB_PROD 128 7003#define IGU_BC_BASE_DSB_PROD 128
6293#define IGU_NORM_BASE_DSB_PROD 136 7004#define IGU_NORM_BASE_DSB_PROD 136
6294 7005
6295#define IGU_CTRL_CMD_TYPE_WR\
6296 1
6297#define IGU_CTRL_CMD_TYPE_RD\
6298 0
6299
6300#define IGU_SEG_ACCESS_NORM 0
6301#define IGU_SEG_ACCESS_DEF 1
6302#define IGU_SEG_ACCESS_ATTN 2
6303
6304 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \ 7006 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
6305 [5:2] = 0; [1:0] = PF number) */ 7007 [5:2] = 0; [1:0] = PF number) */
6306#define IGU_FID_ENCODE_IS_PF (0x1<<6) 7008#define IGU_FID_ENCODE_IS_PF (0x1<<6)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-12 22:02:36 -0500