diff options
Diffstat (limited to 'drivers/mfd/sec-irq.c')
| -rw-r--r-- | drivers/mfd/sec-irq.c | 204 |
1 files changed, 102 insertions, 102 deletions
diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c index 5e90cc1f0fd7..d9c11374ad0f 100644 --- a/drivers/mfd/sec-irq.c +++ b/drivers/mfd/sec-irq.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * s5m-irq.c | 2 | * sec-irq.c |
| 3 | * | 3 | * |
| 4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd | 4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd |
| 5 | * http://www.samsung.com | 5 | * http://www.samsung.com |
| @@ -16,12 +16,12 @@ | |||
| 16 | #include <linux/irq.h> | 16 | #include <linux/irq.h> |
| 17 | #include <linux/mfd/samsung/s5m-core.h> | 17 | #include <linux/mfd/samsung/s5m-core.h> |
| 18 | 18 | ||
| 19 | struct s5m_irq_data { | 19 | struct sec_irq_data { |
| 20 | int reg; | 20 | int reg; |
| 21 | int mask; | 21 | int mask; |
| 22 | }; | 22 | }; |
| 23 | 23 | ||
| 24 | static struct s5m_irq_data s5m8767_irqs[] = { | 24 | static struct sec_irq_data s5m8767_irqs[] = { |
| 25 | [S5M8767_IRQ_PWRR] = { | 25 | [S5M8767_IRQ_PWRR] = { |
| 26 | .reg = 1, | 26 | .reg = 1, |
| 27 | .mask = S5M8767_IRQ_PWRR_MASK, | 27 | .mask = S5M8767_IRQ_PWRR_MASK, |
| @@ -92,7 +92,7 @@ static struct s5m_irq_data s5m8767_irqs[] = { | |||
| 92 | }, | 92 | }, |
| 93 | }; | 93 | }; |
| 94 | 94 | ||
| 95 | static struct s5m_irq_data s5m8763_irqs[] = { | 95 | static struct sec_irq_data s5m8763_irqs[] = { |
| 96 | [S5M8763_IRQ_DCINF] = { | 96 | [S5M8763_IRQ_DCINF] = { |
| 97 | .reg = 1, | 97 | .reg = 1, |
| 98 | .mask = S5M8763_IRQ_DCINF_MASK, | 98 | .mask = S5M8763_IRQ_DCINF_MASK, |
| @@ -167,51 +167,51 @@ static struct s5m_irq_data s5m8763_irqs[] = { | |||
| 167 | }, | 167 | }, |
| 168 | }; | 168 | }; |
| 169 | 169 | ||
| 170 | static inline struct s5m_irq_data * | 170 | static inline struct sec_irq_data * |
| 171 | irq_to_s5m8767_irq(struct s5m87xx_dev *s5m87xx, int irq) | 171 | irq_to_s5m8767_irq(struct sec_pmic_dev *sec_pmic, int irq) |
| 172 | { | 172 | { |
| 173 | return &s5m8767_irqs[irq - s5m87xx->irq_base]; | 173 | return &s5m8767_irqs[irq - sec_pmic->irq_base]; |
| 174 | } | 174 | } |
| 175 | 175 | ||
| 176 | static void s5m8767_irq_lock(struct irq_data *data) | 176 | static void s5m8767_irq_lock(struct irq_data *data) |
| 177 | { | 177 | { |
| 178 | struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data); | 178 | struct sec_pmic_dev *sec_pmic = irq_data_get_irq_chip_data(data); |
| 179 | 179 | ||
| 180 | mutex_lock(&s5m87xx->irqlock); | 180 | mutex_lock(&sec_pmic->irqlock); |
| 181 | } | 181 | } |
| 182 | 182 | ||
| 183 | static void s5m8767_irq_sync_unlock(struct irq_data *data) | 183 | static void s5m8767_irq_sync_unlock(struct irq_data *data) |
| 184 | { | 184 | { |
| 185 | struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data); | 185 | struct sec_pmic_dev *sec_pmic = irq_data_get_irq_chip_data(data); |
| 186 | int i; | 186 | int i; |
| 187 | 187 | ||
| 188 | for (i = 0; i < ARRAY_SIZE(s5m87xx->irq_masks_cur); i++) { | 188 | for (i = 0; i < ARRAY_SIZE(sec_pmic->irq_masks_cur); i++) { |
| 189 | if (s5m87xx->irq_masks_cur[i] != s5m87xx->irq_masks_cache[i]) { | 189 | if (sec_pmic->irq_masks_cur[i] != sec_pmic->irq_masks_cache[i]) { |
| 190 | s5m87xx->irq_masks_cache[i] = s5m87xx->irq_masks_cur[i]; | 190 | sec_pmic->irq_masks_cache[i] = sec_pmic->irq_masks_cur[i]; |
| 191 | s5m_reg_write(s5m87xx, S5M8767_REG_INT1M + i, | 191 | sec_reg_write(sec_pmic, S5M8767_REG_INT1M + i, |
| 192 | s5m87xx->irq_masks_cur[i]); | 192 | sec_pmic->irq_masks_cur[i]); |
| 193 | } | 193 | } |
| 194 | } | 194 | } |
| 195 | 195 | ||
| 196 | mutex_unlock(&s5m87xx->irqlock); | 196 | mutex_unlock(&sec_pmic->irqlock); |
| 197 | } | 197 | } |
| 198 | 198 | ||
| 199 | static void s5m8767_irq_unmask(struct irq_data *data) | 199 | static void s5m8767_irq_unmask(struct irq_data *data) |
| 200 | { | 200 | { |
| 201 | struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data); | 201 | struct sec_pmic_dev *sec_pmic = irq_data_get_irq_chip_data(data); |
| 202 | struct s5m_irq_data *irq_data = irq_to_s5m8767_irq(s5m87xx, | 202 | struct sec_irq_data *irq_data = irq_to_s5m8767_irq(sec_pmic, |
| 203 | data->irq); | 203 | data->irq); |
| 204 | 204 | ||
| 205 | s5m87xx->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask; | 205 | sec_pmic->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask; |
| 206 | } | 206 | } |
| 207 | 207 | ||
| 208 | static void s5m8767_irq_mask(struct irq_data *data) | 208 | static void s5m8767_irq_mask(struct irq_data *data) |
| 209 | { | 209 | { |
| 210 | struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data); | 210 | struct sec_pmic_dev *sec_pmic = irq_data_get_irq_chip_data(data); |
| 211 | struct s5m_irq_data *irq_data = irq_to_s5m8767_irq(s5m87xx, | 211 | struct sec_irq_data *irq_data = irq_to_s5m8767_irq(sec_pmic, |
| 212 | data->irq); | 212 | data->irq); |
| 213 | 213 | ||
| 214 | s5m87xx->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask; | 214 | sec_pmic->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask; |
| 215 | } | 215 | } |
| 216 | 216 | ||
| 217 | static struct irq_chip s5m8767_irq_chip = { | 217 | static struct irq_chip s5m8767_irq_chip = { |
| @@ -222,51 +222,51 @@ static struct irq_chip s5m8767_irq_chip = { | |||
| 222 | .irq_unmask = s5m8767_irq_unmask, | 222 | .irq_unmask = s5m8767_irq_unmask, |
| 223 | }; | 223 | }; |
| 224 | 224 | ||
| 225 | static inline struct s5m_irq_data * | 225 | static inline struct sec_irq_data * |
| 226 | irq_to_s5m8763_irq(struct s5m87xx_dev *s5m87xx, int irq) | 226 | irq_to_s5m8763_irq(struct sec_pmic_dev *sec_pmic, int irq) |
| 227 | { | 227 | { |
| 228 | return &s5m8763_irqs[irq - s5m87xx->irq_base]; | 228 | return &s5m8763_irqs[irq - sec_pmic->irq_base]; |
| 229 | } | 229 | } |
| 230 | 230 | ||
| 231 | static void s5m8763_irq_lock(struct irq_data *data) | 231 | static void s5m8763_irq_lock(struct irq_data *data) |
| 232 | { | 232 | { |
| 233 | struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data); | 233 | struct sec_pmic_dev *sec_pmic = irq_data_get_irq_chip_data(data); |
| 234 | 234 | ||
| 235 | mutex_lock(&s5m87xx->irqlock); | 235 | mutex_lock(&sec_pmic->irqlock); |
| 236 | } | 236 | } |
| 237 | 237 | ||
| 238 | static void s5m8763_irq_sync_unlock(struct irq_data *data) | 238 | static void s5m8763_irq_sync_unlock(struct irq_data *data) |
| 239 | { | 239 | { |
| 240 | struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data); | 240 | struct sec_pmic_dev *sec_pmic = irq_data_get_irq_chip_data(data); |
| 241 | int i; | 241 | int i; |
| 242 | 242 | ||
| 243 | for (i = 0; i < ARRAY_SIZE(s5m87xx->irq_masks_cur); i++) { | 243 | for (i = 0; i < ARRAY_SIZE(sec_pmic->irq_masks_cur); i++) { |
| 244 | if (s5m87xx->irq_masks_cur[i] != s5m87xx->irq_masks_cache[i]) { | 244 | if (sec_pmic->irq_masks_cur[i] != sec_pmic->irq_masks_cache[i]) { |
| 245 | s5m87xx->irq_masks_cache[i] = s5m87xx->irq_masks_cur[i]; | 245 | sec_pmic->irq_masks_cache[i] = sec_pmic->irq_masks_cur[i]; |
| 246 | s5m_reg_write(s5m87xx, S5M8763_REG_IRQM1 + i, | 246 | sec_reg_write(sec_pmic, S5M8763_REG_IRQM1 + i, |
| 247 | s5m87xx->irq_masks_cur[i]); | 247 | sec_pmic->irq_masks_cur[i]); |
| 248 | } | 248 | } |
| 249 | } | 249 | } |
| 250 | 250 | ||
| 251 | mutex_unlock(&s5m87xx->irqlock); | 251 | mutex_unlock(&sec_pmic->irqlock); |
| 252 | } | 252 | } |
| 253 | 253 | ||
| 254 | static void s5m8763_irq_unmask(struct irq_data *data) | 254 | static void s5m8763_irq_unmask(struct irq_data *data) |
| 255 | { | 255 | { |
| 256 | struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data); | 256 | struct sec_pmic_dev *sec_pmic = irq_data_get_irq_chip_data(data); |
| 257 | struct s5m_irq_data *irq_data = irq_to_s5m8763_irq(s5m87xx, | 257 | struct sec_irq_data *irq_data = irq_to_s5m8763_irq(sec_pmic, |
| 258 | data->irq); | 258 | data->irq); |
| 259 | 259 | ||
| 260 | s5m87xx->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask; | 260 | sec_pmic->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask; |
| 261 | } | 261 | } |
| 262 | 262 | ||
| 263 | static void s5m8763_irq_mask(struct irq_data *data) | 263 | static void s5m8763_irq_mask(struct irq_data *data) |
| 264 | { | 264 | { |
| 265 | struct s5m87xx_dev *s5m87xx = irq_data_get_irq_chip_data(data); | 265 | struct sec_pmic_dev *sec_pmic = irq_data_get_irq_chip_data(data); |
| 266 | struct s5m_irq_data *irq_data = irq_to_s5m8763_irq(s5m87xx, | 266 | struct sec_irq_data *irq_data = irq_to_s5m8763_irq(sec_pmic, |
| 267 | data->irq); | 267 | data->irq); |
| 268 | 268 | ||
| 269 | s5m87xx->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask; | 269 | sec_pmic->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask; |
| 270 | } | 270 | } |
| 271 | 271 | ||
| 272 | static struct irq_chip s5m8763_irq_chip = { | 272 | static struct irq_chip s5m8763_irq_chip = { |
| @@ -280,26 +280,26 @@ static struct irq_chip s5m8763_irq_chip = { | |||
| 280 | 280 | ||
| 281 | static irqreturn_t s5m8767_irq_thread(int irq, void *data) | 281 | static irqreturn_t s5m8767_irq_thread(int irq, void *data) |
| 282 | { | 282 | { |
| 283 | struct s5m87xx_dev *s5m87xx = data; | 283 | struct sec_pmic_dev *sec_pmic = data; |
| 284 | u8 irq_reg[NUM_IRQ_REGS-1]; | 284 | u8 irq_reg[NUM_IRQ_REGS-1]; |
| 285 | int ret; | 285 | int ret; |
| 286 | int i; | 286 | int i; |
| 287 | 287 | ||
| 288 | 288 | ||
| 289 | ret = s5m_bulk_read(s5m87xx, S5M8767_REG_INT1, | 289 | ret = sec_bulk_read(sec_pmic, S5M8767_REG_INT1, |
| 290 | NUM_IRQ_REGS - 1, irq_reg); | 290 | NUM_IRQ_REGS - 1, irq_reg); |
| 291 | if (ret < 0) { | 291 | if (ret < 0) { |
| 292 | dev_err(s5m87xx->dev, "Failed to read interrupt register: %d\n", | 292 | dev_err(sec_pmic->dev, "Failed to read interrupt register: %d\n", |
| 293 | ret); | 293 | ret); |
| 294 | return IRQ_NONE; | 294 | return IRQ_NONE; |
| 295 | } | 295 | } |
| 296 | 296 | ||
| 297 | for (i = 0; i < NUM_IRQ_REGS - 1; i++) | 297 | for (i = 0; i < NUM_IRQ_REGS - 1; i++) |
| 298 | irq_reg[i] &= ~s5m87xx->irq_masks_cur[i]; | 298 | irq_reg[i] &= ~sec_pmic->irq_masks_cur[i]; |
| 299 | 299 | ||
| 300 | for (i = 0; i < S5M8767_IRQ_NR; i++) { | 300 | for (i = 0; i < S5M8767_IRQ_NR; i++) { |
| 301 | if (irq_reg[s5m8767_irqs[i].reg - 1] & s5m8767_irqs[i].mask) | 301 | if (irq_reg[s5m8767_irqs[i].reg - 1] & s5m8767_irqs[i].mask) |
| 302 | handle_nested_irq(s5m87xx->irq_base + i); | 302 | handle_nested_irq(sec_pmic->irq_base + i); |
| 303 | } | 303 | } |
| 304 | 304 | ||
| 305 | return IRQ_HANDLED; | 305 | return IRQ_HANDLED; |
| @@ -307,44 +307,44 @@ static irqreturn_t s5m8767_irq_thread(int irq, void *data) | |||
| 307 | 307 | ||
| 308 | static irqreturn_t s5m8763_irq_thread(int irq, void *data) | 308 | static irqreturn_t s5m8763_irq_thread(int irq, void *data) |
| 309 | { | 309 | { |
| 310 | struct s5m87xx_dev *s5m87xx = data; | 310 | struct sec_pmic_dev *sec_pmic = data; |
| 311 | u8 irq_reg[NUM_IRQ_REGS]; | 311 | u8 irq_reg[NUM_IRQ_REGS]; |
| 312 | int ret; | 312 | int ret; |
| 313 | int i; | 313 | int i; |
| 314 | 314 | ||
| 315 | ret = s5m_bulk_read(s5m87xx, S5M8763_REG_IRQ1, | 315 | ret = sec_bulk_read(sec_pmic, S5M8763_REG_IRQ1, |
| 316 | NUM_IRQ_REGS, irq_reg); | 316 | NUM_IRQ_REGS, irq_reg); |
| 317 | if (ret < 0) { | 317 | if (ret < 0) { |
| 318 | dev_err(s5m87xx->dev, "Failed to read interrupt register: %d\n", | 318 | dev_err(sec_pmic->dev, "Failed to read interrupt register: %d\n", |
| 319 | ret); | 319 | ret); |
| 320 | return IRQ_NONE; | 320 | return IRQ_NONE; |
| 321 | } | 321 | } |
| 322 | 322 | ||
| 323 | for (i = 0; i < NUM_IRQ_REGS; i++) | 323 | for (i = 0; i < NUM_IRQ_REGS; i++) |
| 324 | irq_reg[i] &= ~s5m87xx->irq_masks_cur[i]; | 324 | irq_reg[i] &= ~sec_pmic->irq_masks_cur[i]; |
| 325 | 325 | ||
| 326 | for (i = 0; i < S5M8763_IRQ_NR; i++) { | 326 | for (i = 0; i < S5M8763_IRQ_NR; i++) { |
| 327 | if (irq_reg[s5m8763_irqs[i].reg - 1] & s5m8763_irqs[i].mask) | 327 | if (irq_reg[s5m8763_irqs[i].reg - 1] & s5m8763_irqs[i].mask) |
| 328 | handle_nested_irq(s5m87xx->irq_base + i); | 328 | handle_nested_irq(sec_pmic->irq_base + i); |
| 329 | } | 329 | } |
| 330 | 330 | ||
| 331 | return IRQ_HANDLED; | 331 | return IRQ_HANDLED; |
| 332 | } | 332 | } |
| 333 | 333 | ||
| 334 | int s5m_irq_resume(struct s5m87xx_dev *s5m87xx) | 334 | int sec_irq_resume(struct sec_pmic_dev *sec_pmic) |
| 335 | { | 335 | { |
| 336 | if (s5m87xx->irq && s5m87xx->irq_base) { | 336 | if (sec_pmic->irq && sec_pmic->irq_base) { |
| 337 | switch (s5m87xx->device_type) { | 337 | switch (sec_pmic->device_type) { |
| 338 | case S5M8763X: | 338 | case S5M8763X: |
| 339 | s5m8763_irq_thread(s5m87xx->irq_base, s5m87xx); | 339 | s5m8763_irq_thread(sec_pmic->irq_base, sec_pmic); |
| 340 | break; | 340 | break; |
| 341 | case S5M8767X: | 341 | case S5M8767X: |
| 342 | s5m8767_irq_thread(s5m87xx->irq_base, s5m87xx); | 342 | s5m8767_irq_thread(sec_pmic->irq_base, sec_pmic); |
| 343 | break; | 343 | break; |
| 344 | default: | 344 | default: |
| 345 | dev_err(s5m87xx->dev, | 345 | dev_err(sec_pmic->dev, |
| 346 | "Unknown device type %d\n", | 346 | "Unknown device type %d\n", |
| 347 | s5m87xx->device_type); | 347 | sec_pmic->device_type); |
| 348 | return -EINVAL; | 348 | return -EINVAL; |
| 349 | 349 | ||
| 350 | } | 350 | } |
| @@ -352,43 +352,43 @@ int s5m_irq_resume(struct s5m87xx_dev *s5m87xx) | |||
| 352 | return 0; | 352 | return 0; |
| 353 | } | 353 | } |
| 354 | 354 | ||
| 355 | int s5m_irq_init(struct s5m87xx_dev *s5m87xx) | 355 | int sec_irq_init(struct sec_pmic_dev *sec_pmic) |
| 356 | { | 356 | { |
| 357 | int i; | 357 | int i; |
| 358 | int cur_irq; | 358 | int cur_irq; |
| 359 | int ret = 0; | 359 | int ret = 0; |
| 360 | int type = s5m87xx->device_type; | 360 | int type = sec_pmic->device_type; |
| 361 | 361 | ||
| 362 | if (!s5m87xx->irq) { | 362 | if (!sec_pmic->irq) { |
| 363 | dev_warn(s5m87xx->dev, | 363 | dev_warn(sec_pmic->dev, |
| 364 | "No interrupt specified, no interrupts\n"); | 364 | "No interrupt specified, no interrupts\n"); |
| 365 | s5m87xx->irq_base = 0; | 365 | sec_pmic->irq_base = 0; |
| 366 | return 0; | 366 | return 0; |
| 367 | } | 367 | } |
| 368 | 368 | ||
| 369 | if (!s5m87xx->irq_base) { | 369 | if (!sec_pmic->irq_base) { |
| 370 | dev_err(s5m87xx->dev, | 370 | dev_err(sec_pmic->dev, |
| 371 | "No interrupt base specified, no interrupts\n"); | 371 | "No interrupt base specified, no interrupts\n"); |
| 372 | return 0; | 372 | return 0; |
| 373 | } | 373 | } |
| 374 | 374 | ||
| 375 | mutex_init(&s5m87xx->irqlock); | 375 | mutex_init(&sec_pmic->irqlock); |
| 376 | 376 | ||
| 377 | switch (type) { | 377 | switch (type) { |
| 378 | case S5M8763X: | 378 | case S5M8763X: |
| 379 | for (i = 0; i < NUM_IRQ_REGS; i++) { | 379 | for (i = 0; i < NUM_IRQ_REGS; i++) { |
| 380 | s5m87xx->irq_masks_cur[i] = 0xff; | 380 | sec_pmic->irq_masks_cur[i] = 0xff; |
| 381 | s5m87xx->irq_masks_cache[i] = 0xff; | 381 | sec_pmic->irq_masks_cache[i] = 0xff; |
| 382 | s5m_reg_write(s5m87xx, S5M8763_REG_IRQM1 + i, | 382 | sec_reg_write(sec_pmic, S5M8763_REG_IRQM1 + i, |
| 383 | 0xff); | 383 | 0xff); |
| 384 | } | 384 | } |
| 385 | 385 | ||
| 386 | s5m_reg_write(s5m87xx, S5M8763_REG_STATUSM1, 0xff); | 386 | sec_reg_write(sec_pmic, S5M8763_REG_STATUSM1, 0xff); |
| 387 | s5m_reg_write(s5m87xx, S5M8763_REG_STATUSM2, 0xff); | 387 | sec_reg_write(sec_pmic, S5M8763_REG_STATUSM2, 0xff); |
| 388 | 388 | ||
| 389 | for (i = 0; i < S5M8763_IRQ_NR; i++) { | 389 | for (i = 0; i < S5M8763_IRQ_NR; i++) { |
| 390 | cur_irq = i + s5m87xx->irq_base; | 390 | cur_irq = i + sec_pmic->irq_base; |
| 391 | irq_set_chip_data(cur_irq, s5m87xx); | 391 | irq_set_chip_data(cur_irq, sec_pmic); |
| 392 | irq_set_chip_and_handler(cur_irq, &s5m8763_irq_chip, | 392 | irq_set_chip_and_handler(cur_irq, &s5m8763_irq_chip, |
| 393 | handle_edge_irq); | 393 | handle_edge_irq); |
| 394 | irq_set_nested_thread(cur_irq, 1); | 394 | irq_set_nested_thread(cur_irq, 1); |
| @@ -399,30 +399,30 @@ int s5m_irq_init(struct s5m87xx_dev *s5m87xx) | |||
| 399 | #endif | 399 | #endif |
| 400 | } | 400 | } |
| 401 | 401 | ||
| 402 | ret = request_threaded_irq(s5m87xx->irq, NULL, | 402 | ret = request_threaded_irq(sec_pmic->irq, NULL, |
| 403 | s5m8763_irq_thread, | 403 | s5m8763_irq_thread, |
| 404 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, | 404 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, |
| 405 | "s5m87xx-irq", s5m87xx); | 405 | "sec-pmic-irq", sec_pmic); |
| 406 | if (ret) { | 406 | if (ret) { |
| 407 | dev_err(s5m87xx->dev, "Failed to request IRQ %d: %d\n", | 407 | dev_err(sec_pmic->dev, "Failed to request IRQ %d: %d\n", |
| 408 | s5m87xx->irq, ret); | 408 | sec_pmic->irq, ret); |
| 409 | return ret; | 409 | return ret; |
| 410 | } | 410 | } |
| 411 | break; | 411 | break; |
| 412 | case S5M8767X: | 412 | case S5M8767X: |
| 413 | for (i = 0; i < NUM_IRQ_REGS - 1; i++) { | 413 | for (i = 0; i < NUM_IRQ_REGS - 1; i++) { |
| 414 | s5m87xx->irq_masks_cur[i] = 0xff; | 414 | sec_pmic->irq_masks_cur[i] = 0xff; |
| 415 | s5m87xx->irq_masks_cache[i] = 0xff; | 415 | sec_pmic->irq_masks_cache[i] = 0xff; |
| 416 | s5m_reg_write(s5m87xx, S5M8767_REG_INT1M + i, | 416 | sec_reg_write(sec_pmic, S5M8767_REG_INT1M + i, |
| 417 | 0xff); | 417 | 0xff); |
| 418 | } | 418 | } |
| 419 | for (i = 0; i < S5M8767_IRQ_NR; i++) { | 419 | for (i = 0; i < S5M8767_IRQ_NR; i++) { |
| 420 | cur_irq = i + s5m87xx->irq_base; | 420 | cur_irq = i + sec_pmic->irq_base; |
| 421 | irq_set_chip_data(cur_irq, s5m87xx); | 421 | irq_set_chip_data(cur_irq, sec_pmic); |
| 422 | if (ret) { | 422 | if (ret) { |
| 423 | dev_err(s5m87xx->dev, | 423 | dev_err(sec_pmic->dev, |
| 424 | "Failed to irq_set_chip_data %d: %d\n", | 424 | "Failed to irq_set_chip_data %d: %d\n", |
| 425 | s5m87xx->irq, ret); | 425 | sec_pmic->irq, ret); |
| 426 | return ret; | 426 | return ret; |
| 427 | } | 427 | } |
| 428 | 428 | ||
| @@ -436,40 +436,40 @@ int s5m_irq_init(struct s5m87xx_dev *s5m87xx) | |||
| 436 | #endif | 436 | #endif |
| 437 | } | 437 | } |
| 438 | 438 | ||
| 439 | ret = request_threaded_irq(s5m87xx->irq, NULL, | 439 | ret = request_threaded_irq(sec_pmic->irq, NULL, |
| 440 | s5m8767_irq_thread, | 440 | s5m8767_irq_thread, |
| 441 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, | 441 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, |
| 442 | "s5m87xx-irq", s5m87xx); | 442 | "sec-pmic-irq", sec_pmic); |
| 443 | if (ret) { | 443 | if (ret) { |
| 444 | dev_err(s5m87xx->dev, "Failed to request IRQ %d: %d\n", | 444 | dev_err(sec_pmic->dev, "Failed to request IRQ %d: %d\n", |
| 445 | s5m87xx->irq, ret); | 445 | sec_pmic->irq, ret); |
| 446 | return ret; | 446 | return ret; |
| 447 | } | 447 | } |
| 448 | break; | 448 | break; |
| 449 | default: | 449 | default: |
| 450 | dev_err(s5m87xx->dev, | 450 | dev_err(sec_pmic->dev, |
| 451 | "Unknown device type %d\n", s5m87xx->device_type); | 451 | "Unknown device type %d\n", sec_pmic->device_type); |
| 452 | return -EINVAL; | 452 | return -EINVAL; |
| 453 | } | 453 | } |
| 454 | 454 | ||
| 455 | if (!s5m87xx->ono) | 455 | if (!sec_pmic->ono) |
| 456 | return 0; | 456 | return 0; |
| 457 | 457 | ||
| 458 | switch (type) { | 458 | switch (type) { |
| 459 | case S5M8763X: | 459 | case S5M8763X: |
| 460 | ret = request_threaded_irq(s5m87xx->ono, NULL, | 460 | ret = request_threaded_irq(sec_pmic->ono, NULL, |
| 461 | s5m8763_irq_thread, | 461 | s5m8763_irq_thread, |
| 462 | IRQF_TRIGGER_FALLING | | 462 | IRQF_TRIGGER_FALLING | |
| 463 | IRQF_TRIGGER_RISING | | 463 | IRQF_TRIGGER_RISING | |
| 464 | IRQF_ONESHOT, "s5m87xx-ono", | 464 | IRQF_ONESHOT, "sec_pmic-ono", |
| 465 | s5m87xx); | 465 | sec_pmic); |
| 466 | break; | 466 | break; |
| 467 | case S5M8767X: | 467 | case S5M8767X: |
| 468 | ret = request_threaded_irq(s5m87xx->ono, NULL, | 468 | ret = request_threaded_irq(sec_pmic->ono, NULL, |
| 469 | s5m8767_irq_thread, | 469 | s5m8767_irq_thread, |
| 470 | IRQF_TRIGGER_FALLING | | 470 | IRQF_TRIGGER_FALLING | |
| 471 | IRQF_TRIGGER_RISING | | 471 | IRQF_TRIGGER_RISING | |
| 472 | IRQF_ONESHOT, "s5m87xx-ono", s5m87xx); | 472 | IRQF_ONESHOT, "sec_pmic-ono", sec_pmic); |
| 473 | break; | 473 | break; |
| 474 | default: | 474 | default: |
| 475 | ret = -EINVAL; | 475 | ret = -EINVAL; |
| @@ -477,19 +477,19 @@ int s5m_irq_init(struct s5m87xx_dev *s5m87xx) | |||
| 477 | } | 477 | } |
| 478 | 478 | ||
| 479 | if (ret) { | 479 | if (ret) { |
| 480 | dev_err(s5m87xx->dev, "Failed to request IRQ %d: %d\n", | 480 | dev_err(sec_pmic->dev, "Failed to request IRQ %d: %d\n", |
| 481 | s5m87xx->ono, ret); | 481 | sec_pmic->ono, ret); |
| 482 | return ret; | 482 | return ret; |
| 483 | } | 483 | } |
| 484 | 484 | ||
| 485 | return 0; | 485 | return 0; |
| 486 | } | 486 | } |
| 487 | 487 | ||
| 488 | void s5m_irq_exit(struct s5m87xx_dev *s5m87xx) | 488 | void sec_irq_exit(struct sec_pmic_dev *sec_pmic) |
| 489 | { | 489 | { |
| 490 | if (s5m87xx->ono) | 490 | if (sec_pmic->ono) |
| 491 | free_irq(s5m87xx->ono, s5m87xx); | 491 | free_irq(sec_pmic->ono, sec_pmic); |
| 492 | 492 | ||
| 493 | if (s5m87xx->irq) | 493 | if (sec_pmic->irq) |
| 494 | free_irq(s5m87xx->irq, s5m87xx); | 494 | free_irq(sec_pmic->irq, sec_pmic); |
| 495 | } | 495 | } |
