88 files changed, 3200 insertions, 1790 deletions
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index fa19c2b9820f..d91fb8c0b7b3 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -283,7 +283,7 @@ EXPORT_SYMBOL(drm_mode_object_find);
 * functions & device file and adds it to the master fd list.
 *
 * RETURNS:
- * Zero on success, error code on falure.
+ * Zero on success, error code on failure.
 */
 int drm_framebuffer_init(struct drm_device *dev, struct drm_framebuffer *fb,
                         const struct drm_framebuffer_funcs *funcs)
@@ -2434,7 +2434,7 @@ int drm_mode_connector_property_set_ioctl(struct drm_device *dev,
        } else if (connector->funcs->set_property)
                ret = connector->funcs->set_property(connector, property, out_resp->value);
-        /* store the property value if succesful */
+        /* store the property value if successful */
        if (!ret)
                drm_connector_property_set_value(connector, property, out_resp->value);
 out:
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index 7d0f00a935fa..f2aaf39be398 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -836,11 +836,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
                        mode_changed = true;
                } else if (set->fb == NULL) {
                        mode_changed = true;
-                } else if ((set->fb->bits_per_pixel !=
+                } else
-                         set->crtc->fb->bits_per_pixel) ||
-                         set->fb->depth != set->crtc->fb->depth)
-                        fb_changed = true;
-                else
                        fb_changed = true;
        }
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 766c46875a20..f3c58e2bd75c 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -125,28 +125,28 @@ static struct drm_ioctl_desc drm_ioctls[] = {
        DRM_IOCTL_DEF(DRM_IOCTL_UPDATE_DRAW, drm_update_drawable_info, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
-        DRM_IOCTL_DEF(DRM_IOCTL_GEM_CLOSE, drm_gem_close_ioctl, 0),
+        DRM_IOCTL_DEF(DRM_IOCTL_GEM_CLOSE, drm_gem_close_ioctl, DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_GEM_FLINK, drm_gem_flink_ioctl, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_IOCTL_GEM_FLINK, drm_gem_flink_ioctl, DRM_AUTH|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_GEM_OPEN, drm_gem_open_ioctl, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_IOCTL_GEM_OPEN, drm_gem_open_ioctl, DRM_AUTH|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETRESOURCES, drm_mode_getresources, DRM_MASTER|DRM_CONTROL_ALLOW),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETRESOURCES, drm_mode_getresources, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCRTC, drm_mode_getcrtc, DRM_MASTER|DRM_CONTROL_ALLOW),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCRTC, drm_mode_getcrtc, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETCRTC, drm_mode_setcrtc, DRM_MASTER|DRM_CONTROL_ALLOW),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETCRTC, drm_mode_setcrtc, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR, drm_mode_cursor_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR, drm_mode_cursor_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETGAMMA, drm_mode_gamma_get_ioctl, DRM_MASTER),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETGAMMA, drm_mode_gamma_get_ioctl, DRM_MASTER|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETGAMMA, drm_mode_gamma_set_ioctl, DRM_MASTER),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETGAMMA, drm_mode_gamma_set_ioctl, DRM_MASTER|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETENCODER, drm_mode_getencoder, DRM_MASTER|DRM_CONTROL_ALLOW),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETENCODER, drm_mode_getencoder, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCONNECTOR, drm_mode_getconnector, DRM_MASTER|DRM_CONTROL_ALLOW),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCONNECTOR, drm_mode_getconnector, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_ATTACHMODE, drm_mode_attachmode_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_ATTACHMODE, drm_mode_attachmode_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_DETACHMODE, drm_mode_detachmode_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_DETACHMODE, drm_mode_detachmode_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPERTY, drm_mode_getproperty_ioctl, DRM_MASTER | DRM_CONTROL_ALLOW),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPERTY, drm_mode_getproperty_ioctl, DRM_MASTER | DRM_CONTROL_ALLOW|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETPROPERTY, drm_mode_connector_property_set_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETPROPERTY, drm_mode_connector_property_set_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPBLOB, drm_mode_getblob_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPBLOB, drm_mode_getblob_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETFB, drm_mode_getfb, DRM_MASTER|DRM_CONTROL_ALLOW),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETFB, drm_mode_getfb, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_ADDFB, drm_mode_addfb, DRM_MASTER|DRM_CONTROL_ALLOW),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_ADDFB, drm_mode_addfb, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_RMFB, drm_mode_rmfb, DRM_MASTER|DRM_CONTROL_ALLOW),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_RMFB, drm_mode_rmfb, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_PAGE_FLIP, drm_mode_page_flip_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_PAGE_FLIP, drm_mode_page_flip_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
-        DRM_IOCTL_DEF(DRM_IOCTL_MODE_DIRTYFB, drm_mode_dirtyfb_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW)
+        DRM_IOCTL_DEF(DRM_IOCTL_MODE_DIRTYFB, drm_mode_dirtyfb_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED)
 };
 #define DRM_CORE_IOCTL_COUNT    ARRAY_SIZE( drm_ioctls )
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index f41e91ceaea6..f97e7c42ac8e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -598,6 +598,50 @@ struct drm_display_mode *drm_mode_std(struct drm_device *dev,
        return mode;
 }
+/*
+ * EDID is delightfully ambiguous about how interlaced modes are to be
+ * encoded.  Our internal representation is of frame height, but some
+ * HDTV detailed timings are encoded as field height.
+ *
+ * The format list here is from CEA, in frame size.  Technically we
+ * should be checking refresh rate too.  Whatever.
+ */
+static void
+drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
+                            struct detailed_pixel_timing *pt)
+{
+        int i;
+        static const struct {
+                int w, h;
+        } cea_interlaced[] = {
+                { 1920, 1080 },
+                {  720,  480 },
+                { 1440,  480 },
+                { 2880,  480 },
+                {  720,  576 },
+                { 1440,  576 },
+                { 2880,  576 },
+        };
+        static const int n_sizes =
+                sizeof(cea_interlaced)/sizeof(cea_interlaced[0]);
+        if (!(pt->misc & DRM_EDID_PT_INTERLACED))
+                return;
+        for (i = 0; i < n_sizes; i++) {
+                if ((mode->hdisplay == cea_interlaced[i].w) &&
+                    (mode->vdisplay == cea_interlaced[i].h / 2)) {
+                        mode->vdisplay *= 2;
+                        mode->vsync_start *= 2;
+                        mode->vsync_end *= 2;
+                        mode->vtotal *= 2;
+                        mode->vtotal |= 1;
+                }
+        }
+        mode->flags |= DRM_MODE_FLAG_INTERLACE;
+}
 /**
 * drm_mode_detailed - create a new mode from an EDID detailed timing section
 * @dev: DRM device (needed to create new mode)
@@ -680,8 +724,7 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
        drm_mode_set_name(mode);
-        if (pt->misc & DRM_EDID_PT_INTERLACED)
+        drm_mode_do_interlace_quirk(mode, pt);
-                mode->flags |= DRM_MODE_FLAG_INTERLACE;
        if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
                pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 0f9e90552dc4..50549703584f 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -27,6 +27,7 @@
 *      Dave Airlie <airlied@linux.ie>
 *      Jesse Barnes <jesse.barnes@intel.com>
 */
+#include <linux/kernel.h>
 #include <linux/sysrq.h>
 #include <linux/fb.h>
 #include "drmP.h"
@@ -50,21 +51,6 @@ int drm_fb_helper_add_connector(struct drm_connector *connector)
 }
 EXPORT_SYMBOL(drm_fb_helper_add_connector);
-static int my_atoi(const char *name)
-{
-        int val = 0;
-        for (;; name++) {
-                switch (*name) {
-                case '0' ... '9':
-                        val = 10*val+(*name-'0');
-                        break;
-                default:
-                        return val;
-                }
-        }
-}
 /**
 * drm_fb_helper_connector_parse_command_line - parse command line for connector
 * @connector - connector to parse line for
@@ -111,7 +97,7 @@ static bool drm_fb_helper_connector_parse_command_line(struct drm_connector *con
                        namelen = i;
                        if (!refresh_specified && !bpp_specified &&
                            !yres_specified) {
-                                refresh = my_atoi(&name[i+1]);
+                                refresh = simple_strtol(&name[i+1], NULL, 10);
                                refresh_specified = 1;
                                if (cvt || rb)
                                        cvt = 0;
@@ -121,7 +107,7 @@ static bool drm_fb_helper_connector_parse_command_line(struct drm_connector *con
                case '-':
                        namelen = i;
                        if (!bpp_specified && !yres_specified) {
-                                bpp = my_atoi(&name[i+1]);
+                                bpp = simple_strtol(&name[i+1], NULL, 10);
                                bpp_specified = 1;
                                if (cvt || rb)
                                        cvt = 0;
@@ -130,7 +116,7 @@ static bool drm_fb_helper_connector_parse_command_line(struct drm_connector *con
                        break;
                case 'x':
                        if (!yres_specified) {
-                                yres = my_atoi(&name[i+1]);
+                                yres = simple_strtol(&name[i+1], NULL, 10);
                                yres_specified = 1;
                        } else
                                goto done;
@@ -170,7 +156,7 @@ static bool drm_fb_helper_connector_parse_command_line(struct drm_connector *con
                }
        }
        if (i < 0 && yres_specified) {
-                xres = my_atoi(name);
+                xres = simple_strtol(name, NULL, 10);
                res_specified = 1;
        }
 done:
@@ -694,7 +680,7 @@ int drm_fb_helper_set_par(struct fb_info *info)
        int i;
        if (var->pixclock != 0) {
-                DRM_ERROR("PIXEL CLCOK SET\n");
+                DRM_ERROR("PIXEL CLOCK SET\n");
                return -EINVAL;
        }
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index e9dbb481c469..aa89d4b0b4c4 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -142,19 +142,6 @@ drm_gem_object_alloc(struct drm_device *dev, size_t size)
        if (IS_ERR(obj->filp))
                goto free;
-        /* Basically we want to disable the OOM killer and handle ENOMEM
-         * ourselves by sacrificing pages from cached buffers.
-         * XXX shmem_file_[gs]et_gfp_mask()
-         */
-        mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping,
-                             GFP_HIGHUSER |
-                             __GFP_COLD |
-                             __GFP_FS |
-                             __GFP_RECLAIMABLE |
-                             __GFP_NORETRY |
-                             __GFP_NOWARN |
-                             __GFP_NOMEMALLOC);
        kref_init(&obj->refcount);
        kref_init(&obj->handlecount);
        obj->size = size;
@@ -205,9 +192,7 @@ drm_gem_handle_delete(struct drm_file *filp, u32 handle)
        idr_remove(&filp->object_idr, handle);
        spin_unlock(&filp->table_lock);
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_handle_unreference_unlocked(obj);
-        drm_gem_object_handle_unreference(obj);
-        mutex_unlock(&dev->struct_mutex);
        return 0;
 }
@@ -338,9 +323,7 @@ again:
        }
 err:
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(obj);
-        drm_gem_object_unreference(obj);
-        mutex_unlock(&dev->struct_mutex);
        return ret;
 }
@@ -371,9 +354,7 @@ drm_gem_open_ioctl(struct drm_device *dev, void *data,
                return -ENOENT;
        ret = drm_gem_handle_create(file_priv, obj, &handle);
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(obj);
-        drm_gem_object_unreference(obj);
-        mutex_unlock(&dev->struct_mutex);
        if (ret)
                return ret;
@@ -403,7 +384,7 @@ drm_gem_object_release_handle(int id, void *ptr, void *data)
 {
        struct drm_gem_object *obj = ptr;
-        drm_gem_object_handle_unreference(obj);
+        drm_gem_object_handle_unreference_unlocked(obj);
        return 0;
 }
@@ -416,16 +397,25 @@ drm_gem_object_release_handle(int id, void *ptr, void *data)
 void
 drm_gem_release(struct drm_device *dev, struct drm_file *file_private)
 {
-        mutex_lock(&dev->struct_mutex);
        idr_for_each(&file_private->object_idr,
                     &drm_gem_object_release_handle, NULL);
        idr_destroy(&file_private->object_idr);
-        mutex_unlock(&dev->struct_mutex);
+}
+static void
+drm_gem_object_free_common(struct drm_gem_object *obj)
+{
+        struct drm_device *dev = obj->dev;
+        fput(obj->filp);
+        atomic_dec(&dev->object_count);
+        atomic_sub(obj->size, &dev->object_memory);
+        kfree(obj);
 }
 /**
 * Called after the last reference to the object has been lost.
+ * Must be called holding struct_ mutex
 *
 * Frees the object
 */
@@ -440,14 +430,40 @@ drm_gem_object_free(struct kref *kref)
        if (dev->driver->gem_free_object != NULL)
                dev->driver->gem_free_object(obj);
-        fput(obj->filp);
+        drm_gem_object_free_common(obj);
-        atomic_dec(&dev->object_count);
-        atomic_sub(obj->size, &dev->object_memory);
-        kfree(obj);
 }
 EXPORT_SYMBOL(drm_gem_object_free);
 /**
+ * Called after the last reference to the object has been lost.
+ * Must be called without holding struct_mutex
+ *
+ * Frees the object
+ */
+void
+drm_gem_object_free_unlocked(struct kref *kref)
+{
+        struct drm_gem_object *obj = (struct drm_gem_object *) kref;
+        struct drm_device *dev = obj->dev;
+        if (dev->driver->gem_free_object_unlocked != NULL)
+                dev->driver->gem_free_object_unlocked(obj);
+        else if (dev->driver->gem_free_object != NULL) {
+                mutex_lock(&dev->struct_mutex);
+                dev->driver->gem_free_object(obj);
+                mutex_unlock(&dev->struct_mutex);
+        }
+        drm_gem_object_free_common(obj);
+}
+EXPORT_SYMBOL(drm_gem_object_free_unlocked);
+static void drm_gem_object_ref_bug(struct kref *list_kref)
+{
+        BUG();
+}
+/**
 * Called after the last handle to the object has been closed
 *
 * Removes any name for the object. Note that this must be
@@ -471,8 +487,10 @@ drm_gem_object_handle_free(struct kref *kref)
                /*
                 * The object name held a reference to this object, drop
                 * that now.
+                *
+                * This cannot be the last reference, since the handle holds one too.
                 */
-                drm_gem_object_unreference(obj);
+                kref_put(&obj->refcount, drm_gem_object_ref_bug);
        } else
                spin_unlock(&dev->object_name_lock);
@@ -490,11 +508,8 @@ EXPORT_SYMBOL(drm_gem_vm_open);
 void drm_gem_vm_close(struct vm_area_struct *vma)
 {
        struct drm_gem_object *obj = vma->vm_private_data;
-        struct drm_device *dev = obj->dev;
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(obj);
-        drm_gem_object_unreference(obj);
-        mutex_unlock(&dev->struct_mutex);
 }
 EXPORT_SYMBOL(drm_gem_vm_close);
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index cdec32977129..2ac074c8f5d2 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -405,7 +405,8 @@ struct drm_mm_node *drm_mm_search_free_in_range(const struct drm_mm *mm,
                                wasted += alignment - tmp;
                }
-                if (entry->size >= size + wasted) {
+                if (entry->size >= size + wasted &&
+                    (entry->start + wasted + size) <= end) {
                        if (!best_match)
                                return entry;
                        if (entry->size < best_size) {
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 6d81a02463a3..76d63394c776 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1,9 +1,4 @@
 /*
- * The list_sort function is (presumably) licensed under the GPL (see the
- * top level "COPYING" file for details).
- *
- * The remainder of this file is:
- *
 * Copyright © 1997-2003 by The XFree86 Project, Inc.
 * Copyright © 2007 Dave Airlie
 * Copyright © 2007-2008 Intel Corporation
@@ -36,6 +31,7 @@
 */
 #include <linux/list.h>
+#include <linux/list_sort.h>
 #include "drmP.h"
 #include "drm.h"
 #include "drm_crtc.h"
@@ -855,6 +851,7 @@ EXPORT_SYMBOL(drm_mode_prune_invalid);
 /**
 * drm_mode_compare - compare modes for favorability
+ * @priv: unused
 * @lh_a: list_head for first mode
 * @lh_b: list_head for second mode
 *
@@ -868,7 +865,7 @@ EXPORT_SYMBOL(drm_mode_prune_invalid);
 * Negative if @lh_a is better than @lh_b, zero if they're equivalent, or
 * positive if @lh_b is better than @lh_a.
 */
-static int drm_mode_compare(struct list_head *lh_a, struct list_head *lh_b)
+static int drm_mode_compare(void *priv, struct list_head *lh_a, struct list_head *lh_b)
 {
        struct drm_display_mode *a = list_entry(lh_a, struct drm_display_mode, head);
        struct drm_display_mode *b = list_entry(lh_b, struct drm_display_mode, head);
@@ -885,85 +882,6 @@ static int drm_mode_compare(struct list_head *lh_a, struct list_head *lh_b)
        return diff;
 }
-/* FIXME: what we don't have a list sort function? */
-/* list sort from Mark J Roberts (mjr@znex.org) */
-void list_sort(struct list_head *head,
-               int (*cmp)(struct list_head *a, struct list_head *b))
-{
-        struct list_head *p, *q, *e, *list, *tail, *oldhead;
-        int insize, nmerges, psize, qsize, i;
-        list = head->next;
-        list_del(head);
-        insize = 1;
-        for (;;) {
-                p = oldhead = list;
-                list = tail = NULL;
-                nmerges = 0;
-                while (p) {
-                        nmerges++;
-                        q = p;
-                        psize = 0;
-                        for (i = 0; i < insize; i++) {
-                                psize++;
-                                q = q->next == oldhead ? NULL : q->next;
-                                if (!q)
-                                        break;
-                        }
-                        qsize = insize;
-                        while (psize > 0 || (qsize > 0 && q)) {
-                                if (!psize) {
-                                        e = q;
-                                        q = q->next;
-                                        qsize--;
-                                        if (q == oldhead)
-                                                q = NULL;
-                                } else if (!qsize || !q) {
-                                        e = p;
-                                        p = p->next;
-                                        psize--;
-                                        if (p == oldhead)
-                                                p = NULL;
-                                } else if (cmp(p, q) <= 0) {
-                                        e = p;
-                                        p = p->next;
-                                        psize--;
-                                        if (p == oldhead)
-                                                p = NULL;
-                                } else {
-                                        e = q;
-                                        q = q->next;
-                                        qsize--;
-                                        if (q == oldhead)
-                                                q = NULL;
-                                }
-                                if (tail)
-                                        tail->next = e;
-                                else
-                                        list = e;
-                                e->prev = tail;
-                                tail = e;
-                        }
-                        p = q;
-                }
-                tail->next = list;
-                list->prev = tail;
-                if (nmerges <= 1)
-                        break;
-                insize *= 2;
-        }
-        head->next = list;
-        head->prev = list->prev;
-        list->prev->next = head;
-        list->prev = head;
-}
 /**
 * drm_mode_sort - sort mode list
 * @mode_list: list to sort
@@ -975,7 +893,7 @@ void list_sort(struct list_head *head,
 */
 void drm_mode_sort(struct list_head *mode_list)
 {
-        list_sort(mode_list, drm_mode_compare);
+        list_sort(NULL, mode_list, drm_mode_compare);
 }
 EXPORT_SYMBOL(drm_mode_sort);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 18476bf0b580..5eed46312442 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -272,7 +272,7 @@ static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_co
                mem = kmap_atomic(pages[page], KM_USER0);
                for (i = 0; i < PAGE_SIZE; i += 4)
                        seq_printf(m, "%08x :  %08x\n", i, mem[i / 4]);
-                kunmap_atomic(pages[page], KM_USER0);
+                kunmap_atomic(mem, KM_USER0);
        }
 }
@@ -290,7 +290,7 @@ static int i915_batchbuffer_info(struct seq_file *m, void *data)
        list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
                obj = obj_priv->obj;
                if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
-                    ret = i915_gem_object_get_pages(obj);
+                    ret = i915_gem_object_get_pages(obj, 0);
                    if (ret) {
                            DRM_ERROR("Failed to get pages: %d\n", ret);
                            spin_unlock(&dev_priv->mm.active_list_lock);
@@ -350,6 +350,36 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data)
        return 0;
 }
+static const char *pin_flag(int pinned)
+{
+        if (pinned > 0)
+                return " P";
+        else if (pinned < 0)
+                return " p";
+        else
+                return "";
+}
+static const char *tiling_flag(int tiling)
+{
+        switch (tiling) {
+        default:
+        case I915_TILING_NONE: return "";
+        case I915_TILING_X: return " X";
+        case I915_TILING_Y: return " Y";
+        }
+}
+static const char *dirty_flag(int dirty)
+{
+        return dirty ? " dirty" : "";
+}
+static const char *purgeable_flag(int purgeable)
+{
+        return purgeable ? " purgeable" : "";
+}
 static int i915_error_state(struct seq_file *m, void *unused)
 {
        struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -357,6 +387,7 @@ static int i915_error_state(struct seq_file *m, void *unused)
        drm_i915_private_t *dev_priv = dev->dev_private;
        struct drm_i915_error_state *error;
        unsigned long flags;
+        int i, page, offset, elt;
        spin_lock_irqsave(&dev_priv->error_lock, flags);
        if (!dev_priv->first_error) {
@@ -368,6 +399,7 @@ static int i915_error_state(struct seq_file *m, void *unused)
        seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
                   error->time.tv_usec);
+        seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
        seq_printf(m, "EIR: 0x%08x\n", error->eir);
        seq_printf(m, "  PGTBL_ER: 0x%08x\n", error->pgtbl_er);
        seq_printf(m, "  INSTPM: 0x%08x\n", error->instpm);
@@ -379,6 +411,59 @@ static int i915_error_state(struct seq_file *m, void *unused)
                seq_printf(m, "  INSTPS: 0x%08x\n", error->instps);
                seq_printf(m, "  INSTDONE1: 0x%08x\n", error->instdone1);
        }
+        seq_printf(m, "seqno: 0x%08x\n", error->seqno);
+        if (error->active_bo_count) {
+                seq_printf(m, "Buffers [%d]:\n", error->active_bo_count);
+                for (i = 0; i < error->active_bo_count; i++) {
+                        seq_printf(m, "  %08x %8zd %08x %08x %08x%s%s%s%s",
+                                   error->active_bo[i].gtt_offset,
+                                   error->active_bo[i].size,
+                                   error->active_bo[i].read_domains,
+                                   error->active_bo[i].write_domain,
+                                   error->active_bo[i].seqno,
+                                   pin_flag(error->active_bo[i].pinned),
+                                   tiling_flag(error->active_bo[i].tiling),
+                                   dirty_flag(error->active_bo[i].dirty),
+                                   purgeable_flag(error->active_bo[i].purgeable));
+                        if (error->active_bo[i].name)
+                                seq_printf(m, " (name: %d)", error->active_bo[i].name);
+                        if (error->active_bo[i].fence_reg != I915_FENCE_REG_NONE)
+                                seq_printf(m, " (fence: %d)", error->active_bo[i].fence_reg);
+                        seq_printf(m, "\n");
+                }
+        }
+        for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {
+                if (error->batchbuffer[i]) {
+                        struct drm_i915_error_object *obj = error->batchbuffer[i];
+                        seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);
+                        offset = 0;
+                        for (page = 0; page < obj->page_count; page++) {
+                                for (elt = 0; elt < PAGE_SIZE/4; elt++) {
+                                        seq_printf(m, "%08x :  %08x\n", offset, obj->pages[page][elt]);
+                                        offset += 4;
+                                }
+                        }
+                }
+        }
+        if (error->ringbuffer) {
+                struct drm_i915_error_object *obj = error->ringbuffer;
+                seq_printf(m, "--- ringbuffer = 0x%08x\n", obj->gtt_offset);
+                offset = 0;
+                for (page = 0; page < obj->page_count; page++) {
+                        for (elt = 0; elt < PAGE_SIZE/4; elt++) {
+                                seq_printf(m, "%08x :  %08x\n", offset, obj->pages[page][elt]);
+                                offset += 4;
+                        }
+                }
+        }
 out:
        spin_unlock_irqrestore(&dev_priv->error_lock, flags);
@@ -386,30 +471,161 @@ out:
        return 0;
 }
-static int i915_registers_info(struct seq_file *m, void *data) {
+static int i915_rstdby_delays(struct seq_file *m, void *unused)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        u16 crstanddelay = I915_READ16(CRSTANDVID);
+        seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
+        return 0;
+}
+static int i915_cur_delayinfo(struct seq_file *m, void *unused)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        u16 rgvswctl = I915_READ16(MEMSWCTL);
+        seq_printf(m, "Last command: 0x%01x\n", (rgvswctl >> 13) & 0x3);
+        seq_printf(m, "Command status: %d\n", (rgvswctl >> 12) & 1);
+        seq_printf(m, "P%d DELAY 0x%02x\n", (rgvswctl >> 8) & 0xf,
+                   rgvswctl & 0x3f);
+        return 0;
+}
+static int i915_delayfreq_table(struct seq_file *m, void *unused)
+{
        struct drm_info_node *node = (struct drm_info_node *) m->private;
        struct drm_device *dev = node->minor->dev;
        drm_i915_private_t *dev_priv = dev->dev_private;
-        uint32_t reg;
+        u32 delayfreq;
+        int i;
-#define DUMP_RANGE(start, end) \
-        for (reg=start; reg < end; reg += 4) \
+        for (i = 0; i < 16; i++) {
-        seq_printf(m, "%08x\t%08x\n", reg, I915_READ(reg));
+                delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
+                seq_printf(m, "P%02dVIDFREQ: 0x%08x\n", i, delayfreq);
-        DUMP_RANGE(0x00000, 0x00fff);   /* VGA registers */
+        }
-        DUMP_RANGE(0x02000, 0x02fff);   /* instruction, memory, interrupt control registers */
-        DUMP_RANGE(0x03000, 0x031ff);   /* FENCE and PPGTT control registers */
+        return 0;
-        DUMP_RANGE(0x03200, 0x03fff);   /* frame buffer compression registers */
+}
-        DUMP_RANGE(0x05000, 0x05fff);   /* I/O control registers */
-        DUMP_RANGE(0x06000, 0x06fff);   /* clock control registers */
+static inline int MAP_TO_MV(int map)
-        DUMP_RANGE(0x07000, 0x07fff);   /* 3D internal debug registers */
+{
-        DUMP_RANGE(0x07400, 0x088ff);   /* GPE debug registers */
+        return 1250 - (map * 25);
-        DUMP_RANGE(0x0a000, 0x0afff);   /* display palette registers */
+}
-        DUMP_RANGE(0x10000, 0x13fff);   /* MMIO MCHBAR */
-        DUMP_RANGE(0x30000, 0x3ffff);   /* overlay registers */
+static int i915_inttoext_table(struct seq_file *m, void *unused)
-        DUMP_RANGE(0x60000, 0x6ffff);   /* display engine pipeline registers */
+{
-        DUMP_RANGE(0x70000, 0x72fff);   /* display and cursor registers */
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
-        DUMP_RANGE(0x73000, 0x73fff);   /* performance counters */
+        struct drm_device *dev = node->minor->dev;
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        u32 inttoext;
+        int i;
+        for (i = 1; i <= 32; i++) {
+                inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
+                seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
+        }
+        return 0;
+}
+static int i915_drpc_info(struct seq_file *m, void *unused)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        u32 rgvmodectl = I915_READ(MEMMODECTL);
+        seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
+                   "yes" : "no");
+        seq_printf(m, "Boost freq: %d\n",
+                   (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
+                   MEMMODE_BOOST_FREQ_SHIFT);
+        seq_printf(m, "HW control enabled: %s\n",
+                   rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
+        seq_printf(m, "SW control enabled: %s\n",
+                   rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
+        seq_printf(m, "Gated voltage change: %s\n",
+                   rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
+        seq_printf(m, "Starting frequency: P%d\n",
+                   (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
+        seq_printf(m, "Max frequency: P%d\n",
+                   (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
+        seq_printf(m, "Min frequency: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
+        return 0;
+}
+static int i915_fbc_status(struct seq_file *m, void *unused)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        struct drm_crtc *crtc;
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        bool fbc_enabled = false;
+        if (!dev_priv->display.fbc_enabled) {
+                seq_printf(m, "FBC unsupported on this chipset\n");
+                return 0;
+        }
+        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+                if (!crtc->enabled)
+                        continue;
+                if (dev_priv->display.fbc_enabled(crtc))
+                        fbc_enabled = true;
+        }
+        if (fbc_enabled) {
+                seq_printf(m, "FBC enabled\n");
+        } else {
+                seq_printf(m, "FBC disabled: ");
+                switch (dev_priv->no_fbc_reason) {
+                case FBC_STOLEN_TOO_SMALL:
+                        seq_printf(m, "not enough stolen memory");
+                        break;
+                case FBC_UNSUPPORTED_MODE:
+                        seq_printf(m, "mode not supported");
+                        break;
+                case FBC_MODE_TOO_LARGE:
+                        seq_printf(m, "mode too large");
+                        break;
+                case FBC_BAD_PLANE:
+                        seq_printf(m, "FBC unsupported on plane");
+                        break;
+                case FBC_NOT_TILED:
+                        seq_printf(m, "scanout buffer not tiled");
+                        break;
+                default:
+                        seq_printf(m, "unknown reason");
+                }
+                seq_printf(m, "\n");
+        }
+        return 0;
+}
+static int i915_sr_status(struct seq_file *m, void *unused)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        bool sr_enabled = false;
+        if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev))
+                sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
+        else if (IS_I915GM(dev))
+                sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
+        else if (IS_PINEVIEW(dev))
+                sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
+        seq_printf(m, "self-refresh: %s\n", sr_enabled ? "enabled" :
+                   "disabled");
        return 0;
 }
@@ -519,7 +735,6 @@ static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
 }
 static struct drm_info_list i915_debugfs_list[] = {
-        {"i915_regs", i915_registers_info, 0},
        {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
        {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
        {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
@@ -532,6 +747,13 @@ static struct drm_info_list i915_debugfs_list[] = {
        {"i915_ringbuffer_info", i915_ringbuffer_info, 0},
        {"i915_batchbuffers", i915_batchbuffer_info, 0},
        {"i915_error_state", i915_error_state, 0},
+        {"i915_rstdby_delays", i915_rstdby_delays, 0},
+        {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
+        {"i915_delayfreq_table", i915_delayfreq_table, 0},
+        {"i915_inttoext_table", i915_inttoext_table, 0},
+        {"i915_drpc_info", i915_drpc_info, 0},
+        {"i915_fbc_status", i915_fbc_status, 0},
+        {"i915_sr_status", i915_sr_status, 0},
 };
 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 02607ed61399..dbfe07c90cbc 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -35,6 +35,8 @@
 #include "i915_drv.h"
 #include "i915_trace.h"
 #include <linux/vgaarb.h>
+#include <linux/acpi.h>
+#include <linux/pnp.h>
 /* Really want an OS-independent resettable timer.  Would like to have
 * this loop run for (eg) 3 sec, but have the timer reset every time
@@ -134,6 +136,10 @@ static int i915_init_phys_hws(struct drm_device *dev)
        memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
+        if (IS_I965G(dev))
+                dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
+                                             0xf0;
        I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
        DRM_DEBUG_DRIVER("Enabled hardware status page\n");
        return 0;
@@ -731,8 +737,10 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
        if (cmdbuf->num_cliprects) {
                cliprects = kcalloc(cmdbuf->num_cliprects,
                                    sizeof(struct drm_clip_rect), GFP_KERNEL);
-                if (cliprects == NULL)
+                if (cliprects == NULL) {
+                        ret = -ENOMEM;
                        goto fail_batch_free;
+                }
                ret = copy_from_user(cliprects, cmdbuf->cliprects,
                                     cmdbuf->num_cliprects *
@@ -813,9 +821,13 @@ static int i915_getparam(struct drm_device *dev, void *data,
        case I915_PARAM_HAS_PAGEFLIPPING:
                value = 1;
                break;
+        case I915_PARAM_HAS_EXECBUF2:
+                /* depends on GEM */
+                value = dev_priv->has_gem;
+                break;
        default:
                DRM_DEBUG_DRIVER("Unknown parameter %d\n",
-                                        param->param);
+                                 param->param);
                return -EINVAL;
        }
@@ -923,6 +935,120 @@ static int i915_get_bridge_dev(struct drm_device *dev)
        return 0;
 }
+#define MCHBAR_I915 0x44
+#define MCHBAR_I965 0x48
+#define MCHBAR_SIZE (4*4096)
+#define DEVEN_REG 0x54
+#define   DEVEN_MCHBAR_EN (1 << 28)
+/* Allocate space for the MCH regs if needed, return nonzero on error */
+static int
+intel_alloc_mchbar_resource(struct drm_device *dev)
+{
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
+        u32 temp_lo, temp_hi = 0;
+        u64 mchbar_addr;
+        int ret = 0;
+        if (IS_I965G(dev))
+                pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
+        pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
+        mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
+        /* If ACPI doesn't have it, assume we need to allocate it ourselves */
+#ifdef CONFIG_PNP
+        if (mchbar_addr &&
+            pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
+                ret = 0;
+                goto out;
+        }
+#endif
+        /* Get some space for it */
+        ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
+                                     MCHBAR_SIZE, MCHBAR_SIZE,
+                                     PCIBIOS_MIN_MEM,
+                                     0,   pcibios_align_resource,
+                                     dev_priv->bridge_dev);
+        if (ret) {
+                DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
+                dev_priv->mch_res.start = 0;
+                goto out;
+        }
+        if (IS_I965G(dev))
+                pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
+                                       upper_32_bits(dev_priv->mch_res.start));
+        pci_write_config_dword(dev_priv->bridge_dev, reg,
+                               lower_32_bits(dev_priv->mch_res.start));
+out:
+        return ret;
+}
+/* Setup MCHBAR if possible, return true if we should disable it again */
+static void
+intel_setup_mchbar(struct drm_device *dev)
+{
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
+        u32 temp;
+        bool enabled;
+        dev_priv->mchbar_need_disable = false;
+        if (IS_I915G(dev) || IS_I915GM(dev)) {
+                pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
+                enabled = !!(temp & DEVEN_MCHBAR_EN);
+        } else {
+                pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
+                enabled = temp & 1;
+        }
+        /* If it's already enabled, don't have to do anything */
+        if (enabled)
+                return;
+        if (intel_alloc_mchbar_resource(dev))
+                return;
+        dev_priv->mchbar_need_disable = true;
+        /* Space is allocated or reserved, so enable it. */
+        if (IS_I915G(dev) || IS_I915GM(dev)) {
+                pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
+                                       temp | DEVEN_MCHBAR_EN);
+        } else {
+                pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
+                pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
+        }
+}
+static void
+intel_teardown_mchbar(struct drm_device *dev)
+{
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
+        u32 temp;
+        if (dev_priv->mchbar_need_disable) {
+                if (IS_I915G(dev) || IS_I915GM(dev)) {
+                        pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
+                        temp &= ~DEVEN_MCHBAR_EN;
+                        pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
+                } else {
+                        pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
+                        temp &= ~1;
+                        pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
+                }
+        }
+        if (dev_priv->mch_res.start)
+                release_resource(&dev_priv->mch_res);
+}
 /**
 * i915_probe_agp - get AGP bootup configuration
 * @pdev: PCI device
@@ -1117,11 +1243,13 @@ static void i915_setup_compression(struct drm_device *dev, int size)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_mm_node *compressed_fb, *compressed_llb;
-        unsigned long cfb_base, ll_base;
+        unsigned long cfb_base;
+        unsigned long ll_base = 0;
        /* Leave 1M for line length buffer & misc. */
        compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
        if (!compressed_fb) {
+                dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
                i915_warn_stolen(dev);
                return;
        }
@@ -1129,6 +1257,7 @@ static void i915_setup_compression(struct drm_device *dev, int size)
        compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
        if (!compressed_fb) {
                i915_warn_stolen(dev);
+                dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
                return;
        }
@@ -1200,14 +1329,6 @@ static int i915_load_modeset_init(struct drm_device *dev,
        dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
                0xff000000;
-        if (IS_MOBILE(dev) || IS_I9XX(dev))
-                dev_priv->cursor_needs_physical = true;
-        else
-                dev_priv->cursor_needs_physical = false;
-        if (IS_I965G(dev) || IS_G33(dev))
-                dev_priv->cursor_needs_physical = false;
        /* Basic memrange allocator for stolen space (aka vram) */
        drm_mm_init(&dev_priv->vram, 0, prealloc_size);
        DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
@@ -1257,6 +1378,8 @@ static int i915_load_modeset_init(struct drm_device *dev,
        if (ret)
                goto destroy_ringbuffer;
+        intel_modeset_init(dev);
        ret = drm_irq_install(dev);
        if (ret)
                goto destroy_ringbuffer;
@@ -1271,8 +1394,6 @@ static int i915_load_modeset_init(struct drm_device *dev,
        I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
-        intel_modeset_init(dev);
        drm_helper_initial_config(dev);
        return 0;
@@ -1360,7 +1481,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        resource_size_t base, size;
-        int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
+        int ret = 0, mmio_bar;
        uint32_t agp_size, prealloc_size, prealloc_start;
        /* i915 has 4 more counters */
@@ -1376,8 +1497,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
        dev->dev_private = (void *)dev_priv;
        dev_priv->dev = dev;
+        dev_priv->info = (struct intel_device_info *) flags;
        /* Add register map (needed for suspend/resume) */
+        mmio_bar = IS_I9XX(dev) ? 0 : 1;
        base = drm_get_resource_start(dev, mmio_bar);
        size = drm_get_resource_len(dev, mmio_bar);
@@ -1445,6 +1568,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
                dev->driver->get_vblank_counter = gm45_get_vblank_counter;
        }
+        /* Try to make sure MCHBAR is enabled before poking at it */
+        intel_setup_mchbar(dev);
        i915_gem_load(dev);
        /* Init HWS */
@@ -1518,6 +1644,8 @@ int i915_driver_unload(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
+        i915_destroy_error_state(dev);
        destroy_workqueue(dev_priv->wq);
        del_timer_sync(&dev_priv->hangcheck_timer);
@@ -1564,6 +1692,8 @@ int i915_driver_unload(struct drm_device *dev)
                intel_cleanup_overlay(dev);
        }
+        intel_teardown_mchbar(dev);
        pci_dev_put(dev_priv->bridge_dev);
        kfree(dev->dev_private);
@@ -1652,6 +1782,7 @@ struct drm_ioctl_desc i915_ioctls[] = {
        DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
        DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
        DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH),
        DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
        DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
        DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 24286ca168fc..742bd8f738ca 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -33,7 +33,6 @@
 #include "i915_drm.h"
 #include "i915_drv.h"
-#include "drm_pciids.h"
 #include <linux/console.h>
 #include "drm_crtc_helper.h"
@@ -46,36 +45,149 @@ module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
 unsigned int i915_powersave = 1;
 module_param_named(powersave, i915_powersave, int, 0400);
+unsigned int i915_lvds_downclock = 0;
+module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
 static struct drm_driver driver;
-static struct pci_device_id pciidlist[] = {
+#define INTEL_VGA_DEVICE(id, info) {            \
-        i915_PCI_IDS
+        .class = PCI_CLASS_DISPLAY_VGA << 8,    \
+        .class_mask = 0xffff00,                 \
+        .vendor = 0x8086,                       \
+        .device = id,                           \
+        .subvendor = PCI_ANY_ID,                \
+        .subdevice = PCI_ANY_ID,                \
+        .driver_data = (unsigned long) info }
+const static struct intel_device_info intel_i830_info = {
+        .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
+};
+const static struct intel_device_info intel_845g_info = {
+        .is_i8xx = 1,
+};
+const static struct intel_device_info intel_i85x_info = {
+        .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
+};
+const static struct intel_device_info intel_i865g_info = {
+        .is_i8xx = 1,
+};
+const static struct intel_device_info intel_i915g_info = {
+        .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
+};
+const static struct intel_device_info intel_i915gm_info = {
+        .is_i9xx = 1,  .is_mobile = 1, .has_fbc = 1,
+        .cursor_needs_physical = 1,
+};
+const static struct intel_device_info intel_i945g_info = {
+        .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
+};
+const static struct intel_device_info intel_i945gm_info = {
+        .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
+        .has_hotplug = 1, .cursor_needs_physical = 1,
+};
+const static struct intel_device_info intel_i965g_info = {
+        .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
+};
+const static struct intel_device_info intel_i965gm_info = {
+        .is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,
+        .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
+        .has_hotplug = 1,
+};
+const static struct intel_device_info intel_g33_info = {
+        .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1,
+        .has_hotplug = 1,
+};
+const static struct intel_device_info intel_g45_info = {
+        .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
+        .has_pipe_cxsr = 1,
+        .has_hotplug = 1,
+};
+const static struct intel_device_info intel_gm45_info = {
+        .is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,
+        .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
+        .has_pipe_cxsr = 1,
+        .has_hotplug = 1,
+};
+const static struct intel_device_info intel_pineview_info = {
+        .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
+        .need_gfx_hws = 1,
+        .has_hotplug = 1,
+};
+const static struct intel_device_info intel_ironlake_d_info = {
+        .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
+        .has_pipe_cxsr = 1,
+        .has_hotplug = 1,
+};
+const static struct intel_device_info intel_ironlake_m_info = {
+        .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
+        .need_gfx_hws = 1, .has_rc6 = 1,
+        .has_hotplug = 1,
+};
+const static struct pci_device_id pciidlist[] = {
+        INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
+        INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
+        INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
+        INTEL_VGA_DEVICE(0x35e8, &intel_i85x_info),
+        INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
+        INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
+        INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
+        INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
+        INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
+        INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
+        INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
+        INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
+        INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
+        INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
+        INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
+        INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
+        INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
+        INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
+        INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
+        INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
+        INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
+        INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
+        INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
+        INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
+        INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
+        INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
+        INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
+        INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
+        INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
+        INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
+        {0, 0, 0}
 };
 #if defined(CONFIG_DRM_I915_KMS)
 MODULE_DEVICE_TABLE(pci, pciidlist);
 #endif
-static int i915_suspend(struct drm_device *dev, pm_message_t state)
+static int i915_drm_freeze(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
-        if (!dev || !dev_priv) {
-                DRM_ERROR("dev: %p, dev_priv: %p\n", dev, dev_priv);
-                DRM_ERROR("DRM not initialized, aborting suspend.\n");
-                return -ENODEV;
-        }
-        if (state.event == PM_EVENT_PRETHAW)
-                return 0;
        pci_save_state(dev->pdev);
        /* If KMS is active, we do the leavevt stuff here */
        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                if (i915_gem_idle(dev))
+                int error = i915_gem_idle(dev);
+                if (error) {
                        dev_err(&dev->pdev->dev,
-                                "GEM idle failed, resume may fail\n");
+                                "GEM idle failed, resume might fail\n");
+                        return error;
+                }
                drm_irq_uninstall(dev);
        }
@@ -83,26 +195,42 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
        intel_opregion_free(dev, 1);
+        /* Modeset on resume, not lid events */
+        dev_priv->modeset_on_lid = 0;
+        return 0;
+}
+static int i915_suspend(struct drm_device *dev, pm_message_t state)
+{
+        int error;
+        if (!dev || !dev->dev_private) {
+                DRM_ERROR("dev: %p\n", dev);
+                DRM_ERROR("DRM not initialized, aborting suspend.\n");
+                return -ENODEV;
+        }
+        if (state.event == PM_EVENT_PRETHAW)
+                return 0;
+        error = i915_drm_freeze(dev);
+        if (error)
+                return error;
        if (state.event == PM_EVENT_SUSPEND) {
                /* Shut down the device */
                pci_disable_device(dev->pdev);
                pci_set_power_state(dev->pdev, PCI_D3hot);
        }
-        /* Modeset on resume, not lid events */
-        dev_priv->modeset_on_lid = 0;
        return 0;
 }
-static int i915_resume(struct drm_device *dev)
+static int i915_drm_thaw(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
-        int ret = 0;
+        int error = 0;
-        if (pci_enable_device(dev->pdev))
-                return -1;
-        pci_set_master(dev->pdev);
        i915_restore_state(dev);
@@ -113,21 +241,28 @@ static int i915_resume(struct drm_device *dev)
                mutex_lock(&dev->struct_mutex);
                dev_priv->mm.suspended = 0;
-                ret = i915_gem_init_ringbuffer(dev);
+                error = i915_gem_init_ringbuffer(dev);
-                if (ret != 0)
-                        ret = -1;
                mutex_unlock(&dev->struct_mutex);
                drm_irq_install(dev);
-        }
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
                /* Resume the modeset for every activated CRTC */
                drm_helper_resume_force_mode(dev);
        }
        dev_priv->modeset_on_lid = 0;
-        return ret;
+        return error;
+}
+static int i915_resume(struct drm_device *dev)
+{
+        if (pci_enable_device(dev->pdev))
+                return -EIO;
+        pci_set_master(dev->pdev);
+        return i915_drm_thaw(dev);
 }
 /**
@@ -268,22 +403,73 @@ i915_pci_remove(struct pci_dev *pdev)
        drm_put_dev(dev);
 }
-static int
+static int i915_pm_suspend(struct device *dev)
-i915_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 {
-        struct drm_device *dev = pci_get_drvdata(pdev);
+        struct pci_dev *pdev = to_pci_dev(dev);
+        struct drm_device *drm_dev = pci_get_drvdata(pdev);
+        int error;
+        if (!drm_dev || !drm_dev->dev_private) {
+                dev_err(dev, "DRM not initialized, aborting suspend.\n");
+                return -ENODEV;
+        }
-        return i915_suspend(dev, state);
+        error = i915_drm_freeze(drm_dev);
+        if (error)
+                return error;
+        pci_disable_device(pdev);
+        pci_set_power_state(pdev, PCI_D3hot);
+        return 0;
 }
-static int
+static int i915_pm_resume(struct device *dev)
-i915_pci_resume(struct pci_dev *pdev)
 {
-        struct drm_device *dev = pci_get_drvdata(pdev);
+        struct pci_dev *pdev = to_pci_dev(dev);
+        struct drm_device *drm_dev = pci_get_drvdata(pdev);
+        return i915_resume(drm_dev);
+}
+static int i915_pm_freeze(struct device *dev)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+        struct drm_device *drm_dev = pci_get_drvdata(pdev);
+        if (!drm_dev || !drm_dev->dev_private) {
+                dev_err(dev, "DRM not initialized, aborting suspend.\n");
+                return -ENODEV;
+        }
+        return i915_drm_freeze(drm_dev);
+}
-        return i915_resume(dev);
+static int i915_pm_thaw(struct device *dev)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+        struct drm_device *drm_dev = pci_get_drvdata(pdev);
+        return i915_drm_thaw(drm_dev);
 }
+static int i915_pm_poweroff(struct device *dev)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+        struct drm_device *drm_dev = pci_get_drvdata(pdev);
+        return i915_drm_freeze(drm_dev);
+}
+const struct dev_pm_ops i915_pm_ops = {
+     .suspend = i915_pm_suspend,
+     .resume = i915_pm_resume,
+     .freeze = i915_pm_freeze,
+     .thaw = i915_pm_thaw,
+     .poweroff = i915_pm_poweroff,
+     .restore = i915_pm_resume,
+};
 static struct vm_operations_struct i915_gem_vm_ops = {
        .fault = i915_gem_fault,
        .open = drm_gem_vm_open,
@@ -303,8 +489,11 @@ static struct drm_driver driver = {
        .lastclose = i915_driver_lastclose,
        .preclose = i915_driver_preclose,
        .postclose = i915_driver_postclose,
+        /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
        .suspend = i915_suspend,
        .resume = i915_resume,
        .device_is_agp = i915_driver_device_is_agp,
        .enable_vblank = i915_enable_vblank,
        .disable_vblank = i915_disable_vblank,
@@ -344,10 +533,7 @@ static struct drm_driver driver = {
                 .id_table = pciidlist,
                 .probe = i915_pci_probe,
                 .remove = i915_pci_remove,
-#ifdef CONFIG_PM
+                 .driver.pm = &i915_pm_ops,
-                 .resume = i915_pci_resume,
-                 .suspend = i915_pci_suspend,
-#endif
        },
        .name = DRIVER_NAME,
@@ -385,6 +571,11 @@ static int __init i915_init(void)
                driver.driver_features &= ~DRIVER_MODESET;
 #endif
+        if (!(driver.driver_features & DRIVER_MODESET)) {
+                driver.suspend = i915_suspend;
+                driver.resume = i915_resume;
+        }
        return drm_init(&driver);
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fbecac72f5bb..ec06d4865a5f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -150,7 +150,27 @@ struct drm_i915_error_state {
        u32 instps;
        u32 instdone1;
        u32 seqno;
+        u64 bbaddr;
        struct timeval time;
+        struct drm_i915_error_object {
+                int page_count;
+                u32 gtt_offset;
+                u32 *pages[0];
+        } *ringbuffer, *batchbuffer[2];
+        struct drm_i915_error_buffer {
+                size_t size;
+                u32 name;
+                u32 seqno;
+                u32 gtt_offset;
+                u32 read_domains;
+                u32 write_domain;
+                u32 fence_reg;
+                s32 pinned:2;
+                u32 tiling:2;
+                u32 dirty:1;
+                u32 purgeable:1;
+        } *active_bo;
+        u32 active_bo_count;
 };
 struct drm_i915_display_funcs {
@@ -172,9 +192,39 @@ struct drm_i915_display_funcs {
 struct intel_overlay;
+struct intel_device_info {
+        u8 is_mobile : 1;
+        u8 is_i8xx : 1;
+        u8 is_i915g : 1;
+        u8 is_i9xx : 1;
+        u8 is_i945gm : 1;
+        u8 is_i965g : 1;
+        u8 is_i965gm : 1;
+        u8 is_g33 : 1;
+        u8 need_gfx_hws : 1;
+        u8 is_g4x : 1;
+        u8 is_pineview : 1;
+        u8 is_ironlake : 1;
+        u8 has_fbc : 1;
+        u8 has_rc6 : 1;
+        u8 has_pipe_cxsr : 1;
+        u8 has_hotplug : 1;
+        u8 cursor_needs_physical : 1;
+};
+enum no_fbc_reason {
+        FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
+        FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
+        FBC_MODE_TOO_LARGE, /* mode too large for compression */
+        FBC_BAD_PLANE, /* fbc not supported on plane */
+        FBC_NOT_TILED, /* buffer not tiled */
+};
 typedef struct drm_i915_private {
        struct drm_device *dev;
+        const struct intel_device_info *info;
        int has_gem;
        void __iomem *regs;
@@ -232,8 +282,6 @@ typedef struct drm_i915_private {
        int hangcheck_count;
        uint32_t last_acthd;
-        bool cursor_needs_physical;
        struct drm_mm vram;
        unsigned long cfb_size;
@@ -263,6 +311,7 @@ typedef struct drm_i915_private {
        unsigned int lvds_use_ssc:1;
        unsigned int edp_support:1;
        int lvds_ssc_freq;
+        int edp_bpp;
        struct notifier_block lid_notifier;
@@ -287,8 +336,6 @@ typedef struct drm_i915_private {
        u32 saveDSPACNTR;
        u32 saveDSPBCNTR;
        u32 saveDSPARB;
-        u32 saveRENDERSTANDBY;
-        u32 savePWRCTXA;
        u32 saveHWS;
        u32 savePIPEACONF;
        u32 savePIPEBCONF;
@@ -433,6 +480,7 @@ typedef struct drm_i915_private {
        u32 savePIPEB_DATA_N1;
        u32 savePIPEB_LINK_M1;
        u32 savePIPEB_LINK_N1;
+        u32 saveMCHBAR_RENDER_STANDBY;
        struct {
                struct drm_mm gtt_space;
@@ -474,6 +522,15 @@ typedef struct drm_i915_private {
                struct list_head flushing_list;
                /**
+                 * List of objects currently pending a GPU write flush.
+                 *
+                 * All elements on this list will belong to either the
+                 * active_list or flushing_list, last_rendering_seqno can
+                 * be used to differentiate between the two elements.
+                 */
+                struct list_head gpu_write_list;
+                /**
                 * LRU list of objects which are not in the ringbuffer and
                 * are ready to unbind, but are still in the GTT.
                 *
@@ -561,6 +618,15 @@ typedef struct drm_i915_private {
        u16 orig_clock;
        int child_dev_num;
        struct child_device_config *child_dev;
+        struct drm_connector *int_lvds_connector;
+        bool mchbar_need_disable;
+        u8 cur_delay;
+        u8 min_delay;
+        u8 max_delay;
+        enum no_fbc_reason no_fbc_reason;
 } drm_i915_private_t;
 /** driver private structure attached to each drm_gem_object */
@@ -572,6 +638,8 @@ struct drm_i915_gem_object {
        /** This object's place on the active/flushing/inactive lists */
        struct list_head list;
+        /** This object's place on GPU write list */
+        struct list_head gpu_write_list;
        /** This object's place on the fenced object LRU */
        struct list_head fence_list;
@@ -703,6 +771,7 @@ extern struct drm_ioctl_desc i915_ioctls[];
 extern int i915_max_ioctl;
 extern unsigned int i915_fbpercrtc;
 extern unsigned int i915_powersave;
+extern unsigned int i915_lvds_downclock;
 extern void i915_save_display(struct drm_device *dev);
 extern void i915_restore_display(struct drm_device *dev);
@@ -729,6 +798,7 @@ extern int i965_reset(struct drm_device *dev, u8 flags);
 /* i915_irq.c */
 void i915_hangcheck_elapsed(unsigned long data);
+void i915_destroy_error_state(struct drm_device *dev);
 extern int i915_irq_emit(struct drm_device *dev, void *data,
                         struct drm_file *file_priv);
 extern int i915_irq_wait(struct drm_device *dev, void *data,
@@ -794,6 +864,8 @@ int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
                             struct drm_file *file_priv);
 int i915_gem_execbuffer(struct drm_device *dev, void *data,
                        struct drm_file *file_priv);
+int i915_gem_execbuffer2(struct drm_device *dev, void *data,
+                         struct drm_file *file_priv);
 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
                       struct drm_file *file_priv);
 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
@@ -843,12 +915,13 @@ int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptib
 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
                                      int write);
+int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
 int i915_gem_attach_phys_object(struct drm_device *dev,
                                struct drm_gem_object *obj, int id);
 void i915_gem_detach_phys_object(struct drm_device *dev,
                                 struct drm_gem_object *obj);
 void i915_gem_free_all_phys_object(struct drm_device *dev);
-int i915_gem_object_get_pages(struct drm_gem_object *obj);
+int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
 void i915_gem_object_put_pages(struct drm_gem_object *obj);
 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
 void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
@@ -860,6 +933,10 @@ void i915_gem_shrinker_exit(void);
 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
+bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
+                    int tiling_mode);
+bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
+                                     int tiling_mode);
 /* i915_gem_debug.c */
 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
@@ -982,67 +1059,33 @@ extern void g4x_disable_fbc(struct drm_device *dev);
 extern int i915_wrap_ring(struct drm_device * dev);
 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
-#define IS_I830(dev) ((dev)->pci_device == 0x3577)
+#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
-#define IS_845G(dev) ((dev)->pci_device == 0x2562)
-#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
+#define IS_I830(dev)            ((dev)->pci_device == 0x3577)
-#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
+#define IS_845G(dev)            ((dev)->pci_device == 0x2562)
-#define IS_I8XX(dev) (IS_I830(dev) || IS_845G(dev) || IS_I85X(dev) || IS_I865G(dev))
+#define IS_I85X(dev)            ((dev)->pci_device == 0x3582)
+#define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
-#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
+#define IS_I8XX(dev)            (INTEL_INFO(dev)->is_i8xx)
-#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
+#define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
-#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
+#define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
-#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
+#define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
-                        (dev)->pci_device == 0x27AE)
+#define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
-#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
+#define IS_I965G(dev)           (INTEL_INFO(dev)->is_i965g)
-                       (dev)->pci_device == 0x2982 || \
+#define IS_I965GM(dev)          (INTEL_INFO(dev)->is_i965gm)
-                       (dev)->pci_device == 0x2992 || \
+#define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
-                       (dev)->pci_device == 0x29A2 || \
+#define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
-                       (dev)->pci_device == 0x2A02 || \
+#define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
-                       (dev)->pci_device == 0x2A12 || \
+#define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
-                       (dev)->pci_device == 0x2A42 || \
+#define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
-                       (dev)->pci_device == 0x2E02 || \
+#define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
-                       (dev)->pci_device == 0x2E12 || \
-                       (dev)->pci_device == 0x2E22 || \
-                       (dev)->pci_device == 0x2E32 || \
-                       (dev)->pci_device == 0x2E42 || \
-                       (dev)->pci_device == 0x0042 || \
-                       (dev)->pci_device == 0x0046)
-#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
-                        (dev)->pci_device == 0x2A12)
-#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
-#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
-                     (dev)->pci_device == 0x2E12 || \
-                     (dev)->pci_device == 0x2E22 || \
-                     (dev)->pci_device == 0x2E32 || \
-                     (dev)->pci_device == 0x2E42 || \
-                     IS_GM45(dev))
-#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
-#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
-#define IS_PINEVIEW(dev) (IS_PINEVIEW_G(dev) || IS_PINEVIEW_M(dev))
-#define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||  \
-                        (dev)->pci_device == 0x29B2 ||  \
-                        (dev)->pci_device == 0x29D2 ||  \
-                        (IS_PINEVIEW(dev)))
 #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
-#define IS_IRONLAKE(dev)        (IS_IRONLAKE_D(dev) || IS_IRONLAKE_M(dev))
+#define IS_IRONLAKE(dev)        (INTEL_INFO(dev)->is_ironlake)
+#define IS_I9XX(dev)            (INTEL_INFO(dev)->is_i9xx)
-#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
+#define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
-                      IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
-                      IS_IRONLAKE(dev))
-#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
+#define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
-                        IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
-                        IS_PINEVIEW(dev) || IS_IRONLAKE_M(dev))
-#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
-                                IS_IRONLAKE(dev))
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
@@ -1054,17 +1097,14 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
 #define SUPPORTS_TV(dev)                (IS_I9XX(dev) && IS_MOBILE(dev) && \
                                        !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev))
-#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
+#define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
 /* dsparb controlled by hw only */
 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
-#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
+#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
-#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \
+#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
-                           (IS_I9XX(dev) || IS_GM45(dev)) && \
+#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
-                           !IS_PINEVIEW(dev) && \
-                           !IS_IRONLAKE(dev))
-#define I915_HAS_RC6(dev) (IS_I965GM(dev) || IS_GM45(dev) || IS_IRONLAKE_M(dev))
 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c7f0cbec4e84..b5df30ca0fa2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -128,9 +128,7 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
                return -ENOMEM;
        ret = drm_gem_handle_create(file_priv, obj, &handle);
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_handle_unreference_unlocked(obj);
-        drm_gem_object_handle_unreference(obj);
-        mutex_unlock(&dev->struct_mutex);
        if (ret)
                return ret;
@@ -277,7 +275,7 @@ i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
        mutex_lock(&dev->struct_mutex);
-        ret = i915_gem_object_get_pages(obj);
+        ret = i915_gem_object_get_pages(obj, 0);
        if (ret != 0)
                goto fail_unlock;
@@ -321,40 +319,24 @@ fail_unlock:
        return ret;
 }
-static inline gfp_t
-i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
-{
-        return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
-}
-static inline void
-i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
-{
-        mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
-}
 static int
 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
 {
        int ret;
-        ret = i915_gem_object_get_pages(obj);
+        ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
        /* If we've insufficient memory to map in the pages, attempt
         * to make some space by throwing out some old buffers.
         */
        if (ret == -ENOMEM) {
                struct drm_device *dev = obj->dev;
-                gfp_t gfp;
                ret = i915_gem_evict_something(dev, obj->size);
                if (ret)
                        return ret;
-                gfp = i915_gem_object_get_page_gfp_mask(obj);
+                ret = i915_gem_object_get_pages(obj, 0);
-                i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
-                ret = i915_gem_object_get_pages(obj);
-                i915_gem_object_set_page_gfp_mask (obj, gfp);
        }
        return ret;
@@ -504,7 +486,7 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
         */
        if (args->offset > obj->size || args->size > obj->size ||
            args->offset + args->size > obj->size) {
-                drm_gem_object_unreference(obj);
+                drm_gem_object_unreference_unlocked(obj);
                return -EINVAL;
        }
@@ -517,7 +499,7 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
                                                        file_priv);
        }
-        drm_gem_object_unreference(obj);
+        drm_gem_object_unreference_unlocked(obj);
        return ret;
 }
@@ -790,7 +772,7 @@ i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
        mutex_lock(&dev->struct_mutex);
-        ret = i915_gem_object_get_pages(obj);
+        ret = i915_gem_object_get_pages(obj, 0);
        if (ret != 0)
                goto fail_unlock;
@@ -977,7 +959,7 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
         */
        if (args->offset > obj->size || args->size > obj->size ||
            args->offset + args->size > obj->size) {
-                drm_gem_object_unreference(obj);
+                drm_gem_object_unreference_unlocked(obj);
                return -EINVAL;
        }
@@ -1011,7 +993,7 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
                DRM_INFO("pwrite failed %d\n", ret);
 #endif
-        drm_gem_object_unreference(obj);
+        drm_gem_object_unreference_unlocked(obj);
        return ret;
 }
@@ -1154,9 +1136,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
                       PROT_READ | PROT_WRITE, MAP_SHARED,
                       args->offset);
        up_write(&current->mm->mmap_sem);
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(obj);
-        drm_gem_object_unreference(obj);
-        mutex_unlock(&dev->struct_mutex);
        if (IS_ERR((void *)addr))
                return addr;
@@ -1310,7 +1290,7 @@ out_free_list:
 * i915_gem_release_mmap - remove physical page mappings
 * @obj: obj in question
 *
- * Preserve the reservation of the mmaping with the DRM core code, but
+ * Preserve the reservation of the mmapping with the DRM core code, but
 * relinquish ownership of the pages back to the system.
 *
 * It is vital that we remove the page mapping if we have mapped a tiled
@@ -1568,6 +1548,8 @@ i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
        else
                list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
+        BUG_ON(!list_empty(&obj_priv->gpu_write_list));
        obj_priv->last_rendering_seqno = 0;
        if (obj_priv->active) {
                obj_priv->active = 0;
@@ -1638,7 +1620,8 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
                struct drm_i915_gem_object *obj_priv, *next;
                list_for_each_entry_safe(obj_priv, next,
-                                         &dev_priv->mm.flushing_list, list) {
+                                         &dev_priv->mm.gpu_write_list,
+                                         gpu_write_list) {
                        struct drm_gem_object *obj = obj_priv->obj;
                        if ((obj->write_domain & flush_domains) ==
@@ -1646,6 +1629,7 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
                                uint32_t old_write_domain = obj->write_domain;
                                obj->write_domain = 0;
+                                list_del_init(&obj_priv->gpu_write_list);
                                i915_gem_object_move_to_active(obj, seqno);
                                trace_i915_gem_object_change_domain(obj,
@@ -2021,9 +2005,6 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
        /* blow away mappings if mapped through GTT */
        i915_gem_release_mmap(obj);
-        if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
-                i915_gem_clear_fence_reg(obj);
        /* Move the object to the CPU domain to ensure that
         * any possible CPU writes while it's not in the GTT
         * are flushed when we go to remap it. This will
@@ -2039,6 +2020,10 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
        BUG_ON(obj_priv->active);
+        /* release the fence reg _after_ flushing */
+        if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
+                i915_gem_clear_fence_reg(obj);
        if (obj_priv->agp_mem != NULL) {
                drm_unbind_agp(obj_priv->agp_mem);
                drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
@@ -2099,8 +2084,8 @@ static int
 i915_gem_evict_everything(struct drm_device *dev)
 {
        drm_i915_private_t *dev_priv = dev->dev_private;
-        uint32_t seqno;
        int ret;
+        uint32_t seqno;
        bool lists_empty;
        spin_lock(&dev_priv->mm.active_list_lock);
@@ -2122,6 +2107,8 @@ i915_gem_evict_everything(struct drm_device *dev)
        if (ret)
                return ret;
+        BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
        ret = i915_gem_evict_from_inactive_list(dev);
        if (ret)
                return ret;
@@ -2229,7 +2216,8 @@ i915_gem_evict_something(struct drm_device *dev, int min_size)
 }
 int
-i915_gem_object_get_pages(struct drm_gem_object *obj)
+i915_gem_object_get_pages(struct drm_gem_object *obj,
+                          gfp_t gfpmask)
 {
        struct drm_i915_gem_object *obj_priv = obj->driver_private;
        int page_count, i;
@@ -2255,7 +2243,10 @@ i915_gem_object_get_pages(struct drm_gem_object *obj)
        inode = obj->filp->f_path.dentry->d_inode;
        mapping = inode->i_mapping;
        for (i = 0; i < page_count; i++) {
-                page = read_mapping_page(mapping, i, NULL);
+                page = read_cache_page_gfp(mapping, i,
+                                           mapping_gfp_mask (mapping) |
+                                           __GFP_COLD |
+                                           gfpmask);
                if (IS_ERR(page)) {
                        ret = PTR_ERR(page);
                        i915_gem_object_put_pages(obj);
@@ -2549,6 +2540,12 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
        if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
                return 0;
+        /* If we've changed tiling, GTT-mappings of the object
+         * need to re-fault to ensure that the correct fence register
+         * setup is in place.
+         */
+        i915_gem_release_mmap(obj);
        /* On the i915, GPU access to tiled buffers is via a fence,
         * therefore we must wait for any outstanding access to complete
         * before clearing the fence.
@@ -2557,12 +2554,12 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
                int ret;
                i915_gem_object_flush_gpu_write_domain(obj);
-                i915_gem_object_flush_gtt_write_domain(obj);
                ret = i915_gem_object_wait_rendering(obj);
                if (ret != 0)
                        return ret;
        }
+        i915_gem_object_flush_gtt_write_domain(obj);
        i915_gem_clear_fence_reg (obj);
        return 0;
@@ -2578,12 +2575,9 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
        drm_i915_private_t *dev_priv = dev->dev_private;
        struct drm_i915_gem_object *obj_priv = obj->driver_private;
        struct drm_mm_node *free_space;
-        bool retry_alloc = false;
+        gfp_t gfpmask =  __GFP_NORETRY | __GFP_NOWARN;
        int ret;
-        if (dev_priv->mm.suspended)
-                return -EBUSY;
        if (obj_priv->madv != I915_MADV_WILLNEED) {
                DRM_ERROR("Attempting to bind a purgeable object\n");
                return -EINVAL;
@@ -2625,15 +2619,7 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
        DRM_INFO("Binding object of size %zd at 0x%08x\n",
                 obj->size, obj_priv->gtt_offset);
 #endif
-        if (retry_alloc) {
+        ret = i915_gem_object_get_pages(obj, gfpmask);
-                i915_gem_object_set_page_gfp_mask (obj,
-                                                   i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
-        }
-        ret = i915_gem_object_get_pages(obj);
-        if (retry_alloc) {
-                i915_gem_object_set_page_gfp_mask (obj,
-                                                   i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
-        }
        if (ret) {
                drm_mm_put_block(obj_priv->gtt_space);
                obj_priv->gtt_space = NULL;
@@ -2643,9 +2629,9 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
                        ret = i915_gem_evict_something(dev, obj->size);
                        if (ret) {
                                /* now try to shrink everyone else */
-                                if (! retry_alloc) {
+                                if (gfpmask) {
-                                    retry_alloc = true;
+                                        gfpmask = 0;
-                                    goto search_free;
+                                        goto search_free;
                                }
                                return ret;
@@ -2723,7 +2709,7 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
        old_write_domain = obj->write_domain;
        i915_gem_flush(dev, 0, obj->write_domain);
        seqno = i915_add_request(dev, NULL, obj->write_domain);
-        obj->write_domain = 0;
+        BUG_ON(obj->write_domain);
        i915_gem_object_move_to_active(obj, seqno);
        trace_i915_gem_object_change_domain(obj,
@@ -2839,6 +2825,57 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
        return 0;
 }
+/*
+ * Prepare buffer for display plane. Use uninterruptible for possible flush
+ * wait, as in modesetting process we're not supposed to be interrupted.
+ */
+int
+i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
+{
+        struct drm_device *dev = obj->dev;
+        struct drm_i915_gem_object *obj_priv = obj->driver_private;
+        uint32_t old_write_domain, old_read_domains;
+        int ret;
+        /* Not valid to be called on unbound objects. */
+        if (obj_priv->gtt_space == NULL)
+                return -EINVAL;
+        i915_gem_object_flush_gpu_write_domain(obj);
+        /* Wait on any GPU rendering and flushing to occur. */
+        if (obj_priv->active) {
+#if WATCH_BUF
+                DRM_INFO("%s: object %p wait for seqno %08x\n",
+                          __func__, obj, obj_priv->last_rendering_seqno);
+#endif
+                ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
+                if (ret != 0)
+                        return ret;
+        }
+        old_write_domain = obj->write_domain;
+        old_read_domains = obj->read_domains;
+        obj->read_domains &= I915_GEM_DOMAIN_GTT;
+        i915_gem_object_flush_cpu_write_domain(obj);
+        /* It should now be out of any other write domains, and we can update
+         * the domain values for our changes.
+         */
+        BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
+        obj->read_domains |= I915_GEM_DOMAIN_GTT;
+        obj->write_domain = I915_GEM_DOMAIN_GTT;
+        obj_priv->dirty = 1;
+        trace_i915_gem_object_change_domain(obj,
+                                            old_read_domains,
+                                            old_write_domain);
+        return 0;
+}
 /**
 * Moves a single object to the CPU read, and possibly write domain.
 *
@@ -3198,7 +3235,7 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
 static int
 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
                                 struct drm_file *file_priv,
-                                 struct drm_i915_gem_exec_object *entry,
+                                 struct drm_i915_gem_exec_object2 *entry,
                                 struct drm_i915_gem_relocation_entry *relocs)
 {
        struct drm_device *dev = obj->dev;
@@ -3206,12 +3243,36 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
        struct drm_i915_gem_object *obj_priv = obj->driver_private;
        int i, ret;
        void __iomem *reloc_page;
+        bool need_fence;
+        need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
+                     obj_priv->tiling_mode != I915_TILING_NONE;
+        /* Check fence reg constraints and rebind if necessary */
+        if (need_fence && !i915_gem_object_fence_offset_ok(obj,
+            obj_priv->tiling_mode))
+                i915_gem_object_unbind(obj);
        /* Choose the GTT offset for our buffer and put it there. */
        ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
        if (ret)
                return ret;
+        /*
+         * Pre-965 chips need a fence register set up in order to
+         * properly handle blits to/from tiled surfaces.
+         */
+        if (need_fence) {
+                ret = i915_gem_object_get_fence_reg(obj);
+                if (ret != 0) {
+                        if (ret != -EBUSY && ret != -ERESTARTSYS)
+                                DRM_ERROR("Failure to install fence: %d\n",
+                                          ret);
+                        i915_gem_object_unpin(obj);
+                        return ret;
+                }
+        }
        entry->offset = obj_priv->gtt_offset;
        /* Apply the relocations, using the GTT aperture to avoid cache
@@ -3373,7 +3434,7 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
 */
 static int
 i915_dispatch_gem_execbuffer(struct drm_device *dev,
-                              struct drm_i915_gem_execbuffer *exec,
+                              struct drm_i915_gem_execbuffer2 *exec,
                              struct drm_clip_rect *cliprects,
                              uint64_t exec_offset)
 {
@@ -3463,7 +3524,7 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
 }
 static int
-i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
+i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
                              uint32_t buffer_count,
                              struct drm_i915_gem_relocation_entry **relocs)
 {
@@ -3478,8 +3539,10 @@ i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
        }
        *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
-        if (*relocs == NULL)
+        if (*relocs == NULL) {
+                DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
                return -ENOMEM;
+        }
        for (i = 0; i < buffer_count; i++) {
                struct drm_i915_gem_relocation_entry __user *user_relocs;
@@ -3503,13 +3566,16 @@ i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
 }
 static int
-i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
+i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
                            uint32_t buffer_count,
                            struct drm_i915_gem_relocation_entry *relocs)
 {
        uint32_t reloc_count = 0, i;
        int ret = 0;
+        if (relocs == NULL)
+            return 0;
        for (i = 0; i < buffer_count; i++) {
                struct drm_i915_gem_relocation_entry __user *user_relocs;
                int unwritten;
@@ -3536,7 +3602,7 @@ err:
 }
 static int
-i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
+i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
                           uint64_t exec_offset)
 {
        uint32_t exec_start, exec_len;
@@ -3589,18 +3655,18 @@ i915_gem_wait_for_pending_flip(struct drm_device *dev,
 }
 int
-i915_gem_execbuffer(struct drm_device *dev, void *data,
+i915_gem_do_execbuffer(struct drm_device *dev, void *data,
-                    struct drm_file *file_priv)
+                       struct drm_file *file_priv,
+                       struct drm_i915_gem_execbuffer2 *args,
+                       struct drm_i915_gem_exec_object2 *exec_list)
 {
        drm_i915_private_t *dev_priv = dev->dev_private;
-        struct drm_i915_gem_execbuffer *args = data;
-        struct drm_i915_gem_exec_object *exec_list = NULL;
        struct drm_gem_object **object_list = NULL;
        struct drm_gem_object *batch_obj;
        struct drm_i915_gem_object *obj_priv;
        struct drm_clip_rect *cliprects = NULL;
-        struct drm_i915_gem_relocation_entry *relocs;
+        struct drm_i915_gem_relocation_entry *relocs = NULL;
-        int ret, ret2, i, pinned = 0;
+        int ret = 0, ret2, i, pinned = 0;
        uint64_t exec_offset;
        uint32_t seqno, flush_domains, reloc_index;
        int pin_tries, flips;
@@ -3614,31 +3680,21 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
                DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
                return -EINVAL;
        }
-        /* Copy in the exec list from userland */
-        exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
        object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
-        if (exec_list == NULL || object_list == NULL) {
+        if (object_list == NULL) {
-                DRM_ERROR("Failed to allocate exec or object list "
+                DRM_ERROR("Failed to allocate object list for %d buffers\n",
-                          "for %d buffers\n",
                          args->buffer_count);
                ret = -ENOMEM;
                goto pre_mutex_err;
        }
-        ret = copy_from_user(exec_list,
-                             (struct drm_i915_relocation_entry __user *)
-                             (uintptr_t) args->buffers_ptr,
-                             sizeof(*exec_list) * args->buffer_count);
-        if (ret != 0) {
-                DRM_ERROR("copy %d exec entries failed %d\n",
-                          args->buffer_count, ret);
-                goto pre_mutex_err;
-        }
        if (args->num_cliprects != 0) {
                cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
                                    GFP_KERNEL);
-                if (cliprects == NULL)
+                if (cliprects == NULL) {
+                        ret = -ENOMEM;
                        goto pre_mutex_err;
+                }
                ret = copy_from_user(cliprects,
                                     (struct drm_clip_rect __user *)
@@ -3680,6 +3736,8 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
                if (object_list[i] == NULL) {
                        DRM_ERROR("Invalid object handle %d at index %d\n",
                                   exec_list[i].handle, i);
+                        /* prevent error path from reading uninitialized data */
+                        args->buffer_count = i + 1;
                        ret = -EBADF;
                        goto err;
                }
@@ -3688,6 +3746,8 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
                if (obj_priv->in_execbuffer) {
                        DRM_ERROR("Object %p appears more than once in object list\n",
                                   object_list[i]);
+                        /* prevent error path from reading uninitialized data */
+                        args->buffer_count = i + 1;
                        ret = -EBADF;
                        goto err;
                }
@@ -3801,16 +3861,23 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
                i915_gem_flush(dev,
                               dev->invalidate_domains,
                               dev->flush_domains);
-                if (dev->flush_domains)
+                if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
                        (void)i915_add_request(dev, file_priv,
                                               dev->flush_domains);
        }
        for (i = 0; i < args->buffer_count; i++) {
                struct drm_gem_object *obj = object_list[i];
+                struct drm_i915_gem_object *obj_priv = obj->driver_private;
                uint32_t old_write_domain = obj->write_domain;
                obj->write_domain = obj->pending_write_domain;
+                if (obj->write_domain)
+                        list_move_tail(&obj_priv->gpu_write_list,
+                                       &dev_priv->mm.gpu_write_list);
+                else
+                        list_del_init(&obj_priv->gpu_write_list);
                trace_i915_gem_object_change_domain(obj,
                                                    obj->read_domains,
                                                    old_write_domain);
@@ -3884,8 +3951,101 @@ err:
        mutex_unlock(&dev->struct_mutex);
+pre_mutex_err:
+        /* Copy the updated relocations out regardless of current error
+         * state.  Failure to update the relocs would mean that the next
+         * time userland calls execbuf, it would do so with presumed offset
+         * state that didn't match the actual object state.
+         */
+        ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
+                                           relocs);
+        if (ret2 != 0) {
+                DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
+                if (ret == 0)
+                        ret = ret2;
+        }
+        drm_free_large(object_list);
+        kfree(cliprects);
+        return ret;
+}
+/*
+ * Legacy execbuffer just creates an exec2 list from the original exec object
+ * list array and passes it to the real function.
+ */
+int
+i915_gem_execbuffer(struct drm_device *dev, void *data,
+                    struct drm_file *file_priv)
+{
+        struct drm_i915_gem_execbuffer *args = data;
+        struct drm_i915_gem_execbuffer2 exec2;
+        struct drm_i915_gem_exec_object *exec_list = NULL;
+        struct drm_i915_gem_exec_object2 *exec2_list = NULL;
+        int ret, i;
+#if WATCH_EXEC
+        DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
+                  (int) args->buffers_ptr, args->buffer_count, args->batch_len);
+#endif
+        if (args->buffer_count < 1) {
+                DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
+                return -EINVAL;
+        }
+        /* Copy in the exec list from userland */
+        exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
+        exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
+        if (exec_list == NULL || exec2_list == NULL) {
+                DRM_ERROR("Failed to allocate exec list for %d buffers\n",
+                          args->buffer_count);
+                drm_free_large(exec_list);
+                drm_free_large(exec2_list);
+                return -ENOMEM;
+        }
+        ret = copy_from_user(exec_list,
+                             (struct drm_i915_relocation_entry __user *)
+                             (uintptr_t) args->buffers_ptr,
+                             sizeof(*exec_list) * args->buffer_count);
+        if (ret != 0) {
+                DRM_ERROR("copy %d exec entries failed %d\n",
+                          args->buffer_count, ret);
+                drm_free_large(exec_list);
+                drm_free_large(exec2_list);
+                return -EFAULT;
+        }
+        for (i = 0; i < args->buffer_count; i++) {
+                exec2_list[i].handle = exec_list[i].handle;
+                exec2_list[i].relocation_count = exec_list[i].relocation_count;
+                exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
+                exec2_list[i].alignment = exec_list[i].alignment;
+                exec2_list[i].offset = exec_list[i].offset;
+                if (!IS_I965G(dev))
+                        exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
+                else
+                        exec2_list[i].flags = 0;
+        }
+        exec2.buffers_ptr = args->buffers_ptr;
+        exec2.buffer_count = args->buffer_count;
+        exec2.batch_start_offset = args->batch_start_offset;
+        exec2.batch_len = args->batch_len;
+        exec2.DR1 = args->DR1;
+        exec2.DR4 = args->DR4;
+        exec2.num_cliprects = args->num_cliprects;
+        exec2.cliprects_ptr = args->cliprects_ptr;
+        exec2.flags = 0;
+        ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
        if (!ret) {
                /* Copy the new buffer offsets back to the user's exec list. */
+                for (i = 0; i < args->buffer_count; i++)
+                        exec_list[i].offset = exec2_list[i].offset;
+                /* ... and back out to userspace */
                ret = copy_to_user((struct drm_i915_relocation_entry __user *)
                                   (uintptr_t) args->buffers_ptr,
                                   exec_list,
@@ -3898,25 +4058,62 @@ err:
                }
        }
-        /* Copy the updated relocations out regardless of current error
+        drm_free_large(exec_list);
-         * state.  Failure to update the relocs would mean that the next
+        drm_free_large(exec2_list);
-         * time userland calls execbuf, it would do so with presumed offset
+        return ret;
-         * state that didn't match the actual object state.
+}
-         */
-        ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
-                                           relocs);
-        if (ret2 != 0) {
-                DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
-                if (ret == 0)
+int
-                        ret = ret2;
+i915_gem_execbuffer2(struct drm_device *dev, void *data,
+                     struct drm_file *file_priv)
+{
+        struct drm_i915_gem_execbuffer2 *args = data;
+        struct drm_i915_gem_exec_object2 *exec2_list = NULL;
+        int ret;
+#if WATCH_EXEC
+        DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
+                  (int) args->buffers_ptr, args->buffer_count, args->batch_len);
+#endif
+        if (args->buffer_count < 1) {
+                DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
+                return -EINVAL;
        }
-pre_mutex_err:
+        exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
-        drm_free_large(object_list);
+        if (exec2_list == NULL) {
-        drm_free_large(exec_list);
+                DRM_ERROR("Failed to allocate exec list for %d buffers\n",
-        kfree(cliprects);
+                          args->buffer_count);
+                return -ENOMEM;
+        }
+        ret = copy_from_user(exec2_list,
+                             (struct drm_i915_relocation_entry __user *)
+                             (uintptr_t) args->buffers_ptr,
+                             sizeof(*exec2_list) * args->buffer_count);
+        if (ret != 0) {
+                DRM_ERROR("copy %d exec entries failed %d\n",
+                          args->buffer_count, ret);
+                drm_free_large(exec2_list);
+                return -EFAULT;
+        }
+        ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
+        if (!ret) {
+                /* Copy the new buffer offsets back to the user's exec list. */
+                ret = copy_to_user((struct drm_i915_relocation_entry __user *)
+                                   (uintptr_t) args->buffers_ptr,
+                                   exec2_list,
+                                   sizeof(*exec2_list) * args->buffer_count);
+                if (ret) {
+                        ret = -EFAULT;
+                        DRM_ERROR("failed to copy %d exec entries "
+                                  "back to user (%d)\n",
+                                  args->buffer_count, ret);
+                }
+        }
+        drm_free_large(exec2_list);
        return ret;
 }
@@ -3933,19 +4130,7 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
                if (ret)
                        return ret;
        }
-        /*
-         * Pre-965 chips need a fence register set up in order to
-         * properly handle tiled surfaces.
-         */
-        if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
-                ret = i915_gem_object_get_fence_reg(obj);
-                if (ret != 0) {
-                        if (ret != -EBUSY && ret != -ERESTARTSYS)
-                                DRM_ERROR("Failure to install fence: %d\n",
-                                          ret);
-                        return ret;
-                }
-        }
        obj_priv->pin_count++;
        /* If the object is not active and not pending a flush,
@@ -4203,6 +4388,7 @@ int i915_gem_init_object(struct drm_gem_object *obj)
        obj_priv->obj = obj;
        obj_priv->fence_reg = I915_FENCE_REG_NONE;
        INIT_LIST_HEAD(&obj_priv->list);
+        INIT_LIST_HEAD(&obj_priv->gpu_write_list);
        INIT_LIST_HEAD(&obj_priv->fence_list);
        obj_priv->madv = I915_MADV_WILLNEED;
@@ -4258,129 +4444,73 @@ i915_gem_evict_from_inactive_list(struct drm_device *dev)
        return 0;
 }
-int
+static int
-i915_gem_idle(struct drm_device *dev)
+i915_gpu_idle(struct drm_device *dev)
 {
        drm_i915_private_t *dev_priv = dev->dev_private;
-        uint32_t seqno, cur_seqno, last_seqno;
+        bool lists_empty;
-        int stuck, ret;
+        uint32_t seqno;
-        mutex_lock(&dev->struct_mutex);
+        spin_lock(&dev_priv->mm.active_list_lock);
+        lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
+                      list_empty(&dev_priv->mm.active_list);
+        spin_unlock(&dev_priv->mm.active_list_lock);
-        if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
+        if (lists_empty)
-                mutex_unlock(&dev->struct_mutex);
                return 0;
-        }
-        /* Hack!  Don't let anybody do execbuf while we don't control the chip.
+        /* Flush everything onto the inactive list. */
-         * We need to replace this with a semaphore, or something.
-         */
-        dev_priv->mm.suspended = 1;
-        del_timer(&dev_priv->hangcheck_timer);
-        /* Cancel the retire work handler, wait for it to finish if running
-         */
-        mutex_unlock(&dev->struct_mutex);
-        cancel_delayed_work_sync(&dev_priv->mm.retire_work);
-        mutex_lock(&dev->struct_mutex);
-        i915_kernel_lost_context(dev);
-        /* Flush the GPU along with all non-CPU write domains
-         */
        i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
        seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
+        if (seqno == 0)
-        if (seqno == 0) {
-                mutex_unlock(&dev->struct_mutex);
                return -ENOMEM;
-        }
-        dev_priv->mm.waiting_gem_seqno = seqno;
-        last_seqno = 0;
-        stuck = 0;
-        for (;;) {
-                cur_seqno = i915_get_gem_seqno(dev);
-                if (i915_seqno_passed(cur_seqno, seqno))
-                        break;
-                if (last_seqno == cur_seqno) {
-                        if (stuck++ > 100) {
-                                DRM_ERROR("hardware wedged\n");
-                                atomic_set(&dev_priv->mm.wedged, 1);
-                                DRM_WAKEUP(&dev_priv->irq_queue);
-                                break;
-                        }
-                }
-                msleep(10);
-                last_seqno = cur_seqno;
-        }
-        dev_priv->mm.waiting_gem_seqno = 0;
-        i915_gem_retire_requests(dev);
-        spin_lock(&dev_priv->mm.active_list_lock);
-        if (!atomic_read(&dev_priv->mm.wedged)) {
-                /* Active and flushing should now be empty as we've
-                 * waited for a sequence higher than any pending execbuffer
-                 */
-                WARN_ON(!list_empty(&dev_priv->mm.active_list));
-                WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
-                /* Request should now be empty as we've also waited
-                 * for the last request in the list
-                 */
-                WARN_ON(!list_empty(&dev_priv->mm.request_list));
-        }
-        /* Empty the active and flushing lists to inactive.  If there's
-         * anything left at this point, it means that we're wedged and
-         * nothing good's going to happen by leaving them there.  So strip
-         * the GPU domains and just stuff them onto inactive.
-         */
-        while (!list_empty(&dev_priv->mm.active_list)) {
-                struct drm_gem_object *obj;
-                uint32_t old_write_domain;
-                obj = list_first_entry(&dev_priv->mm.active_list,
-                                       struct drm_i915_gem_object,
-                                       list)->obj;
-                old_write_domain = obj->write_domain;
-                obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
-                i915_gem_object_move_to_inactive(obj);
-                trace_i915_gem_object_change_domain(obj,
+        return i915_wait_request(dev, seqno);
-                                                    obj->read_domains,
+}
-                                                    old_write_domain);
-        }
-        spin_unlock(&dev_priv->mm.active_list_lock);
-        while (!list_empty(&dev_priv->mm.flushing_list)) {
+int
-                struct drm_gem_object *obj;
+i915_gem_idle(struct drm_device *dev)
-                uint32_t old_write_domain;
+{
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        int ret;
-                obj = list_first_entry(&dev_priv->mm.flushing_list,
+        mutex_lock(&dev->struct_mutex);
-                                       struct drm_i915_gem_object,
-                                       list)->obj;
-                old_write_domain = obj->write_domain;
-                obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
-                i915_gem_object_move_to_inactive(obj);
-                trace_i915_gem_object_change_domain(obj,
+        if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
-                                                    obj->read_domains,
+                mutex_unlock(&dev->struct_mutex);
-                                                    old_write_domain);
+                return 0;
        }
+        ret = i915_gpu_idle(dev);
-        /* Move all inactive buffers out of the GTT. */
-        ret = i915_gem_evict_from_inactive_list(dev);
-        WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
        if (ret) {
                mutex_unlock(&dev->struct_mutex);
                return ret;
        }
+        /* Under UMS, be paranoid and evict. */
+        if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
+                ret = i915_gem_evict_from_inactive_list(dev);
+                if (ret) {
+                        mutex_unlock(&dev->struct_mutex);
+                        return ret;
+                }
+        }
+        /* Hack!  Don't let anybody do execbuf while we don't control the chip.
+         * We need to replace this with a semaphore, or something.
+         * And not confound mm.suspended!
+         */
+        dev_priv->mm.suspended = 1;
+        del_timer(&dev_priv->hangcheck_timer);
+        i915_kernel_lost_context(dev);
        i915_gem_cleanup_ringbuffer(dev);
        mutex_unlock(&dev->struct_mutex);
+        /* Cancel the retire work handler, which should be idle now. */
+        cancel_delayed_work_sync(&dev_priv->mm.retire_work);
        return 0;
 }
@@ -4654,6 +4784,7 @@ i915_gem_load(struct drm_device *dev)
        spin_lock_init(&dev_priv->mm.active_list_lock);
        INIT_LIST_HEAD(&dev_priv->mm.active_list);
        INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
+        INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
        INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
        INIT_LIST_HEAD(&dev_priv->mm.request_list);
        INIT_LIST_HEAD(&dev_priv->mm.fence_list);
@@ -4666,7 +4797,8 @@ i915_gem_load(struct drm_device *dev)
        spin_unlock(&shrink_list_lock);
        /* Old X drivers will take 0-2 for front, back, depth buffers */
-        dev_priv->fence_reg_start = 3;
+        if (!drm_core_check_feature(dev, DRIVER_MODESET))
+                dev_priv->fence_reg_start = 3;
        if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
                dev_priv->num_fence_regs = 16;
@@ -4766,7 +4898,7 @@ void i915_gem_detach_phys_object(struct drm_device *dev,
        if (!obj_priv->phys_obj)
                return;
-        ret = i915_gem_object_get_pages(obj);
+        ret = i915_gem_object_get_pages(obj, 0);
        if (ret)
                goto out;
@@ -4824,7 +4956,7 @@ i915_gem_attach_phys_object(struct drm_device *dev,
        obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
        obj_priv->phys_obj->cur_obj = obj;
-        ret = i915_gem_object_get_pages(obj);
+        ret = i915_gem_object_get_pages(obj, 0);
        if (ret) {
                DRM_ERROR("failed to get page list\n");
                goto out;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 30d6af6c09bb..20653776965a 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -25,8 +25,6 @@
 *
 */
-#include <linux/acpi.h>
-#include <linux/pnp.h>
 #include "linux/string.h"
 #include "linux/bitops.h"
 #include "drmP.h"
@@ -83,120 +81,6 @@
 * to match what the GPU expects.
 */
-#define MCHBAR_I915 0x44
-#define MCHBAR_I965 0x48
-#define MCHBAR_SIZE (4*4096)
-#define DEVEN_REG 0x54
-#define   DEVEN_MCHBAR_EN (1 << 28)
-/* Allocate space for the MCH regs if needed, return nonzero on error */
-static int
-intel_alloc_mchbar_resource(struct drm_device *dev)
-{
-        drm_i915_private_t *dev_priv = dev->dev_private;
-        int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
-        u32 temp_lo, temp_hi = 0;
-        u64 mchbar_addr;
-        int ret = 0;
-        if (IS_I965G(dev))
-                pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
-        pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
-        mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
-        /* If ACPI doesn't have it, assume we need to allocate it ourselves */
-#ifdef CONFIG_PNP
-        if (mchbar_addr &&
-            pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
-                ret = 0;
-                goto out;
-        }
-#endif
-        /* Get some space for it */
-        ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
-                                     MCHBAR_SIZE, MCHBAR_SIZE,
-                                     PCIBIOS_MIN_MEM,
-                                     0,   pcibios_align_resource,
-                                     dev_priv->bridge_dev);
-        if (ret) {
-                DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
-                dev_priv->mch_res.start = 0;
-                goto out;
-        }
-        if (IS_I965G(dev))
-                pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
-                                       upper_32_bits(dev_priv->mch_res.start));
-        pci_write_config_dword(dev_priv->bridge_dev, reg,
-                               lower_32_bits(dev_priv->mch_res.start));
-out:
-        return ret;
-}
-/* Setup MCHBAR if possible, return true if we should disable it again */
-static bool
-intel_setup_mchbar(struct drm_device *dev)
-{
-        drm_i915_private_t *dev_priv = dev->dev_private;
-        int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
-        u32 temp;
-        bool need_disable = false, enabled;
-        if (IS_I915G(dev) || IS_I915GM(dev)) {
-                pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
-                enabled = !!(temp & DEVEN_MCHBAR_EN);
-        } else {
-                pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
-                enabled = temp & 1;
-        }
-        /* If it's already enabled, don't have to do anything */
-        if (enabled)
-                goto out;
-        if (intel_alloc_mchbar_resource(dev))
-                goto out;
-        need_disable = true;
-        /* Space is allocated or reserved, so enable it. */
-        if (IS_I915G(dev) || IS_I915GM(dev)) {
-                pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
-                                       temp | DEVEN_MCHBAR_EN);
-        } else {
-                pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
-                pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
-        }
-out:
-        return need_disable;
-}
-static void
-intel_teardown_mchbar(struct drm_device *dev, bool disable)
-{
-        drm_i915_private_t *dev_priv = dev->dev_private;
-        int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
-        u32 temp;
-        if (disable) {
-                if (IS_I915G(dev) || IS_I915GM(dev)) {
-                        pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
-                        temp &= ~DEVEN_MCHBAR_EN;
-                        pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
-                } else {
-                        pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
-                        temp &= ~1;
-                        pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
-                }
-        }
-        if (dev_priv->mch_res.start)
-                release_resource(&dev_priv->mch_res);
-}
 /**
 * Detects bit 6 swizzling of address lookup between IGD access and CPU
 * access through main memory.
@@ -207,7 +91,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
        drm_i915_private_t *dev_priv = dev->dev_private;
        uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
        uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
-        bool need_disable;
        if (IS_IRONLAKE(dev)) {
                /* On Ironlake whatever DRAM config, GPU always do
@@ -224,9 +107,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
        } else if (IS_MOBILE(dev)) {
                uint32_t dcc;
-                /* Try to make sure MCHBAR is enabled before poking at it */
-                need_disable = intel_setup_mchbar(dev);
                /* On mobile 9xx chipsets, channel interleave by the CPU is
                 * determined by DCC.  For single-channel, neither the CPU
                 * nor the GPU do swizzling.  For dual channel interleaved,
@@ -266,8 +146,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
                        swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
                        swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
                }
-                intel_teardown_mchbar(dev, need_disable);
        } else {
                /* The 965, G33, and newer, have a very flexible memory
                 * configuration.  It will enable dual-channel mode
@@ -302,37 +180,8 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
        dev_priv->mm.bit_6_swizzle_y = swizzle_y;
 }
-/**
- * Returns the size of the fence for a tiled object of the given size.
- */
-static int
-i915_get_fence_size(struct drm_device *dev, int size)
-{
-        int i;
-        int start;
-        if (IS_I965G(dev)) {
-                /* The 965 can have fences at any page boundary. */
-                return ALIGN(size, 4096);
-        } else {
-                /* Align the size to a power of two greater than the smallest
-                 * fence size.
-                 */
-                if (IS_I9XX(dev))
-                        start = 1024 * 1024;
-                else
-                        start = 512 * 1024;
-                for (i = start; i < size; i <<= 1)
-                        ;
-                return i;
-        }
-}
 /* Check pitch constriants for all chips & tiling formats */
-static bool
+bool
 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
 {
        int tile_width;
@@ -384,16 +233,10 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
        if (stride & (stride - 1))
                return false;
-        /* We don't 0handle the aperture area covered by the fence being bigger
-         * than the object size.
-         */
-        if (i915_get_fence_size(dev, size) != size)
-                return false;
        return true;
 }
-static bool
+bool
 i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, int tiling_mode)
 {
        struct drm_device *dev = obj->dev;
@@ -440,9 +283,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
        obj_priv = obj->driver_private;
        if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) {
-                mutex_lock(&dev->struct_mutex);
+                drm_gem_object_unreference_unlocked(obj);
-                drm_gem_object_unreference(obj);
-                mutex_unlock(&dev->struct_mutex);
                return -EINVAL;
        }
@@ -495,12 +336,6 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
                        goto err;
                }
-                /* If we've changed tiling, GTT-mappings of the object
-                 * need to re-fault to ensure that the correct fence register
-                 * setup is in place.
-                 */
-                i915_gem_release_mmap(obj);
                obj_priv->tiling_mode = args->tiling_mode;
                obj_priv->stride = args->stride;
        }
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 85f4c5de97e2..ba1d8314c1ce 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -269,12 +269,62 @@ static void i915_hotplug_work_func(struct work_struct *work)
        drm_sysfs_hotplug_event(dev);
 }
+static void i915_handle_rps_change(struct drm_device *dev)
+{
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        u32 busy_up, busy_down, max_avg, min_avg;
+        u16 rgvswctl;
+        u8 new_delay = dev_priv->cur_delay;
+        I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG);
+        busy_up = I915_READ(RCPREVBSYTUPAVG);
+        busy_down = I915_READ(RCPREVBSYTDNAVG);
+        max_avg = I915_READ(RCBMAXAVG);
+        min_avg = I915_READ(RCBMINAVG);
+        /* Handle RCS change request from hw */
+        if (busy_up > max_avg) {
+                if (dev_priv->cur_delay != dev_priv->max_delay)
+                        new_delay = dev_priv->cur_delay - 1;
+                if (new_delay < dev_priv->max_delay)
+                        new_delay = dev_priv->max_delay;
+        } else if (busy_down < min_avg) {
+                if (dev_priv->cur_delay != dev_priv->min_delay)
+                        new_delay = dev_priv->cur_delay + 1;
+                if (new_delay > dev_priv->min_delay)
+                        new_delay = dev_priv->min_delay;
+        }
+        DRM_DEBUG("rps change requested: %d -> %d\n",
+                  dev_priv->cur_delay, new_delay);
+        rgvswctl = I915_READ(MEMSWCTL);
+        if (rgvswctl & MEMCTL_CMD_STS) {
+                DRM_ERROR("gpu busy, RCS change rejected\n");
+                return; /* still busy with another command */
+        }
+        /* Program the new state */
+        rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
+                (new_delay << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
+        I915_WRITE(MEMSWCTL, rgvswctl);
+        POSTING_READ(MEMSWCTL);
+        rgvswctl |= MEMCTL_CMD_STS;
+        I915_WRITE(MEMSWCTL, rgvswctl);
+        dev_priv->cur_delay = new_delay;
+        DRM_DEBUG("rps changed\n");
+        return;
+}
 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 {
        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
        int ret = IRQ_NONE;
        u32 de_iir, gt_iir, de_ier, pch_iir;
-        u32 new_de_iir, new_gt_iir, new_pch_iir;
        struct drm_i915_master_private *master_priv;
        /* disable master interrupt before clearing iir  */
@@ -286,49 +336,63 @@ irqreturn_t ironlake_irq_handler(struct drm_device *dev)
        gt_iir = I915_READ(GTIIR);
        pch_iir = I915_READ(SDEIIR);
-        for (;;) {
+        if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
-                if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
+                goto done;
-                        break;
-                ret = IRQ_HANDLED;
+        ret = IRQ_HANDLED;
-                /* should clear PCH hotplug event before clear CPU irq */
+        if (dev->primary->master) {
-                I915_WRITE(SDEIIR, pch_iir);
+                master_priv = dev->primary->master->driver_priv;
-                new_pch_iir = I915_READ(SDEIIR);
+                if (master_priv->sarea_priv)
+                        master_priv->sarea_priv->last_dispatch =
+                                READ_BREADCRUMB(dev_priv);
+        }
-                I915_WRITE(DEIIR, de_iir);
+        if (gt_iir & GT_USER_INTERRUPT) {
-                new_de_iir = I915_READ(DEIIR);
+                u32 seqno = i915_get_gem_seqno(dev);
-                I915_WRITE(GTIIR, gt_iir);
+                dev_priv->mm.irq_gem_seqno = seqno;
-                new_gt_iir = I915_READ(GTIIR);
+                trace_i915_gem_request_complete(dev, seqno);
+                DRM_WAKEUP(&dev_priv->irq_queue);
+                dev_priv->hangcheck_count = 0;
+                mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
+        }
-                if (dev->primary->master) {
+        if (de_iir & DE_GSE)
-                        master_priv = dev->primary->master->driver_priv;
+                ironlake_opregion_gse_intr(dev);
-                        if (master_priv->sarea_priv)
-                                master_priv->sarea_priv->last_dispatch =
-                                        READ_BREADCRUMB(dev_priv);
-                }
-                if (gt_iir & GT_USER_INTERRUPT) {
+        if (de_iir & DE_PLANEA_FLIP_DONE) {
-                        u32 seqno = i915_get_gem_seqno(dev);
+                intel_prepare_page_flip(dev, 0);
-                        dev_priv->mm.irq_gem_seqno = seqno;
+                intel_finish_page_flip(dev, 0);
-                        trace_i915_gem_request_complete(dev, seqno);
+        }
-                        DRM_WAKEUP(&dev_priv->irq_queue);
-                }
-                if (de_iir & DE_GSE)
+        if (de_iir & DE_PLANEB_FLIP_DONE) {
-                        ironlake_opregion_gse_intr(dev);
+                intel_prepare_page_flip(dev, 1);
+                intel_finish_page_flip(dev, 1);
+        }
-                /* check event from PCH */
+        if (de_iir & DE_PIPEA_VBLANK)
-                if ((de_iir & DE_PCH_EVENT) &&
+                drm_handle_vblank(dev, 0);
-                        (pch_iir & SDE_HOTPLUG_MASK)) {
-                        queue_work(dev_priv->wq, &dev_priv->hotplug_work);
+        if (de_iir & DE_PIPEB_VBLANK)
-                }
+                drm_handle_vblank(dev, 1);
-                de_iir = new_de_iir;
+        /* check event from PCH */
-                gt_iir = new_gt_iir;
+        if ((de_iir & DE_PCH_EVENT) &&
-                pch_iir = new_pch_iir;
+            (pch_iir & SDE_HOTPLUG_MASK)) {
+                queue_work(dev_priv->wq, &dev_priv->hotplug_work);
        }
+        if (de_iir & DE_PCU_EVENT) {
+                I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS));
+                i915_handle_rps_change(dev);
+        }
+        /* should clear PCH hotplug event before clear CPU irq */
+        I915_WRITE(SDEIIR, pch_iir);
+        I915_WRITE(GTIIR, gt_iir);
+        I915_WRITE(DEIIR, de_iir);
+done:
        I915_WRITE(DEIER, de_ier);
        (void)I915_READ(DEIER);
@@ -368,6 +432,121 @@ static void i915_error_work_func(struct work_struct *work)
        }
 }
+static struct drm_i915_error_object *
+i915_error_object_create(struct drm_device *dev,
+                         struct drm_gem_object *src)
+{
+        struct drm_i915_error_object *dst;
+        struct drm_i915_gem_object *src_priv;
+        int page, page_count;
+        if (src == NULL)
+                return NULL;
+        src_priv = src->driver_private;
+        if (src_priv->pages == NULL)
+                return NULL;
+        page_count = src->size / PAGE_SIZE;
+        dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
+        if (dst == NULL)
+                return NULL;
+        for (page = 0; page < page_count; page++) {
+                void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
+                if (d == NULL)
+                        goto unwind;
+                s = kmap_atomic(src_priv->pages[page], KM_USER0);
+                memcpy(d, s, PAGE_SIZE);
+                kunmap_atomic(s, KM_USER0);
+                dst->pages[page] = d;
+        }
+        dst->page_count = page_count;
+        dst->gtt_offset = src_priv->gtt_offset;
+        return dst;
+unwind:
+        while (page--)
+                kfree(dst->pages[page]);
+        kfree(dst);
+        return NULL;
+}
+static void
+i915_error_object_free(struct drm_i915_error_object *obj)
+{
+        int page;
+        if (obj == NULL)
+                return;
+        for (page = 0; page < obj->page_count; page++)
+                kfree(obj->pages[page]);
+        kfree(obj);
+}
+static void
+i915_error_state_free(struct drm_device *dev,
+                      struct drm_i915_error_state *error)
+{
+        i915_error_object_free(error->batchbuffer[0]);
+        i915_error_object_free(error->batchbuffer[1]);
+        i915_error_object_free(error->ringbuffer);
+        kfree(error->active_bo);
+        kfree(error);
+}
+static u32
+i915_get_bbaddr(struct drm_device *dev, u32 *ring)
+{
+        u32 cmd;
+        if (IS_I830(dev) || IS_845G(dev))
+                cmd = MI_BATCH_BUFFER;
+        else if (IS_I965G(dev))
+                cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
+                       MI_BATCH_NON_SECURE_I965);
+        else
+                cmd = (MI_BATCH_BUFFER_START | (2 << 6));
+        return ring[0] == cmd ? ring[1] : 0;
+}
+static u32
+i915_ringbuffer_last_batch(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 head, bbaddr;
+        u32 *ring;
+        /* Locate the current position in the ringbuffer and walk back
+         * to find the most recently dispatched batch buffer.
+         */
+        bbaddr = 0;
+        head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
+        ring = (u32 *)(dev_priv->ring.virtual_start + head);
+        while (--ring >= (u32 *)dev_priv->ring.virtual_start) {
+                bbaddr = i915_get_bbaddr(dev, ring);
+                if (bbaddr)
+                        break;
+        }
+        if (bbaddr == 0) {
+                ring = (u32 *)(dev_priv->ring.virtual_start + dev_priv->ring.Size);
+                while (--ring >= (u32 *)dev_priv->ring.virtual_start) {
+                        bbaddr = i915_get_bbaddr(dev, ring);
+                        if (bbaddr)
+                                break;
+                }
+        }
+        return bbaddr;
+}
 /**
 * i915_capture_error_state - capture an error record for later analysis
 * @dev: drm device
@@ -380,19 +559,26 @@ static void i915_error_work_func(struct work_struct *work)
 static void i915_capture_error_state(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct drm_i915_gem_object *obj_priv;
        struct drm_i915_error_state *error;
+        struct drm_gem_object *batchbuffer[2];
        unsigned long flags;
+        u32 bbaddr;
+        int count;
        spin_lock_irqsave(&dev_priv->error_lock, flags);
-        if (dev_priv->first_error)
+        error = dev_priv->first_error;
-                goto out;
+        spin_unlock_irqrestore(&dev_priv->error_lock, flags);
+        if (error)
+                return;
        error = kmalloc(sizeof(*error), GFP_ATOMIC);
        if (!error) {
-                DRM_DEBUG_DRIVER("out ot memory, not capturing error state\n");
+                DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
-                goto out;
+                return;
        }
+        error->seqno = i915_get_gem_seqno(dev);
        error->eir = I915_READ(EIR);
        error->pgtbl_er = I915_READ(PGTBL_ER);
        error->pipeastat = I915_READ(PIPEASTAT);
@@ -403,6 +589,7 @@ static void i915_capture_error_state(struct drm_device *dev)
                error->ipehr = I915_READ(IPEHR);
                error->instdone = I915_READ(INSTDONE);
                error->acthd = I915_READ(ACTHD);
+                error->bbaddr = 0;
        } else {
                error->ipeir = I915_READ(IPEIR_I965);
                error->ipehr = I915_READ(IPEHR_I965);
@@ -410,14 +597,101 @@ static void i915_capture_error_state(struct drm_device *dev)
                error->instps = I915_READ(INSTPS);
                error->instdone1 = I915_READ(INSTDONE1);
                error->acthd = I915_READ(ACTHD_I965);
+                error->bbaddr = I915_READ64(BB_ADDR);
        }
-        do_gettimeofday(&error->time);
+        bbaddr = i915_ringbuffer_last_batch(dev);
+        /* Grab the current batchbuffer, most likely to have crashed. */
+        batchbuffer[0] = NULL;
+        batchbuffer[1] = NULL;
+        count = 0;
+        list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
+                struct drm_gem_object *obj = obj_priv->obj;
+                if (batchbuffer[0] == NULL &&
+                    bbaddr >= obj_priv->gtt_offset &&
+                    bbaddr < obj_priv->gtt_offset + obj->size)
+                        batchbuffer[0] = obj;
+                if (batchbuffer[1] == NULL &&
+                    error->acthd >= obj_priv->gtt_offset &&
+                    error->acthd < obj_priv->gtt_offset + obj->size &&
+                    batchbuffer[0] != obj)
+                        batchbuffer[1] = obj;
+                count++;
+        }
+        /* We need to copy these to an anonymous buffer as the simplest
+         * method to avoid being overwritten by userpace.
+         */
+        error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
+        error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
+        /* Record the ringbuffer */
+        error->ringbuffer = i915_error_object_create(dev, dev_priv->ring.ring_obj);
+        /* Record buffers on the active list. */
+        error->active_bo = NULL;
+        error->active_bo_count = 0;
+        if (count)
+                error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
+                                           GFP_ATOMIC);
+        if (error->active_bo) {
+                int i = 0;
+                list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
+                        struct drm_gem_object *obj = obj_priv->obj;
+                        error->active_bo[i].size = obj->size;
+                        error->active_bo[i].name = obj->name;
+                        error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
+                        error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
+                        error->active_bo[i].read_domains = obj->read_domains;
+                        error->active_bo[i].write_domain = obj->write_domain;
+                        error->active_bo[i].fence_reg = obj_priv->fence_reg;
+                        error->active_bo[i].pinned = 0;
+                        if (obj_priv->pin_count > 0)
+                                error->active_bo[i].pinned = 1;
+                        if (obj_priv->user_pin_count > 0)
+                                error->active_bo[i].pinned = -1;
+                        error->active_bo[i].tiling = obj_priv->tiling_mode;
+                        error->active_bo[i].dirty = obj_priv->dirty;
+                        error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
+                        if (++i == count)
+                                break;
+                }
+                error->active_bo_count = i;
+        }
-        dev_priv->first_error = error;
+        do_gettimeofday(&error->time);
-out:
+        spin_lock_irqsave(&dev_priv->error_lock, flags);
+        if (dev_priv->first_error == NULL) {
+                dev_priv->first_error = error;
+                error = NULL;
+        }
        spin_unlock_irqrestore(&dev_priv->error_lock, flags);
+        if (error)
+                i915_error_state_free(dev, error);
+}
+void i915_destroy_error_state(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct drm_i915_error_state *error;
+        spin_lock(&dev_priv->error_lock);
+        error = dev_priv->first_error;
+        dev_priv->first_error = NULL;
+        spin_unlock(&dev_priv->error_lock);
+        if (error)
+                i915_error_state_free(dev, error);
 }
 /**
@@ -852,11 +1126,11 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
        if (!(pipeconf & PIPEACONF_ENABLE))
                return -EINVAL;
-        if (IS_IRONLAKE(dev))
-                return 0;
        spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
-        if (IS_I965G(dev))
+        if (IS_IRONLAKE(dev))
+                ironlake_enable_display_irq(dev_priv, (pipe == 0) ? 
+                                            DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
+        else if (IS_I965G(dev))
                i915_enable_pipestat(dev_priv, pipe,
                                     PIPE_START_VBLANK_INTERRUPT_ENABLE);
        else
@@ -874,13 +1148,14 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
        unsigned long irqflags;
-        if (IS_IRONLAKE(dev))
-                return;
        spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
-        i915_disable_pipestat(dev_priv, pipe,
+        if (IS_IRONLAKE(dev))
-                              PIPE_VBLANK_INTERRUPT_ENABLE |
+                ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 
-                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
+                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
+        else
+                i915_disable_pipestat(dev_priv, pipe,
+                                      PIPE_VBLANK_INTERRUPT_ENABLE |
+                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
        spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 }
@@ -1023,13 +1298,14 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
 {
        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
        /* enable kind of interrupts always enabled */
-        u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT;
+        u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
+                           DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
        u32 render_mask = GT_USER_INTERRUPT;
        u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
                           SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
        dev_priv->irq_mask_reg = ~display_mask;
-        dev_priv->de_irq_enable_reg = display_mask;
+        dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
        /* should always can generate irq */
        I915_WRITE(DEIIR, I915_READ(DEIIR));
@@ -1054,6 +1330,13 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
        I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
        (void) I915_READ(SDEIER);
+        if (IS_IRONLAKE_M(dev)) {
+                /* Clear & enable PCU event interrupts */
+                I915_WRITE(DEIIR, DE_PCU_EVENT);
+                I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
+                ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
+        }
        return 0;
 }
@@ -1084,6 +1367,10 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
        (void) I915_READ(IER);
 }
+/*
+ * Must be called after intel_modeset_init or hotplug interrupts won't be
+ * enabled correctly.
+ */
 int i915_driver_irq_postinstall(struct drm_device *dev)
 {
        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -1106,19 +1393,23 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
        if (I915_HAS_HOTPLUG(dev)) {
                u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
-                /* Leave other bits alone */
+                /* Note HDMI and DP share bits */
-                hotplug_en |= HOTPLUG_EN_MASK;
+                if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
+                        hotplug_en |= HDMIB_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
+                        hotplug_en |= HDMIC_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
+                        hotplug_en |= HDMID_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
+                        hotplug_en |= SDVOC_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
+                        hotplug_en |= SDVOB_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
+                        hotplug_en |= CRT_HOTPLUG_INT_EN;
+                /* Ignore TV since it's buggy */
                I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
-                dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS |
-                        TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS |
-                        SDVOB_HOTPLUG_INT_STATUS;
-                if (IS_G4X(dev)) {
-                        dev_priv->hotplug_supported_mask |=
-                                HDMIB_HOTPLUG_INT_STATUS |
-                                HDMIC_HOTPLUG_INT_STATUS |
-                                HDMID_HOTPLUG_INT_STATUS;
-                }
                /* Enable in IER... */
                enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
                /* and unmask in IMR */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 974b3cf70618..eff8d850a758 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -61,6 +61,7 @@
 #define   GC_CLOCK_100_200              (1 << 0)
 #define   GC_CLOCK_100_133              (2 << 0)
 #define   GC_CLOCK_166_250              (3 << 0)
+#define GCFGC2  0xda
 #define GCFGC   0xf0 /* 915+ only */
 #define   GC_LOW_FREQUENCY_ENABLE       (1 << 7)
 #define   GC_DISPLAY_CLOCK_190_200_MHZ  (0 << 4)
@@ -282,7 +283,7 @@
 #define   I915_PIPE_CONTROL_NOTIFY_INTERRUPT            (1<<18)
 #define   I915_DISPLAY_PORT_INTERRUPT                   (1<<17)
 #define   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT    (1<<15)
-#define   I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT      (1<<14)
+#define   I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT      (1<<14) /* p-state */
 #define   I915_HWB_OOM_INTERRUPT                        (1<<13)
 #define   I915_SYNC_STATUS_INTERRUPT                    (1<<12)
 #define   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT   (1<<11)
@@ -306,11 +307,14 @@
 #define   I915_ERROR_MEMORY_REFRESH                     (1<<1)
 #define   I915_ERROR_INSTRUCTION                        (1<<0)
 #define INSTPM          0x020c0
+#define   INSTPM_SELF_EN (1<<12) /* 915GM only */
 #define ACTHD           0x020c8
 #define FW_BLC          0x020d8
 #define FW_BLC2         0x020dc
 #define FW_BLC_SELF     0x020e0 /* 915+ only */
-#define   FW_BLC_SELF_EN (1<<15)
+#define   FW_BLC_SELF_EN_MASK      (1<<31)
+#define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
+#define   FW_BLC_SELF_EN           (1<<15) /* 945 only */
 #define MM_BURST_LENGTH     0x00700000
 #define MM_FIFO_WATERMARK   0x0001F000
 #define LM_BURST_LENGTH     0x00000700
@@ -324,6 +328,7 @@
 #define   CM0_COLOR_EVICT_DISABLE (1<<3)
 #define   CM0_DEPTH_WRITE_DISABLE (1<<1)
 #define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
+#define BB_ADDR         0x02140 /* 8 bytes */
 #define GFX_FLSH_CNTL   0x02170 /* 915+ only */
@@ -338,6 +343,7 @@
 #define   FBC_CTL_PERIODIC      (1<<30)
 #define   FBC_CTL_INTERVAL_SHIFT (16)
 #define   FBC_CTL_UNCOMPRESSIBLE (1<<14)
+#define   FBC_C3_IDLE           (1<<13)
 #define   FBC_CTL_STRIDE_SHIFT  (5)
 #define   FBC_CTL_FENCENO       (1<<0)
 #define FBC_COMMAND             0x0320c
@@ -783,10 +789,144 @@
 #define CLKCFG_MEM_800                                  (3 << 4)
 #define CLKCFG_MEM_MASK                                 (7 << 4)
-/** GM965 GM45 render standby register */
+#define CRSTANDVID              0x11100
-#define MCHBAR_RENDER_STANDBY   0x111B8
+#define PXVFREQ_BASE            0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
+#define   PXVFREQ_PX_MASK       0x7f000000
+#define   PXVFREQ_PX_SHIFT      24
+#define VIDFREQ_BASE            0x11110
+#define VIDFREQ1                0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
+#define VIDFREQ2                0x11114
+#define VIDFREQ3                0x11118
+#define VIDFREQ4                0x1111c
+#define   VIDFREQ_P0_MASK       0x1f000000
+#define   VIDFREQ_P0_SHIFT      24
+#define   VIDFREQ_P0_CSCLK_MASK 0x00f00000
+#define   VIDFREQ_P0_CSCLK_SHIFT 20
+#define   VIDFREQ_P0_CRCLK_MASK 0x000f0000
+#define   VIDFREQ_P0_CRCLK_SHIFT 16
+#define   VIDFREQ_P1_MASK       0x00001f00
+#define   VIDFREQ_P1_SHIFT      8
+#define   VIDFREQ_P1_CSCLK_MASK 0x000000f0
+#define   VIDFREQ_P1_CSCLK_SHIFT 4
+#define   VIDFREQ_P1_CRCLK_MASK 0x0000000f
+#define INTTOEXT_BASE_ILK       0x11300
+#define INTTOEXT_BASE           0x11120 /* INTTOEXT1-8 (0x1113c) */
+#define   INTTOEXT_MAP3_SHIFT   24
+#define   INTTOEXT_MAP3_MASK    (0x1f << INTTOEXT_MAP3_SHIFT)
+#define   INTTOEXT_MAP2_SHIFT   16
+#define   INTTOEXT_MAP2_MASK    (0x1f << INTTOEXT_MAP2_SHIFT)
+#define   INTTOEXT_MAP1_SHIFT   8
+#define   INTTOEXT_MAP1_MASK    (0x1f << INTTOEXT_MAP1_SHIFT)
+#define   INTTOEXT_MAP0_SHIFT   0
+#define   INTTOEXT_MAP0_MASK    (0x1f << INTTOEXT_MAP0_SHIFT)
+#define MEMSWCTL                0x11170 /* Ironlake only */
+#define   MEMCTL_CMD_MASK       0xe000
+#define   MEMCTL_CMD_SHIFT      13
+#define   MEMCTL_CMD_RCLK_OFF   0
+#define   MEMCTL_CMD_RCLK_ON    1
+#define   MEMCTL_CMD_CHFREQ     2
+#define   MEMCTL_CMD_CHVID      3
+#define   MEMCTL_CMD_VMMOFF     4
+#define   MEMCTL_CMD_VMMON      5
+#define   MEMCTL_CMD_STS        (1<<12) /* write 1 triggers command, clears
+                                           when command complete */
+#define   MEMCTL_FREQ_MASK      0x0f00 /* jitter, from 0-15 */
+#define   MEMCTL_FREQ_SHIFT     8
+#define   MEMCTL_SFCAVM         (1<<7)
+#define   MEMCTL_TGT_VID_MASK   0x007f
+#define MEMIHYST                0x1117c
+#define MEMINTREN               0x11180 /* 16 bits */
+#define   MEMINT_RSEXIT_EN      (1<<8)
+#define   MEMINT_CX_SUPR_EN     (1<<7)
+#define   MEMINT_CONT_BUSY_EN   (1<<6)
+#define   MEMINT_AVG_BUSY_EN    (1<<5)
+#define   MEMINT_EVAL_CHG_EN    (1<<4)
+#define   MEMINT_MON_IDLE_EN    (1<<3)
+#define   MEMINT_UP_EVAL_EN     (1<<2)
+#define   MEMINT_DOWN_EVAL_EN   (1<<1)
+#define   MEMINT_SW_CMD_EN      (1<<0)
+#define MEMINTRSTR              0x11182 /* 16 bits */
+#define   MEM_RSEXIT_MASK       0xc000
+#define   MEM_RSEXIT_SHIFT      14
+#define   MEM_CONT_BUSY_MASK    0x3000
+#define   MEM_CONT_BUSY_SHIFT   12
+#define   MEM_AVG_BUSY_MASK     0x0c00
+#define   MEM_AVG_BUSY_SHIFT    10
+#define   MEM_EVAL_CHG_MASK     0x0300
+#define   MEM_EVAL_BUSY_SHIFT   8
+#define   MEM_MON_IDLE_MASK     0x00c0
+#define   MEM_MON_IDLE_SHIFT    6
+#define   MEM_UP_EVAL_MASK      0x0030
+#define   MEM_UP_EVAL_SHIFT     4
+#define   MEM_DOWN_EVAL_MASK    0x000c
+#define   MEM_DOWN_EVAL_SHIFT   2
+#define   MEM_SW_CMD_MASK       0x0003
+#define   MEM_INT_STEER_GFX     0
+#define   MEM_INT_STEER_CMR     1
+#define   MEM_INT_STEER_SMI     2
+#define   MEM_INT_STEER_SCI     3
+#define MEMINTRSTS              0x11184
+#define   MEMINT_RSEXIT         (1<<7)
+#define   MEMINT_CONT_BUSY      (1<<6)
+#define   MEMINT_AVG_BUSY       (1<<5)
+#define   MEMINT_EVAL_CHG       (1<<4)
+#define   MEMINT_MON_IDLE       (1<<3)
+#define   MEMINT_UP_EVAL        (1<<2)
+#define   MEMINT_DOWN_EVAL      (1<<1)
+#define   MEMINT_SW_CMD         (1<<0)
+#define MEMMODECTL              0x11190
+#define   MEMMODE_BOOST_EN      (1<<31)
+#define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
+#define   MEMMODE_BOOST_FREQ_SHIFT 24
+#define   MEMMODE_IDLE_MODE_MASK 0x00030000
+#define   MEMMODE_IDLE_MODE_SHIFT 16
+#define   MEMMODE_IDLE_MODE_EVAL 0
+#define   MEMMODE_IDLE_MODE_CONT 1
+#define   MEMMODE_HWIDLE_EN     (1<<15)
+#define   MEMMODE_SWMODE_EN     (1<<14)
+#define   MEMMODE_RCLK_GATE     (1<<13)
+#define   MEMMODE_HW_UPDATE     (1<<12)
+#define   MEMMODE_FSTART_MASK   0x00000f00 /* starting jitter, 0-15 */
+#define   MEMMODE_FSTART_SHIFT  8
+#define   MEMMODE_FMAX_MASK     0x000000f0 /* max jitter, 0-15 */
+#define   MEMMODE_FMAX_SHIFT    4
+#define   MEMMODE_FMIN_MASK     0x0000000f /* min jitter, 0-15 */
+#define RCBMAXAVG               0x1119c
+#define MEMSWCTL2               0x1119e /* Cantiga only */
+#define   SWMEMCMD_RENDER_OFF   (0 << 13)
+#define   SWMEMCMD_RENDER_ON    (1 << 13)
+#define   SWMEMCMD_SWFREQ       (2 << 13)
+#define   SWMEMCMD_TARVID       (3 << 13)
+#define   SWMEMCMD_VRM_OFF      (4 << 13)
+#define   SWMEMCMD_VRM_ON       (5 << 13)
+#define   CMDSTS                (1<<12)
+#define   SFCAVM                (1<<11)
+#define   SWFREQ_MASK           0x0380 /* P0-7 */
+#define   SWFREQ_SHIFT          7
+#define   TARVID_MASK           0x001f
+#define MEMSTAT_CTG             0x111a0
+#define RCBMINAVG               0x111a0
+#define RCUPEI                  0x111b0
+#define RCDNEI                  0x111b4
+#define MCHBAR_RENDER_STANDBY           0x111b8
 #define   RCX_SW_EXIT           (1<<23)
 #define   RSX_STATUS_MASK       0x00700000
+#define VIDCTL                  0x111c0
+#define VIDSTS                  0x111c8
+#define VIDSTART                0x111cc /* 8 bits */
+#define MEMSTAT_ILK                     0x111f8
+#define   MEMSTAT_VID_MASK      0x7f00
+#define   MEMSTAT_VID_SHIFT     8
+#define   MEMSTAT_PSTATE_MASK   0x00f8
+#define   MEMSTAT_PSTATE_SHIFT  3
+#define   MEMSTAT_MON_ACTV      (1<<2)
+#define   MEMSTAT_SRC_CTL_MASK  0x0003
+#define   MEMSTAT_SRC_CTL_CORE  0
+#define   MEMSTAT_SRC_CTL_TRB   1
+#define   MEMSTAT_SRC_CTL_THM   2
+#define   MEMSTAT_SRC_CTL_STDBY 3
+#define RCPREVBSYTUPAVG         0x113b8
+#define RCPREVBSYTDNAVG         0x113bc
 #define PEG_BAND_GAP_DATA       0x14d68
 /*
@@ -879,13 +1019,6 @@
 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV        (1 << 2)
 #define CRT_HOTPLUG_MASK                        (0x3fc) /* Bits 9-2 */
 #define CRT_FORCE_HOTPLUG_MASK                  0xfffffe1f
-#define HOTPLUG_EN_MASK (HDMIB_HOTPLUG_INT_EN | \
-                         HDMIC_HOTPLUG_INT_EN |   \
-                         HDMID_HOTPLUG_INT_EN |   \
-                         SDVOB_HOTPLUG_INT_EN |   \
-                         SDVOC_HOTPLUG_INT_EN |   \
-                         CRT_HOTPLUG_INT_EN)
 #define PORT_HOTPLUG_STAT       0x61114
 #define   HDMIB_HOTPLUG_INT_STATUS              (1 << 29)
@@ -982,6 +1115,8 @@
 #define   LVDS_PORT_EN                  (1 << 31)
 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
 #define   LVDS_PIPEB_SELECT             (1 << 30)
+/* LVDS dithering flag on 965/g4x platform */
+#define   LVDS_ENABLE_DITHER            (1 << 25)
 /* Enable border for unscaled (or aspect-scaled) display */
 #define   LVDS_BORDER_ENABLE            (1 << 15)
 /*
@@ -1751,6 +1886,8 @@
 /* Display & cursor control */
+/* dithering flag on Ironlake */
+#define PIPE_ENABLE_DITHER      (1 << 4)
 /* Pipe A */
 #define PIPEADSL                0x70000
 #define PIPEACONF               0x70008
@@ -1818,7 +1955,7 @@
 #define   DSPFW_PLANEB_SHIFT    8
 #define DSPFW2                  0x70038
 #define   DSPFW_CURSORA_MASK    0x00003f00
-#define   DSPFW_CURSORA_SHIFT   16
+#define   DSPFW_CURSORA_SHIFT   8
 #define DSPFW3                  0x7003c
 #define   DSPFW_HPLL_SR_EN      (1<<31)
 #define   DSPFW_CURSOR_SR_SHIFT 24
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index d5ebb00a9d49..ac0d1a73ac22 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -682,6 +682,8 @@ void i915_restore_display(struct drm_device *dev)
                I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
                I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
                I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
+                I915_WRITE(MCHBAR_RENDER_STANDBY,
+                           dev_priv->saveMCHBAR_RENDER_STANDBY);
        } else {
                I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
                I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
@@ -732,12 +734,6 @@ int i915_save_state(struct drm_device *dev)
        pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
-        /* Render Standby */
-        if (I915_HAS_RC6(dev)) {
-                dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
-                dev_priv->savePWRCTXA = I915_READ(PWRCTXA);
-        }
        /* Hardware status page */
        dev_priv->saveHWS = I915_READ(HWS_PGA);
@@ -751,11 +747,16 @@ int i915_save_state(struct drm_device *dev)
                dev_priv->saveGTIMR = I915_READ(GTIMR);
                dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR);
                dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR);
+                dev_priv->saveMCHBAR_RENDER_STANDBY =
+                        I915_READ(MCHBAR_RENDER_STANDBY);
        } else {
                dev_priv->saveIER = I915_READ(IER);
                dev_priv->saveIMR = I915_READ(IMR);
        }
+        if (IS_IRONLAKE_M(dev))
+                ironlake_disable_drps(dev);
        /* Cache mode state */
        dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
@@ -793,12 +794,6 @@ int i915_restore_state(struct drm_device *dev)
        pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
-        /* Render Standby */
-        if (I915_HAS_RC6(dev)) {
-                I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
-                I915_WRITE(PWRCTXA, dev_priv->savePWRCTXA);
-        }
        /* Hardware status page */
        I915_WRITE(HWS_PGA, dev_priv->saveHWS);
@@ -832,6 +827,9 @@ int i915_restore_state(struct drm_device *dev)
        /* Clock gating state */
        intel_init_clock_gating(dev);
+        if (IS_IRONLAKE_M(dev))
+                ironlake_enable_drps(dev);
        /* Cache mode state */
        I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index f27567747580..15fbc1b5a83e 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -33,6 +33,8 @@
 #define SLAVE_ADDR1     0x70
 #define SLAVE_ADDR2     0x72
+static int panel_type;
 static void *
 find_section(struct bdb_header *bdb, int section_id)
 {
@@ -128,6 +130,7 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
        dev_priv->lvds_dither = lvds_options->pixel_dither;
        if (lvds_options->panel_type == 0xff)
                return;
+        panel_type = lvds_options->panel_type;
        lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
        if (!lvds_lfp_data)
@@ -197,7 +200,8 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
                memset(temp_mode, 0, sizeof(*temp_mode));
        }
        kfree(temp_mode);
-        if (temp_downclock < panel_fixed_mode->clock) {
+        if (temp_downclock < panel_fixed_mode->clock &&
+            i915_lvds_downclock) {
                dev_priv->lvds_downclock_avail = 1;
                dev_priv->lvds_downclock = temp_downclock;
                DRM_DEBUG_KMS("LVDS downclock is found in VBT. ",
@@ -405,6 +409,34 @@ parse_driver_features(struct drm_i915_private *dev_priv,
 }
 static void
+parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
+{
+        struct bdb_edp *edp;
+        edp = find_section(bdb, BDB_EDP);
+        if (!edp) {
+                if (SUPPORTS_EDP(dev_priv->dev) && dev_priv->edp_support) {
+                        DRM_DEBUG_KMS("No eDP BDB found but eDP panel supported,\
+                                       assume 18bpp panel color depth.\n");
+                        dev_priv->edp_bpp = 18;
+                }
+                return;
+        }
+        switch ((edp->color_depth >> (panel_type * 2)) & 3) {
+        case EDP_18BPP:
+                dev_priv->edp_bpp = 18;
+                break;
+        case EDP_24BPP:
+                dev_priv->edp_bpp = 24;
+                break;
+        case EDP_30BPP:
+                dev_priv->edp_bpp = 30;
+                break;
+        }
+}
+static void
 parse_device_mapping(struct drm_i915_private *dev_priv,
                       struct bdb_header *bdb)
 {
@@ -521,6 +553,7 @@ intel_init_bios(struct drm_device *dev)
        parse_sdvo_device_mapping(dev_priv, bdb);
        parse_device_mapping(dev_priv, bdb);
        parse_driver_features(dev_priv, bdb);
+        parse_edp(dev_priv, bdb);
        pci_unmap_rom(pdev, bios);
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 425ac9d7f724..4c18514f6f80 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -98,6 +98,7 @@ struct vbios_data {
 #define BDB_SDVO_LVDS_PNP_IDS    24
 #define BDB_SDVO_LVDS_POWER_SEQ  25
 #define BDB_TV_OPTIONS           26
+#define BDB_EDP                  27
 #define BDB_LVDS_OPTIONS         40
 #define BDB_LVDS_LFP_DATA_PTRS   41
 #define BDB_LVDS_LFP_DATA        42
@@ -426,6 +427,45 @@ struct bdb_driver_features {
        u8 custom_vbt_version;
 } __attribute__((packed));
+#define EDP_18BPP       0
+#define EDP_24BPP       1
+#define EDP_30BPP       2
+#define EDP_RATE_1_62   0
+#define EDP_RATE_2_7    1
+#define EDP_LANE_1      0
+#define EDP_LANE_2      1
+#define EDP_LANE_4      3
+#define EDP_PREEMPHASIS_NONE    0
+#define EDP_PREEMPHASIS_3_5dB   1
+#define EDP_PREEMPHASIS_6dB     2
+#define EDP_PREEMPHASIS_9_5dB   3
+#define EDP_VSWING_0_4V         0
+#define EDP_VSWING_0_6V         1
+#define EDP_VSWING_0_8V         2
+#define EDP_VSWING_1_2V         3
+struct edp_power_seq {
+        u16 t3;
+        u16 t7;
+        u16 t9;
+        u16 t10;
+        u16 t12;
+} __attribute__ ((packed));
+struct edp_link_params {
+        u8 rate:4;
+        u8 lanes:4;
+        u8 preemphasis:4;
+        u8 vswing:4;
+} __attribute__ ((packed));
+struct bdb_edp {
+        struct edp_power_seq power_seqs[16];
+        u32 color_depth;
+        u32 sdrrs_msa_timing_delay;
+        struct edp_link_params link_params[16];
+} __attribute__ ((packed));
 bool intel_init_bios(struct drm_device *dev);
 /*
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 9f3d3e563414..79dd4026586f 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -157,6 +157,9 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
        adpa = I915_READ(PCH_ADPA);
        adpa &= ~ADPA_CRT_HOTPLUG_MASK;
+        /* disable HPD first */
+        I915_WRITE(PCH_ADPA, adpa);
+        (void)I915_READ(PCH_ADPA);
        adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 |
                        ADPA_CRT_HOTPLUG_WARMUP_10MS |
@@ -548,4 +551,6 @@ void intel_crt_init(struct drm_device *dev)
        drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
        drm_sysfs_connector_add(connector);
+        dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 52cd9b006da2..1b5cd833bc70 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -70,8 +70,6 @@ struct intel_limit {
    intel_p2_t      p2;
    bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
                      int, int, intel_clock_t *);
-    bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
-                              int, int, intel_clock_t *);
 };
 #define I8XX_DOT_MIN              25000
@@ -242,38 +240,93 @@ struct intel_limit {
 #define IRONLAKE_DOT_MAX         350000
 #define IRONLAKE_VCO_MIN         1760000
 #define IRONLAKE_VCO_MAX         3510000
-#define IRONLAKE_N_MIN           1
-#define IRONLAKE_N_MAX           5
-#define IRONLAKE_M_MIN           79
-#define IRONLAKE_M_MAX           118
 #define IRONLAKE_M1_MIN          12
-#define IRONLAKE_M1_MAX          23
+#define IRONLAKE_M1_MAX          22
 #define IRONLAKE_M2_MIN          5
 #define IRONLAKE_M2_MAX          9
-#define IRONLAKE_P_SDVO_DAC_MIN  5
-#define IRONLAKE_P_SDVO_DAC_MAX  80
-#define IRONLAKE_P_LVDS_MIN      28
-#define IRONLAKE_P_LVDS_MAX      112
-#define IRONLAKE_P1_MIN          1
-#define IRONLAKE_P1_MAX          8
-#define IRONLAKE_P2_SDVO_DAC_SLOW 10
-#define IRONLAKE_P2_SDVO_DAC_FAST 5
-#define IRONLAKE_P2_LVDS_SLOW    14 /* single channel */
-#define IRONLAKE_P2_LVDS_FAST    7  /* double channel */
 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
+/* We have parameter ranges for different type of outputs. */
+/* DAC & HDMI Refclk 120Mhz */
+#define IRONLAKE_DAC_N_MIN      1
+#define IRONLAKE_DAC_N_MAX      5
+#define IRONLAKE_DAC_M_MIN      79
+#define IRONLAKE_DAC_M_MAX      127
+#define IRONLAKE_DAC_P_MIN      5
+#define IRONLAKE_DAC_P_MAX      80
+#define IRONLAKE_DAC_P1_MIN     1
+#define IRONLAKE_DAC_P1_MAX     8
+#define IRONLAKE_DAC_P2_SLOW    10
+#define IRONLAKE_DAC_P2_FAST    5
+/* LVDS single-channel 120Mhz refclk */
+#define IRONLAKE_LVDS_S_N_MIN   1
+#define IRONLAKE_LVDS_S_N_MAX   3
+#define IRONLAKE_LVDS_S_M_MIN   79
+#define IRONLAKE_LVDS_S_M_MAX   118
+#define IRONLAKE_LVDS_S_P_MIN   28
+#define IRONLAKE_LVDS_S_P_MAX   112
+#define IRONLAKE_LVDS_S_P1_MIN  2
+#define IRONLAKE_LVDS_S_P1_MAX  8
+#define IRONLAKE_LVDS_S_P2_SLOW 14
+#define IRONLAKE_LVDS_S_P2_FAST 14
+/* LVDS dual-channel 120Mhz refclk */
+#define IRONLAKE_LVDS_D_N_MIN   1
+#define IRONLAKE_LVDS_D_N_MAX   3
+#define IRONLAKE_LVDS_D_M_MIN   79
+#define IRONLAKE_LVDS_D_M_MAX   127
+#define IRONLAKE_LVDS_D_P_MIN   14
+#define IRONLAKE_LVDS_D_P_MAX   56
+#define IRONLAKE_LVDS_D_P1_MIN  2
+#define IRONLAKE_LVDS_D_P1_MAX  8
+#define IRONLAKE_LVDS_D_P2_SLOW 7
+#define IRONLAKE_LVDS_D_P2_FAST 7
+/* LVDS single-channel 100Mhz refclk */
+#define IRONLAKE_LVDS_S_SSC_N_MIN       1
+#define IRONLAKE_LVDS_S_SSC_N_MAX       2
+#define IRONLAKE_LVDS_S_SSC_M_MIN       79
+#define IRONLAKE_LVDS_S_SSC_M_MAX       126
+#define IRONLAKE_LVDS_S_SSC_P_MIN       28
+#define IRONLAKE_LVDS_S_SSC_P_MAX       112
+#define IRONLAKE_LVDS_S_SSC_P1_MIN      2
+#define IRONLAKE_LVDS_S_SSC_P1_MAX      8
+#define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
+#define IRONLAKE_LVDS_S_SSC_P2_FAST     14
+/* LVDS dual-channel 100Mhz refclk */
+#define IRONLAKE_LVDS_D_SSC_N_MIN       1
+#define IRONLAKE_LVDS_D_SSC_N_MAX       3
+#define IRONLAKE_LVDS_D_SSC_M_MIN       79
+#define IRONLAKE_LVDS_D_SSC_M_MAX       126
+#define IRONLAKE_LVDS_D_SSC_P_MIN       14
+#define IRONLAKE_LVDS_D_SSC_P_MAX       42
+#define IRONLAKE_LVDS_D_SSC_P1_MIN      2
+#define IRONLAKE_LVDS_D_SSC_P1_MAX      6
+#define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
+#define IRONLAKE_LVDS_D_SSC_P2_FAST     7
+/* DisplayPort */
+#define IRONLAKE_DP_N_MIN               1
+#define IRONLAKE_DP_N_MAX               2
+#define IRONLAKE_DP_M_MIN               81
+#define IRONLAKE_DP_M_MAX               90
+#define IRONLAKE_DP_P_MIN               10
+#define IRONLAKE_DP_P_MAX               20
+#define IRONLAKE_DP_P2_FAST             10
+#define IRONLAKE_DP_P2_SLOW             10
+#define IRONLAKE_DP_P2_LIMIT            0
+#define IRONLAKE_DP_P1_MIN              1
+#define IRONLAKE_DP_P1_MAX              2
 static bool
 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                    int target, int refclk, intel_clock_t *best_clock);
 static bool
-intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
-                            int target, int refclk, intel_clock_t *best_clock);
-static bool
 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                        int target, int refclk, intel_clock_t *best_clock);
-static bool
-intel_ironlake_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
-                             int target, int refclk, intel_clock_t *best_clock);
 static bool
 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
@@ -294,7 +347,6 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
        .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
                 .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
        .find_pll = intel_find_best_PLL,
-        .find_reduced_pll = intel_find_best_reduced_PLL,
 };
 static const intel_limit_t intel_limits_i8xx_lvds = {
@@ -309,7 +361,6 @@ static const intel_limit_t intel_limits_i8xx_lvds = {
        .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
                 .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
        .find_pll = intel_find_best_PLL,
-        .find_reduced_pll = intel_find_best_reduced_PLL,
 };
        
 static const intel_limit_t intel_limits_i9xx_sdvo = {
@@ -324,7 +375,6 @@ static const intel_limit_t intel_limits_i9xx_sdvo = {
        .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
                 .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
        .find_pll = intel_find_best_PLL,
-        .find_reduced_pll = intel_find_best_reduced_PLL,
 };
 static const intel_limit_t intel_limits_i9xx_lvds = {
@@ -342,7 +392,6 @@ static const intel_limit_t intel_limits_i9xx_lvds = {
        .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
                 .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
        .find_pll = intel_find_best_PLL,
-        .find_reduced_pll = intel_find_best_reduced_PLL,
 };
    /* below parameter and function is for G4X Chipset Family*/
@@ -360,7 +409,6 @@ static const intel_limit_t intel_limits_g4x_sdvo = {
                 .p2_fast = G4X_P2_SDVO_FAST
        },
        .find_pll = intel_g4x_find_best_PLL,
-        .find_reduced_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_g4x_hdmi = {
@@ -377,7 +425,6 @@ static const intel_limit_t intel_limits_g4x_hdmi = {
                 .p2_fast = G4X_P2_HDMI_DAC_FAST
        },
        .find_pll = intel_g4x_find_best_PLL,
-        .find_reduced_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
@@ -402,7 +449,6 @@ static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
                 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
        },
        .find_pll = intel_g4x_find_best_PLL,
-        .find_reduced_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
@@ -427,7 +473,6 @@ static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
                 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
        },
        .find_pll = intel_g4x_find_best_PLL,
-        .find_reduced_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_g4x_display_port = {
@@ -465,7 +510,6 @@ static const intel_limit_t intel_limits_pineview_sdvo = {
        .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
                 .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
        .find_pll = intel_find_best_PLL,
-        .find_reduced_pll = intel_find_best_reduced_PLL,
 };
 static const intel_limit_t intel_limits_pineview_lvds = {
@@ -481,46 +525,135 @@ static const intel_limit_t intel_limits_pineview_lvds = {
        .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
                 .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
        .find_pll = intel_find_best_PLL,
-        .find_reduced_pll = intel_find_best_reduced_PLL,
 };
-static const intel_limit_t intel_limits_ironlake_sdvo = {
+static const intel_limit_t intel_limits_ironlake_dac = {
+        .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
+        .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
+        .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
+        .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
+        .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
+        .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
+        .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
+        .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
+        .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
+                 .p2_slow = IRONLAKE_DAC_P2_SLOW,
+                 .p2_fast = IRONLAKE_DAC_P2_FAST },
+        .find_pll = intel_g4x_find_best_PLL,
+};
+static const intel_limit_t intel_limits_ironlake_single_lvds = {
+        .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
+        .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
+        .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
+        .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
+        .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
+        .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
+        .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
+        .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
+        .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
+                 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
+                 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
+        .find_pll = intel_g4x_find_best_PLL,
+};
+static const intel_limit_t intel_limits_ironlake_dual_lvds = {
+        .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
+        .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
+        .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
+        .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
+        .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
+        .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
+        .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
+        .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
+        .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
+                 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
+                 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
+        .find_pll = intel_g4x_find_best_PLL,
+};
+static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
        .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
        .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
-        .n   = { .min = IRONLAKE_N_MIN,            .max = IRONLAKE_N_MAX },
+        .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
-        .m   = { .min = IRONLAKE_M_MIN,            .max = IRONLAKE_M_MAX },
+        .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
        .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
        .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
-        .p   = { .min = IRONLAKE_P_SDVO_DAC_MIN,   .max = IRONLAKE_P_SDVO_DAC_MAX },
+        .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
-        .p1  = { .min = IRONLAKE_P1_MIN,           .max = IRONLAKE_P1_MAX },
+        .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
        .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
-                 .p2_slow = IRONLAKE_P2_SDVO_DAC_SLOW,
+                 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
-                 .p2_fast = IRONLAKE_P2_SDVO_DAC_FAST },
+                 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
-        .find_pll = intel_ironlake_find_best_PLL,
+        .find_pll = intel_g4x_find_best_PLL,
 };
-static const intel_limit_t intel_limits_ironlake_lvds = {
+static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
        .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
        .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
-        .n   = { .min = IRONLAKE_N_MIN,            .max = IRONLAKE_N_MAX },
+        .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
-        .m   = { .min = IRONLAKE_M_MIN,            .max = IRONLAKE_M_MAX },
+        .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
        .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
        .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
-        .p   = { .min = IRONLAKE_P_LVDS_MIN,       .max = IRONLAKE_P_LVDS_MAX },
+        .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
-        .p1  = { .min = IRONLAKE_P1_MIN,           .max = IRONLAKE_P1_MAX },
+        .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
        .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
-                 .p2_slow = IRONLAKE_P2_LVDS_SLOW,
+                 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
-                 .p2_fast = IRONLAKE_P2_LVDS_FAST },
+                 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
-        .find_pll = intel_ironlake_find_best_PLL,
+        .find_pll = intel_g4x_find_best_PLL,
+};
+static const intel_limit_t intel_limits_ironlake_display_port = {
+        .dot = { .min = IRONLAKE_DOT_MIN,
+                 .max = IRONLAKE_DOT_MAX },
+        .vco = { .min = IRONLAKE_VCO_MIN,
+                 .max = IRONLAKE_VCO_MAX},
+        .n   = { .min = IRONLAKE_DP_N_MIN,
+                 .max = IRONLAKE_DP_N_MAX },
+        .m   = { .min = IRONLAKE_DP_M_MIN,
+                 .max = IRONLAKE_DP_M_MAX },
+        .m1  = { .min = IRONLAKE_M1_MIN,
+                 .max = IRONLAKE_M1_MAX },
+        .m2  = { .min = IRONLAKE_M2_MIN,
+                 .max = IRONLAKE_M2_MAX },
+        .p   = { .min = IRONLAKE_DP_P_MIN,
+                 .max = IRONLAKE_DP_P_MAX },
+        .p1  = { .min = IRONLAKE_DP_P1_MIN,
+                 .max = IRONLAKE_DP_P1_MAX},
+        .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
+                 .p2_slow = IRONLAKE_DP_P2_SLOW,
+                 .p2_fast = IRONLAKE_DP_P2_FAST },
+        .find_pll = intel_find_pll_ironlake_dp,
 };
 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 {
+        struct drm_device *dev = crtc->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
        const intel_limit_t *limit;
-        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
+        int refclk = 120;
-                limit = &intel_limits_ironlake_lvds;
+        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
+                if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
+                        refclk = 100;
+                if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
+                    LVDS_CLKB_POWER_UP) {
+                        /* LVDS dual channel */
+                        if (refclk == 100)
+                                limit = &intel_limits_ironlake_dual_lvds_100m;
+                        else
+                                limit = &intel_limits_ironlake_dual_lvds;
+                } else {
+                        if (refclk == 100)
+                                limit = &intel_limits_ironlake_single_lvds_100m;
+                        else
+                                limit = &intel_limits_ironlake_single_lvds;
+                }
+        } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
+                        HAS_eDP)
+                limit = &intel_limits_ironlake_display_port;
        else
-                limit = &intel_limits_ironlake_sdvo;
+                limit = &intel_limits_ironlake_dac;
        return limit;
 }
@@ -737,46 +870,6 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
        return (err != target);
 }
-static bool
-intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
-                            int target, int refclk, intel_clock_t *best_clock)
-{
-        struct drm_device *dev = crtc->dev;
-        intel_clock_t clock;
-        int err = target;
-        bool found = false;
-        memcpy(&clock, best_clock, sizeof(intel_clock_t));
-        for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
-                for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
-                        /* m1 is always 0 in Pineview */
-                        if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
-                                break;
-                        for (clock.n = limit->n.min; clock.n <= limit->n.max;
-                             clock.n++) {
-                                int this_err;
-                                intel_clock(dev, refclk, &clock);
-                                if (!intel_PLL_is_valid(crtc, &clock))
-                                        continue;
-                                this_err = abs(clock.dot - target);
-                                if (this_err < err) {
-                                        *best_clock = clock;
-                                        err = this_err;
-                                        found = true;
-                                }
-                        }
-                }
-        }
-        return found;
-}
 static bool
 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                        int target, int refclk, intel_clock_t *best_clock)
@@ -791,7 +884,13 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
        found = false;
        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
-                if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
+                int lvds_reg;
+                if (IS_IRONLAKE(dev))
+                        lvds_reg = PCH_LVDS;
+                else
+                        lvds_reg = LVDS;
+                if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
                    LVDS_CLKB_POWER_UP)
                        clock.p2 = limit->p2.p2_fast;
                else
@@ -839,6 +938,11 @@ intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 {
        struct drm_device *dev = crtc->dev;
        intel_clock_t clock;
+        /* return directly when it is eDP */
+        if (HAS_eDP)
+                return true;
        if (target < 200000) {
                clock.n = 1;
                clock.p1 = 2;
@@ -857,68 +961,6 @@ intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
        return true;
 }
-static bool
-intel_ironlake_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
-                             int target, int refclk, intel_clock_t *best_clock)
-{
-        struct drm_device *dev = crtc->dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        intel_clock_t clock;
-        int err_most = 47;
-        int err_min = 10000;
-        /* eDP has only 2 clock choice, no n/m/p setting */
-        if (HAS_eDP)
-                return true;
-        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
-                return intel_find_pll_ironlake_dp(limit, crtc, target,
-                                               refclk, best_clock);
-        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
-                if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
-                    LVDS_CLKB_POWER_UP)
-                        clock.p2 = limit->p2.p2_fast;
-                else
-                        clock.p2 = limit->p2.p2_slow;
-        } else {
-                if (target < limit->p2.dot_limit)
-                        clock.p2 = limit->p2.p2_slow;
-                else
-                        clock.p2 = limit->p2.p2_fast;
-        }
-        memset(best_clock, 0, sizeof(*best_clock));
-        for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
-                /* based on hardware requriment prefer smaller n to precision */
-                for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
-                        /* based on hardware requirment prefere larger m1,m2 */
-                        for (clock.m1 = limit->m1.max;
-                             clock.m1 >= limit->m1.min; clock.m1--) {
-                                for (clock.m2 = limit->m2.max;
-                                     clock.m2 >= limit->m2.min; clock.m2--) {
-                                        int this_err;
-                                        intel_clock(dev, refclk, &clock);
-                                        if (!intel_PLL_is_valid(crtc, &clock))
-                                                continue;
-                                        this_err = abs((10000 - (target*10000/clock.dot)));
-                                        if (this_err < err_most) {
-                                                *best_clock = clock;
-                                                /* found on first matching */
-                                                goto out;
-                                        } else if (this_err < err_min) {
-                                                *best_clock = clock;
-                                                err_min = this_err;
-                                        }
-                                }
-                        }
-                }
-        }
-out:
-        return true;
-}
 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 static bool
 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
@@ -989,6 +1031,8 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
        /* enable it... */
        fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
+        if (IS_I945GM(dev))
+                fbc_ctl |= FBC_C3_IDLE; /* 945 needs special SR handling */
        fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
        fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
        if (obj_priv->tiling_mode != I915_TILING_NONE)
@@ -1144,25 +1188,30 @@ static void intel_update_fbc(struct drm_crtc *crtc,
        if (intel_fb->obj->size > dev_priv->cfb_size) {
                DRM_DEBUG_KMS("framebuffer too large, disabling "
                                "compression\n");
+                dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
                goto out_disable;
        }
        if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
            (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
                DRM_DEBUG_KMS("mode incompatible with compression, "
                                "disabling\n");
+                dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
                goto out_disable;
        }
        if ((mode->hdisplay > 2048) ||
            (mode->vdisplay > 1536)) {
                DRM_DEBUG_KMS("mode too large for compression, disabling\n");
+                dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
                goto out_disable;
        }
        if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
                DRM_DEBUG_KMS("plane not 0, disabling compression\n");
+                dev_priv->no_fbc_reason = FBC_BAD_PLANE;
                goto out_disable;
        }
        if (obj_priv->tiling_mode != I915_TILING_X) {
                DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
+                dev_priv->no_fbc_reason = FBC_NOT_TILED;
                goto out_disable;
        }
@@ -1282,7 +1331,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                return ret;
        }
-        ret = i915_gem_object_set_to_gtt_domain(obj, 1);
+        ret = i915_gem_object_set_to_display_plane(obj);
        if (ret != 0) {
                i915_gem_object_unpin(obj);
                mutex_unlock(&dev->struct_mutex);
@@ -1493,6 +1542,10 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
        int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
        u32 temp;
        int tries = 5, j, n;
+        u32 pipe_bpc;
+        temp = I915_READ(pipeconf_reg);
+        pipe_bpc = temp & PIPE_BPC_MASK;
        /* XXX: When our outputs are all unaware of DPMS modes other than off
         * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
@@ -1524,6 +1577,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
                        /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
                        temp = I915_READ(fdi_rx_reg);
+                        /*
+                         * make the BPC in FDI Rx be consistent with that in
+                         * pipeconf reg.
+                         */
+                        temp &= ~(0x7 << 16);
+                        temp |= (pipe_bpc << 11);
                        I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
                                        FDI_SEL_PCDCLK |
                                        FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
@@ -1666,6 +1725,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
                        /* enable PCH transcoder */
                        temp = I915_READ(transconf_reg);
+                        /*
+                         * make the BPC in transcoder be consistent with
+                         * that in pipeconf reg.
+                         */
+                        temp &= ~PIPE_BPC_MASK;
+                        temp |= pipe_bpc;
                        I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
                        I915_READ(transconf_reg);
@@ -1697,6 +1762,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
        case DRM_MODE_DPMS_OFF:
                DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
+                drm_vblank_off(dev, pipe);
                /* Disable display plane */
                temp = I915_READ(dspcntr_reg);
                if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
@@ -1745,6 +1811,9 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
                I915_READ(fdi_tx_reg);
                temp = I915_READ(fdi_rx_reg);
+                /* BPC in FDI rx is consistent with that in pipeconf */
+                temp &= ~(0x07 << 16);
+                temp |= (pipe_bpc << 11);
                I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
                I915_READ(fdi_rx_reg);
@@ -1789,7 +1858,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
                                }
                        }
                }
+                temp = I915_READ(transconf_reg);
+                /* BPC in transcoder is consistent with that in pipeconf */
+                temp &= ~PIPE_BPC_MASK;
+                temp |= pipe_bpc;
+                I915_WRITE(transconf_reg, temp);
+                I915_READ(transconf_reg);
                udelay(100);
                /* disable PCH DPLL */
@@ -2448,7 +2522,7 @@ static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
 * A value of 5us seems to be a good balance; safe for very low end
 * platforms but not overly aggressive on lower latency configs.
 */
-const static int latency_ns = 5000;
+static const int latency_ns = 5000;
 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 {
@@ -2559,7 +2633,7 @@ static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
        /* Calc sr entries for one plane configs */
        if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
                /* self-refresh has much higher latency */
-                const static int sr_latency_ns = 12000;
+                static const int sr_latency_ns = 12000;
                sr_clock = planea_clock ? planea_clock : planeb_clock;
                line_time_us = ((sr_hdisplay * 1000) / sr_clock);
@@ -2570,6 +2644,10 @@ static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
                sr_entries = roundup(sr_entries / cacheline_size, 1);
                DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
                I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
+        } else {
+                /* Turn off self refresh if both pipes are enabled */
+                I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
+                                        & ~FW_BLC_SELF_EN);
        }
        DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
@@ -2598,7 +2676,7 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
        /* Calc sr entries for one plane configs */
        if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
                /* self-refresh has much higher latency */
-                const static int sr_latency_ns = 12000;
+                static const int sr_latency_ns = 12000;
                sr_clock = planea_clock ? planea_clock : planeb_clock;
                line_time_us = ((sr_hdisplay * 1000) / sr_clock);
@@ -2613,6 +2691,10 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
                        srwm = 1;
                srwm &= 0x3f;
                I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
+        } else {
+                /* Turn off self refresh if both pipes are enabled */
+                I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
+                                        & ~FW_BLC_SELF_EN);
        }
        DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
@@ -2667,7 +2749,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
        if (HAS_FW_BLC(dev) && sr_hdisplay &&
            (!planea_clock || !planeb_clock)) {
                /* self-refresh has much higher latency */
-                const static int sr_latency_ns = 6000;
+                static const int sr_latency_ns = 6000;
                sr_clock = planea_clock ? planea_clock : planeb_clock;
                line_time_us = ((sr_hdisplay * 1000) / sr_clock);
@@ -2680,7 +2762,22 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
                srwm = total_size - sr_entries;
                if (srwm < 0)
                        srwm = 1;
-                I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
+                if (IS_I945G(dev) || IS_I945GM(dev))
+                        I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
+                else if (IS_I915GM(dev)) {
+                        /* 915M has a smaller SRWM field */
+                        I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
+                        I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
+                }
+        } else {
+                /* Turn off self refresh if both pipes are enabled */
+                if (IS_I945G(dev) || IS_I945GM(dev)) {
+                        I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
+                                   & ~FW_BLC_SELF_EN);
+                } else if (IS_I915GM(dev)) {
+                        I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
+                }
        }
        DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
@@ -2906,10 +3003,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                return -EINVAL;
        }
-        if (is_lvds && limit->find_reduced_pll &&
+        if (is_lvds && dev_priv->lvds_downclock_avail) {
-                        dev_priv->lvds_downclock_avail) {
+                has_reduced_clock = limit->find_pll(limit, crtc,
-                memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
-                has_reduced_clock = limit->find_reduced_pll(limit, crtc,
                                                            dev_priv->lvds_downclock,
                                                            refclk,
                                                            &reduced_clock);
@@ -2969,6 +3064,33 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                /* determine panel color depth */
                temp = I915_READ(pipeconf_reg);
+                temp &= ~PIPE_BPC_MASK;
+                if (is_lvds) {
+                        int lvds_reg = I915_READ(PCH_LVDS);
+                        /* the BPC will be 6 if it is 18-bit LVDS panel */
+                        if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
+                                temp |= PIPE_8BPC;
+                        else
+                                temp |= PIPE_6BPC;
+                } else if (is_edp) {
+                        switch (dev_priv->edp_bpp/3) {
+                        case 8:
+                                temp |= PIPE_8BPC;
+                                break;
+                        case 10:
+                                temp |= PIPE_10BPC;
+                                break;
+                        case 6:
+                                temp |= PIPE_6BPC;
+                                break;
+                        case 12:
+                                temp |= PIPE_12BPC;
+                                break;
+                        }
+                } else
+                        temp |= PIPE_8BPC;
+                I915_WRITE(pipeconf_reg, temp);
+                I915_READ(pipeconf_reg);
                switch (temp & PIPE_BPC_MASK) {
                case PIPE_8BPC:
@@ -3195,7 +3317,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                 * appropriately here, but we need to look more thoroughly into how
                 * panels behave in the two modes.
                 */
+                /* set the dithering flag */
+                if (IS_I965G(dev)) {
+                        if (dev_priv->lvds_dither) {
+                                if (IS_IRONLAKE(dev))
+                                        pipeconf |= PIPE_ENABLE_DITHER;
+                                else
+                                        lvds |= LVDS_ENABLE_DITHER;
+                        } else {
+                                if (IS_IRONLAKE(dev))
+                                        pipeconf &= ~PIPE_ENABLE_DITHER;
+                                else
+                                        lvds &= ~LVDS_ENABLE_DITHER;
+                        }
+                }
                I915_WRITE(lvds_reg, lvds);
                I915_READ(lvds_reg);
        }
@@ -3385,7 +3520,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
        /* we only need to pin inside GTT if cursor is non-phy */
        mutex_lock(&dev->struct_mutex);
-        if (!dev_priv->cursor_needs_physical) {
+        if (!dev_priv->info->cursor_needs_physical) {
                ret = i915_gem_object_pin(bo, PAGE_SIZE);
                if (ret) {
                        DRM_ERROR("failed to pin cursor bo\n");
@@ -3420,7 +3555,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
        I915_WRITE(base, addr);
        if (intel_crtc->cursor_bo) {
-                if (dev_priv->cursor_needs_physical) {
+                if (dev_priv->info->cursor_needs_physical) {
                        if (intel_crtc->cursor_bo != bo)
                                i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
                } else
@@ -3434,11 +3569,10 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
        intel_crtc->cursor_bo = bo;
        return 0;
-fail:
-        mutex_lock(&dev->struct_mutex);
 fail_locked:
-        drm_gem_object_unreference(bo);
        mutex_unlock(&dev->struct_mutex);
+fail:
+        drm_gem_object_unreference_unlocked(bo);
        return ret;
 }
@@ -3779,125 +3913,6 @@ static void intel_gpu_idle_timer(unsigned long arg)
        queue_work(dev_priv->wq, &dev_priv->idle_work);
 }
-void intel_increase_renderclock(struct drm_device *dev, bool schedule)
-{
-        drm_i915_private_t *dev_priv = dev->dev_private;
-        if (IS_IRONLAKE(dev))
-                return;
-        if (!dev_priv->render_reclock_avail) {
-                DRM_DEBUG_DRIVER("not reclocking render clock\n");
-                return;
-        }
-        /* Restore render clock frequency to original value */
-        if (IS_G4X(dev) || IS_I9XX(dev))
-                pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
-        else if (IS_I85X(dev))
-                pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
-        DRM_DEBUG_DRIVER("increasing render clock frequency\n");
-        /* Schedule downclock */
-        if (schedule)
-                mod_timer(&dev_priv->idle_timer, jiffies +
-                          msecs_to_jiffies(GPU_IDLE_TIMEOUT));
-}
-void intel_decrease_renderclock(struct drm_device *dev)
-{
-        drm_i915_private_t *dev_priv = dev->dev_private;
-        if (IS_IRONLAKE(dev))
-                return;
-        if (!dev_priv->render_reclock_avail) {
-                DRM_DEBUG_DRIVER("not reclocking render clock\n");
-                return;
-        }
-        if (IS_G4X(dev)) {
-                u16 gcfgc;
-                /* Adjust render clock... */
-                pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
-                /* Down to minimum... */
-                gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
-                gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
-                pci_write_config_word(dev->pdev, GCFGC, gcfgc);
-        } else if (IS_I965G(dev)) {
-                u16 gcfgc;
-                /* Adjust render clock... */
-                pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
-                /* Down to minimum... */
-                gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
-                gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
-                pci_write_config_word(dev->pdev, GCFGC, gcfgc);
-        } else if (IS_I945G(dev) || IS_I945GM(dev)) {
-                u16 gcfgc;
-                /* Adjust render clock... */
-                pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
-                /* Down to minimum... */
-                gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
-                gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
-                pci_write_config_word(dev->pdev, GCFGC, gcfgc);
-        } else if (IS_I915G(dev)) {
-                u16 gcfgc;
-                /* Adjust render clock... */
-                pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
-                /* Down to minimum... */
-                gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
-                gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
-                pci_write_config_word(dev->pdev, GCFGC, gcfgc);
-        } else if (IS_I85X(dev)) {
-                u16 hpllcc;
-                /* Adjust render clock... */
-                pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
-                /* Up to maximum... */
-                hpllcc &= ~GC_CLOCK_CONTROL_MASK;
-                hpllcc |= GC_CLOCK_133_200;
-                pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
-        }
-        DRM_DEBUG_DRIVER("decreasing render clock frequency\n");
-}
-/* Note that no increase function is needed for this - increase_renderclock()
- *  will also rewrite these bits
- */
-void intel_decrease_displayclock(struct drm_device *dev)
-{
-        if (IS_IRONLAKE(dev))
-                return;
-        if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
-            IS_I915GM(dev)) {
-                u16 gcfgc;
-                /* Adjust render clock... */
-                pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
-                /* Down to minimum... */
-                gcfgc &= ~0xf0;
-                gcfgc |= 0x80;
-                pci_write_config_word(dev->pdev, GCFGC, gcfgc);
-        }
-}
 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
 static void intel_crtc_idle_timer(unsigned long arg)
@@ -4011,10 +4026,9 @@ static void intel_idle_update(struct work_struct *work)
        mutex_lock(&dev->struct_mutex);
-        /* GPU isn't processing, downclock it. */
+        if (IS_I945G(dev) || IS_I945GM(dev)) {
-        if (!dev_priv->busy) {
+                DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
-                intel_decrease_renderclock(dev);
+                I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
-                intel_decrease_displayclock(dev);
        }
        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
@@ -4051,12 +4065,18 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
                return;
        if (!dev_priv->busy) {
+                if (IS_I945G(dev) || IS_I945GM(dev)) {
+                        u32 fw_blc_self;
+                        DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
+                        fw_blc_self = I915_READ(FW_BLC_SELF);
+                        fw_blc_self &= ~FW_BLC_SELF_EN;
+                        I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
+                }
                dev_priv->busy = true;
-                intel_increase_renderclock(dev, true);
+        } else
-        } else {
                mod_timer(&dev_priv->idle_timer, jiffies +
                          msecs_to_jiffies(GPU_IDLE_TIMEOUT));
-        }
        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                if (!crtc->fb)
@@ -4066,6 +4086,14 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
                intel_fb = to_intel_framebuffer(crtc->fb);
                if (intel_fb->obj == obj) {
                        if (!intel_crtc->busy) {
+                                if (IS_I945G(dev) || IS_I945GM(dev)) {
+                                        u32 fw_blc_self;
+                                        DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
+                                        fw_blc_self = I915_READ(FW_BLC_SELF);
+                                        fw_blc_self &= ~FW_BLC_SELF_EN;
+                                        I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
+                                }
                                /* Non-busy -> busy, upclock */
                                intel_increase_pllclock(crtc, true);
                                intel_crtc->busy = true;
@@ -4089,7 +4117,8 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
 struct intel_unpin_work {
        struct work_struct work;
        struct drm_device *dev;
-        struct drm_gem_object *obj;
+        struct drm_gem_object *old_fb_obj;
+        struct drm_gem_object *pending_flip_obj;
        struct drm_pending_vblank_event *event;
        int pending;
 };
@@ -4100,8 +4129,9 @@ static void intel_unpin_work_fn(struct work_struct *__work)
                container_of(__work, struct intel_unpin_work, work);
        mutex_lock(&work->dev->struct_mutex);
-        i915_gem_object_unpin(work->obj);
+        i915_gem_object_unpin(work->old_fb_obj);
-        drm_gem_object_unreference(work->obj);
+        drm_gem_object_unreference(work->pending_flip_obj);
+        drm_gem_object_unreference(work->old_fb_obj);
        mutex_unlock(&work->dev->struct_mutex);
        kfree(work);
 }
@@ -4124,6 +4154,12 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe)
        spin_lock_irqsave(&dev->event_lock, flags);
        work = intel_crtc->unpin_work;
        if (work == NULL || !work->pending) {
+                if (work && !work->pending) {
+                        obj_priv = work->pending_flip_obj->driver_private;
+                        DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
+                                         obj_priv,
+                                         atomic_read(&obj_priv->pending_flip));
+                }
                spin_unlock_irqrestore(&dev->event_lock, flags);
                return;
        }
@@ -4144,8 +4180,11 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe)
        spin_unlock_irqrestore(&dev->event_lock, flags);
-        obj_priv = work->obj->driver_private;
+        obj_priv = work->pending_flip_obj->driver_private;
-        if (atomic_dec_and_test(&obj_priv->pending_flip))
+        /* Initial scanout buffer will have a 0 pending flip count */
+        if ((atomic_read(&obj_priv->pending_flip) == 0) ||
+            atomic_dec_and_test(&obj_priv->pending_flip))
                DRM_WAKEUP(&dev_priv->pending_flip_queue);
        schedule_work(&work->work);
 }
@@ -4158,8 +4197,11 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane)
        unsigned long flags;
        spin_lock_irqsave(&dev->event_lock, flags);
-        if (intel_crtc->unpin_work)
+        if (intel_crtc->unpin_work) {
                intel_crtc->unpin_work->pending = 1;
+        } else {
+                DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
+        }
        spin_unlock_irqrestore(&dev->event_lock, flags);
 }
@@ -4175,7 +4217,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        struct intel_unpin_work *work;
        unsigned long flags;
-        int ret;
+        int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
+        int ret, pipesrc;
        RING_LOCALS;
        work = kzalloc(sizeof *work, GFP_KERNEL);
@@ -4187,12 +4230,13 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
        work->event = event;
        work->dev = crtc->dev;
        intel_fb = to_intel_framebuffer(crtc->fb);
-        work->obj = intel_fb->obj;
+        work->old_fb_obj = intel_fb->obj;
        INIT_WORK(&work->work, intel_unpin_work_fn);
        /* We borrow the event spin lock for protecting unpin_work */
        spin_lock_irqsave(&dev->event_lock, flags);
        if (intel_crtc->unpin_work) {
+                DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
                spin_unlock_irqrestore(&dev->event_lock, flags);
                kfree(work);
                mutex_unlock(&dev->struct_mutex);
@@ -4206,19 +4250,24 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
        ret = intel_pin_and_fence_fb_obj(dev, obj);
        if (ret != 0) {
+                DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
+                          obj->driver_private);
                kfree(work);
+                intel_crtc->unpin_work = NULL;
                mutex_unlock(&dev->struct_mutex);
                return ret;
        }
-        /* Reference the old fb object for the scheduled work. */
+        /* Reference the objects for the scheduled work. */
-        drm_gem_object_reference(work->obj);
+        drm_gem_object_reference(work->old_fb_obj);
+        drm_gem_object_reference(obj);
        crtc->fb = fb;
        i915_gem_object_flush_write_domain(obj);
        drm_vblank_get(dev, intel_crtc->pipe);
        obj_priv = obj->driver_private;
        atomic_inc(&obj_priv->pending_flip);
+        work->pending_flip_obj = obj;
        BEGIN_LP_RING(4);
        OUT_RING(MI_DISPLAY_FLIP |
@@ -4226,7 +4275,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
        OUT_RING(fb->pitch);
        if (IS_I965G(dev)) {
                OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
-                OUT_RING((fb->width << 16) | fb->height);
+                pipesrc = I915_READ(pipesrc_reg); 
+                OUT_RING(pipesrc & 0x0fff0fff);
        } else {
                OUT_RING(obj_priv->gtt_offset);
                OUT_RING(MI_NOOP);
@@ -4400,29 +4450,43 @@ static void intel_setup_outputs(struct drm_device *dev)
                bool found = false;
                if (I915_READ(SDVOB) & SDVO_DETECTED) {
+                        DRM_DEBUG_KMS("probing SDVOB\n");
                        found = intel_sdvo_init(dev, SDVOB);
-                        if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
+                        if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
+                                DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
                                intel_hdmi_init(dev, SDVOB);
+                        }
-                        if (!found && SUPPORTS_INTEGRATED_DP(dev))
+                        if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
+                                DRM_DEBUG_KMS("probing DP_B\n");
                                intel_dp_init(dev, DP_B);
+                        }
                }
                /* Before G4X SDVOC doesn't have its own detect register */
-                if (I915_READ(SDVOB) & SDVO_DETECTED)
+                if (I915_READ(SDVOB) & SDVO_DETECTED) {
+                        DRM_DEBUG_KMS("probing SDVOC\n");
                        found = intel_sdvo_init(dev, SDVOC);
+                }
                if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
-                        if (SUPPORTS_INTEGRATED_HDMI(dev))
+                        if (SUPPORTS_INTEGRATED_HDMI(dev)) {
+                                DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
                                intel_hdmi_init(dev, SDVOC);
-                        if (SUPPORTS_INTEGRATED_DP(dev))
+                        }
+                        if (SUPPORTS_INTEGRATED_DP(dev)) {
+                                DRM_DEBUG_KMS("probing DP_C\n");
                                intel_dp_init(dev, DP_C);
+                        }
                }
-                if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
+                if (SUPPORTS_INTEGRATED_DP(dev) &&
+                    (I915_READ(DP_D) & DP_DETECTED)) {
+                        DRM_DEBUG_KMS("probing DP_D\n");
                        intel_dp_init(dev, DP_D);
+                }
        } else if (IS_I8XX(dev))
                intel_dvo_init(dev);
@@ -4448,9 +4512,7 @@ static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
                intelfb_remove(dev, fb);
        drm_framebuffer_cleanup(fb);
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(intel_fb->obj);
-        drm_gem_object_unreference(intel_fb->obj);
-        mutex_unlock(&dev->struct_mutex);
        kfree(intel_fb);
 }
@@ -4513,9 +4575,7 @@ intel_user_framebuffer_create(struct drm_device *dev,
        ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
        if (ret) {
-                mutex_lock(&dev->struct_mutex);
+                drm_gem_object_unreference_unlocked(obj);
-                drm_gem_object_unreference(obj);
-                mutex_unlock(&dev->struct_mutex);
                return NULL;
        }
@@ -4527,6 +4587,127 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
        .fb_changed = intelfb_probe,
 };
+static struct drm_gem_object *
+intel_alloc_power_context(struct drm_device *dev)
+{
+        struct drm_gem_object *pwrctx;
+        int ret;
+        pwrctx = drm_gem_object_alloc(dev, 4096);
+        if (!pwrctx) {
+                DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
+                return NULL;
+        }
+        mutex_lock(&dev->struct_mutex);
+        ret = i915_gem_object_pin(pwrctx, 4096);
+        if (ret) {
+                DRM_ERROR("failed to pin power context: %d\n", ret);
+                goto err_unref;
+        }
+        ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
+        if (ret) {
+                DRM_ERROR("failed to set-domain on power context: %d\n", ret);
+                goto err_unpin;
+        }
+        mutex_unlock(&dev->struct_mutex);
+        return pwrctx;
+err_unpin:
+        i915_gem_object_unpin(pwrctx);
+err_unref:
+        drm_gem_object_unreference(pwrctx);
+        mutex_unlock(&dev->struct_mutex);
+        return NULL;
+}
+void ironlake_enable_drps(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 rgvmodectl = I915_READ(MEMMODECTL), rgvswctl;
+        u8 fmax, fmin, fstart, vstart;
+        int i = 0;
+        /* 100ms RC evaluation intervals */
+        I915_WRITE(RCUPEI, 100000);
+        I915_WRITE(RCDNEI, 100000);
+        /* Set max/min thresholds to 90ms and 80ms respectively */
+        I915_WRITE(RCBMAXAVG, 90000);
+        I915_WRITE(RCBMINAVG, 80000);
+        I915_WRITE(MEMIHYST, 1);
+        /* Set up min, max, and cur for interrupt handling */
+        fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
+        fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
+        fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
+                MEMMODE_FSTART_SHIFT;
+        vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
+                PXVFREQ_PX_SHIFT;
+        dev_priv->max_delay = fstart; /* can't go to fmax w/o IPS */
+        dev_priv->min_delay = fmin;
+        dev_priv->cur_delay = fstart;
+        I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
+        /*
+         * Interrupts will be enabled in ironlake_irq_postinstall
+         */
+        I915_WRITE(VIDSTART, vstart);
+        POSTING_READ(VIDSTART);
+        rgvmodectl |= MEMMODE_SWMODE_EN;
+        I915_WRITE(MEMMODECTL, rgvmodectl);
+        while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
+                if (i++ > 100) {
+                        DRM_ERROR("stuck trying to change perf mode\n");
+                        break;
+                }
+                msleep(1);
+        }
+        msleep(1);
+        rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
+                (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
+        I915_WRITE(MEMSWCTL, rgvswctl);
+        POSTING_READ(MEMSWCTL);
+        rgvswctl |= MEMCTL_CMD_STS;
+        I915_WRITE(MEMSWCTL, rgvswctl);
+}
+void ironlake_disable_drps(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 rgvswctl;
+        u8 fstart;
+        /* Ack interrupts, disable EFC interrupt */
+        I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
+        I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
+        I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
+        I915_WRITE(DEIIR, DE_PCU_EVENT);
+        I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
+        /* Go back to the starting frequency */
+        fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >>
+                MEMMODE_FSTART_SHIFT;
+        rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
+                (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
+        I915_WRITE(MEMSWCTL, rgvswctl);
+        msleep(1);
+        rgvswctl |= MEMCTL_CMD_STS;
+        I915_WRITE(MEMSWCTL, rgvswctl);
+        msleep(1);
+}
 void intel_init_clock_gating(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4579,42 +4760,27 @@ void intel_init_clock_gating(struct drm_device *dev)
         * GPU can automatically power down the render unit if given a page
         * to save state.
         */
-        if (I915_HAS_RC6(dev)) {
+        if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
-                struct drm_gem_object *pwrctx;
+                struct drm_i915_gem_object *obj_priv = NULL;
-                struct drm_i915_gem_object *obj_priv;
-                int ret;
                if (dev_priv->pwrctx) {
                        obj_priv = dev_priv->pwrctx->driver_private;
                } else {
-                        pwrctx = drm_gem_object_alloc(dev, 4096);
+                        struct drm_gem_object *pwrctx;
-                        if (!pwrctx) {
-                                DRM_DEBUG("failed to alloc power context, "
-                                          "RC6 disabled\n");
-                                goto out;
-                        }
-                        ret = i915_gem_object_pin(pwrctx, 4096);
+                        pwrctx = intel_alloc_power_context(dev);
-                        if (ret) {
+                        if (pwrctx) {
-                                DRM_ERROR("failed to pin power context: %d\n",
+                                dev_priv->pwrctx = pwrctx;
-                                          ret);
+                                obj_priv = pwrctx->driver_private;
-                                drm_gem_object_unreference(pwrctx);
-                                goto out;
                        }
-                        i915_gem_object_set_to_gtt_domain(pwrctx, 1);
-                        dev_priv->pwrctx = pwrctx;
-                        obj_priv = pwrctx->driver_private;
                }
-                I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
+                if (obj_priv) {
-                I915_WRITE(MCHBAR_RENDER_STANDBY,
+                        I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
-                           I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
+                        I915_WRITE(MCHBAR_RENDER_STANDBY,
+                                   I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
+                }
        }
-out:
-        return;
 }
 /* Set up chip specific display functions */
@@ -4725,11 +4891,6 @@ void intel_modeset_init(struct drm_device *dev)
        DRM_DEBUG_KMS("%d display pipe%s available.\n",
                  num_pipe, num_pipe > 1 ? "s" : "");
-        if (IS_I85X(dev))
-                pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
-        else if (IS_I9XX(dev) || IS_G4X(dev))
-                pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
        for (i = 0; i < num_pipe; i++) {
                intel_crtc_init(dev, i);
        }
@@ -4738,6 +4899,9 @@ void intel_modeset_init(struct drm_device *dev)
        intel_init_clock_gating(dev);
+        if (IS_IRONLAKE_M(dev))
+                ironlake_enable_drps(dev);
        INIT_WORK(&dev_priv->idle_work, intel_idle_update);
        setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
                    (unsigned long)dev);
@@ -4770,7 +4934,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
                del_timer_sync(&intel_crtc->idle_timer);
        }
-        intel_increase_renderclock(dev, false);
        del_timer_sync(&dev_priv->idle_timer);
        if (dev_priv->display.disable_fbc)
@@ -4786,6 +4949,9 @@ void intel_modeset_cleanup(struct drm_device *dev)
                drm_gem_object_unreference(dev_priv->pwrctx);
        }
+        if (IS_IRONLAKE_M(dev))
+                ironlake_disable_drps(dev);
        mutex_unlock(&dev->struct_mutex);
        drm_mode_config_cleanup(dev);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4e7aa8b7b938..439506cefc14 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -125,9 +125,15 @@ intel_dp_link_clock(uint8_t link_bw)
 /* I think this is a fiction */
 static int
-intel_dp_link_required(int pixel_clock)
+intel_dp_link_required(struct drm_device *dev,
+                       struct intel_output *intel_output, int pixel_clock)
 {
-        return pixel_clock * 3;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        if (IS_eDP(intel_output))
+                return (pixel_clock * dev_priv->edp_bpp) / 8;
+        else
+                return pixel_clock * 3;
 }
 static int
@@ -138,7 +144,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
        int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output));
        int max_lanes = intel_dp_max_lane_count(intel_output);
-        if (intel_dp_link_required(mode->clock) > max_link_clock * max_lanes)
+        if (intel_dp_link_required(connector->dev, intel_output, mode->clock)
+                        > max_link_clock * max_lanes)
                return MODE_CLOCK_HIGH;
        if (mode->clock < 10000)
@@ -492,7 +499,8 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
                for (clock = 0; clock <= max_clock; clock++) {
                        int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
-                        if (intel_dp_link_required(mode->clock) <= link_avail) {
+                        if (intel_dp_link_required(encoder->dev, intel_output, mode->clock)
+                                        <= link_avail) {
                                dp_priv->link_bw = bws[clock];
                                dp_priv->lane_count = lane_count;
                                adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
@@ -1289,53 +1297,7 @@ intel_dp_hot_plug(struct intel_output *intel_output)
        if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
                intel_dp_check_link_status(intel_output);
 }
-/*
- * Enumerate the child dev array parsed from VBT to check whether
- * the given DP is present.
- * If it is present, return 1.
- * If it is not present, return false.
- * If no child dev is parsed from VBT, it is assumed that the given
- * DP is present.
- */
-static int dp_is_present_in_vbt(struct drm_device *dev, int dp_reg)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        struct child_device_config *p_child;
-        int i, dp_port, ret;
-        if (!dev_priv->child_dev_num)
-                return 1;
-        dp_port = 0;
-        if (dp_reg == DP_B || dp_reg == PCH_DP_B)
-                dp_port = PORT_IDPB;
-        else if (dp_reg == DP_C || dp_reg == PCH_DP_C)
-                dp_port = PORT_IDPC;
-        else if (dp_reg == DP_D || dp_reg == PCH_DP_D)
-                dp_port = PORT_IDPD;
-        ret = 0;
-        for (i = 0; i < dev_priv->child_dev_num; i++) {
-                p_child = dev_priv->child_dev + i;
-                /*
-                 * If the device type is not DP, continue.
-                 */
-                if (p_child->device_type != DEVICE_TYPE_DP &&
-                        p_child->device_type != DEVICE_TYPE_eDP)
-                        continue;
-                /* Find the eDP port */
-                if (dp_reg == DP_A && p_child->device_type == DEVICE_TYPE_eDP) {
-                        ret = 1;
-                        break;
-                }
-                /* Find the DP port */
-                if (p_child->dvo_port == dp_port) {
-                        ret = 1;
-                        break;
-                }
-        }
-        return ret;
-}
 void
 intel_dp_init(struct drm_device *dev, int output_reg)
 {
@@ -1345,10 +1307,6 @@ intel_dp_init(struct drm_device *dev, int output_reg)
        struct intel_dp_priv *dp_priv;
        const char *name = NULL;
-        if (!dp_is_present_in_vbt(dev, output_reg)) {
-                DRM_DEBUG_KMS("DP is not present. Ignore it\n");
-                return;
-        }
        intel_output = kcalloc(sizeof(struct intel_output) + 
                               sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
        if (!intel_output)
@@ -1373,11 +1331,10 @@ intel_dp_init(struct drm_device *dev, int output_reg)
        else if (output_reg == DP_D || output_reg == PCH_DP_D)
                intel_output->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
-        if (IS_eDP(intel_output)) {
+        if (IS_eDP(intel_output))
-                intel_output->crtc_mask = (1 << 1);
                intel_output->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
-        } else
-                intel_output->crtc_mask = (1 << 0) | (1 << 1);
+        intel_output->crtc_mask = (1 << 0) | (1 << 1);
        connector->interlace_allowed = true;
        connector->doublescan_allowed = 0;
@@ -1402,14 +1359,20 @@ intel_dp_init(struct drm_device *dev, int output_reg)
                        break;
                case DP_B:
                case PCH_DP_B:
+                        dev_priv->hotplug_supported_mask |=
+                                HDMIB_HOTPLUG_INT_STATUS;
                        name = "DPDDC-B";
                        break;
                case DP_C:
                case PCH_DP_C:
+                        dev_priv->hotplug_supported_mask |=
+                                HDMIC_HOTPLUG_INT_STATUS;
                        name = "DPDDC-C";
                        break;
                case DP_D:
                case PCH_DP_D:
+                        dev_priv->hotplug_supported_mask |=
+                                HDMID_HOTPLUG_INT_STATUS;
                        name = "DPDDC-D";
                        break;
        }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a51573da1ff6..3a467ca57857 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -209,6 +209,8 @@ extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
                                    u16 *blue, int regno);
 extern void intel_init_clock_gating(struct drm_device *dev);
+extern void ironlake_enable_drps(struct drm_device *dev);
+extern void ironlake_disable_drps(struct drm_device *dev);
 extern int intel_framebuffer_create(struct drm_device *dev,
                                    struct drm_mode_fb_cmd *mode_cmd,
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index d4823cc87895..aaabbcbe5905 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -70,7 +70,7 @@ static struct drm_fb_helper_funcs intel_fb_helper_funcs = {
 /**
- * Curretly it is assumed that the old framebuffer is reused.
+ * Currently it is assumed that the old framebuffer is reused.
 *
 * LOCKING
 * caller should hold the mode config lock.
@@ -148,7 +148,7 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
        mutex_lock(&dev->struct_mutex);
-        ret = i915_gem_object_pin(fbo, PAGE_SIZE);
+        ret = i915_gem_object_pin(fbo, 64*1024);
        if (ret) {
                DRM_ERROR("failed to pin fb: %d\n", ret);
                goto out_unref;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f04dbbe7d400..0e268deed761 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -225,52 +225,6 @@ static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
        .destroy = intel_hdmi_enc_destroy,
 };
-/*
- * Enumerate the child dev array parsed from VBT to check whether
- * the given HDMI is present.
- * If it is present, return 1.
- * If it is not present, return false.
- * If no child dev is parsed from VBT, it assumes that the given
- * HDMI is present.
- */
-static int hdmi_is_present_in_vbt(struct drm_device *dev, int hdmi_reg)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        struct child_device_config *p_child;
-        int i, hdmi_port, ret;
-        if (!dev_priv->child_dev_num)
-                return 1;
-        if (hdmi_reg == SDVOB)
-                hdmi_port = DVO_B;
-        else if (hdmi_reg == SDVOC)
-                hdmi_port = DVO_C;
-        else if (hdmi_reg == HDMIB)
-                hdmi_port = DVO_B;
-        else if (hdmi_reg == HDMIC)
-                hdmi_port = DVO_C;
-        else if (hdmi_reg == HDMID)
-                hdmi_port = DVO_D;
-        else
-                return 0;
-        ret = 0;
-        for (i = 0; i < dev_priv->child_dev_num; i++) {
-                p_child = dev_priv->child_dev + i;
-                /*
-                 * If the device type is not HDMI, continue.
-                 */
-                if (p_child->device_type != DEVICE_TYPE_HDMI)
-                        continue;
-                /* Find the HDMI port */
-                if (p_child->dvo_port == hdmi_port) {
-                        ret = 1;
-                        break;
-                }
-        }
-        return ret;
-}
 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
@@ -278,10 +232,6 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
        struct intel_output *intel_output;
        struct intel_hdmi_priv *hdmi_priv;
-        if (!hdmi_is_present_in_vbt(dev, sdvox_reg)) {
-                DRM_DEBUG_KMS("HDMI is not present. Ignored it \n");
-                return;
-        }
        intel_output = kcalloc(sizeof(struct intel_output) +
                               sizeof(struct intel_hdmi_priv), 1, GFP_KERNEL);
        if (!intel_output)
@@ -303,21 +253,26 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
        if (sdvox_reg == SDVOB) {
                intel_output->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
                intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "HDMIB");
+                dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
        } else if (sdvox_reg == SDVOC) {
                intel_output->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
                intel_output->ddc_bus = intel_i2c_create(dev, GPIOD, "HDMIC");
+                dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
        } else if (sdvox_reg == HDMIB) {
                intel_output->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
                intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOE,
                                                                "HDMIB");
+                dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
        } else if (sdvox_reg == HDMIC) {
                intel_output->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
                intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOD,
                                                                "HDMIC");
+                dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
        } else if (sdvox_reg == HDMID) {
                intel_output->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
                intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOF,
                                                                "HDMID");
+                dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
        }
        if (!intel_output->ddc_bus)
                goto err_connector;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index b04d1e63d439..93031a75d112 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -602,12 +602,47 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
 /* Some lid devices report incorrect lid status, assume they're connected */
 static const struct dmi_system_id bad_lid_status[] = {
        {
+                .ident = "Compaq nx9020",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
+                        DMI_MATCH(DMI_BOARD_NAME, "3084"),
+                },
+        },
+        {
+                .ident = "Samsung SX20S",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
+                        DMI_MATCH(DMI_BOARD_NAME, "SX20S"),
+                },
+        },
+        {
                .ident = "Aspire One",
                .matches = {
                        DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
                        DMI_MATCH(DMI_PRODUCT_NAME, "Aspire one"),
                },
        },
+        {
+                .ident = "Aspire 1810T",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 1810T"),
+                },
+        },
+        {
+                .ident = "PC-81005",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "MALATA"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "PC-81005"),
+                },
+        },
+        {
+                .ident = "Clevo M5x0N",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "CLEVO Co."),
+                        DMI_MATCH(DMI_BOARD_NAME, "M5x0N"),
+                },
+        },
        { }
 };
@@ -620,9 +655,16 @@ static const struct dmi_system_id bad_lid_status[] = {
 */
 static enum drm_connector_status intel_lvds_detect(struct drm_connector *connector)
 {
+        struct drm_device *dev = connector->dev;
        enum drm_connector_status status = connector_status_connected;
-        if (!acpi_lid_open() && !dmi_check_system(bad_lid_status))
+        /* ACPI lid methods were generally unreliable in this generation, so
+         * don't even bother.
+         */
+        if (IS_I8XX(dev))
+                return connector_status_connected;
+        if (!dmi_check_system(bad_lid_status) && !acpi_lid_open())
                status = connector_status_disconnected;
        return status;
@@ -679,7 +721,14 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
        struct drm_i915_private *dev_priv =
                container_of(nb, struct drm_i915_private, lid_notifier);
        struct drm_device *dev = dev_priv->dev;
+        struct drm_connector *connector = dev_priv->int_lvds_connector;
+        /*
+         * check and update the status of LVDS connector after receiving
+         * the LID nofication event.
+         */
+        if (connector)
+                connector->status = connector->funcs->detect(connector);
        if (!acpi_lid_open()) {
                dev_priv->modeset_on_lid = 1;
                return NOTIFY_OK;
@@ -854,65 +903,6 @@ static const struct dmi_system_id intel_no_lvds[] = {
        { }     /* terminating entry */
 };
-#ifdef CONFIG_ACPI
-/*
- * check_lid_device -- check whether @handle is an ACPI LID device.
- * @handle: ACPI device handle
- * @level : depth in the ACPI namespace tree
- * @context: the number of LID device when we find the device
- * @rv: a return value to fill if desired (Not use)
- */
-static acpi_status
-check_lid_device(acpi_handle handle, u32 level, void *context,
-                        void **return_value)
-{
-        struct acpi_device *acpi_dev;
-        int *lid_present = context;
-        acpi_dev = NULL;
-        /* Get the acpi device for device handle */
-        if (acpi_bus_get_device(handle, &acpi_dev) || !acpi_dev) {
-                /* If there is no ACPI device for handle, return */
-                return AE_OK;
-        }
-        if (!strncmp(acpi_device_hid(acpi_dev), "PNP0C0D", 7))
-                *lid_present = 1;
-        return AE_OK;
-}
-/**
- * check whether there exists the ACPI LID device by enumerating the ACPI
- * device tree.
- */
-static int intel_lid_present(void)
-{
-        int lid_present = 0;
-        if (acpi_disabled) {
-                /* If ACPI is disabled, there is no ACPI device tree to
-                 * check, so assume the LID device would have been present.
-                 */
-                return 1;
-        }
-        acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
-                                ACPI_UINT32_MAX,
-                                check_lid_device, &lid_present, NULL);
-        return lid_present;
-}
-#else
-static int intel_lid_present(void)
-{
-        /* In the absence of ACPI built in, assume that the LID device would
-         * have been present.
-         */
-        return 1;
-}
-#endif
 /**
 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
 * @dev: drm device
@@ -957,7 +947,8 @@ static void intel_find_lvds_downclock(struct drm_device *dev,
                }
        }
        mutex_unlock(&dev->mode_config.mutex);
-        if (temp_downclock < panel_fixed_mode->clock) {
+        if (temp_downclock < panel_fixed_mode->clock &&
+            i915_lvds_downclock) {
                /* We found the downclock for LVDS. */
                dev_priv->lvds_downclock_avail = 1;
                dev_priv->lvds_downclock = temp_downclock;
@@ -1031,12 +1022,8 @@ void intel_lvds_init(struct drm_device *dev)
        if (dmi_check_system(intel_no_lvds))
                return;
-        /*
+        if (!lvds_is_present_in_vbt(dev)) {
-         * Assume LVDS is present if there's an ACPI lid device or if the
+                DRM_DEBUG_KMS("LVDS is not present in VBT\n");
-         * device is present in the VBT.
-         */
-        if (!lvds_is_present_in_vbt(dev) && !intel_lid_present()) {
-                DRM_DEBUG_KMS("LVDS is not present in VBT and no lid detected\n");
                return;
        }
@@ -1180,6 +1167,8 @@ out:
                DRM_DEBUG_KMS("lid notifier registration failed\n");
                dev_priv->lid_notifier.notifier_call = NULL;
        }
+        /* keep the LVDS connector */
+        dev_priv->int_lvds_connector = connector;
        drm_sysfs_connector_add(connector);
        return;
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 2639591c72e9..c3fa406912b3 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -199,16 +199,11 @@ static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_over
 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay)
 {
-        struct drm_device *dev = overlay->dev;
-        drm_i915_private_t *dev_priv = dev->dev_private;
        if (OVERLAY_NONPHYSICAL(overlay->dev))
                io_mapping_unmap_atomic(overlay->virt_addr);
        overlay->virt_addr = NULL;
-        I915_READ(OVADD); /* flush wc cashes */
        return;
 }
@@ -225,9 +220,7 @@ static int intel_overlay_on(struct intel_overlay *overlay)
        overlay->active = 1;
        overlay->hw_wedged = NEEDS_WAIT_FOR_FLIP;
-        BEGIN_LP_RING(6);
+        BEGIN_LP_RING(4);
-        OUT_RING(MI_FLUSH);
-        OUT_RING(MI_NOOP);
        OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
        OUT_RING(overlay->flip_addr | OFC_UPDATE);
        OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
@@ -267,9 +260,7 @@ static void intel_overlay_continue(struct intel_overlay *overlay,
        if (tmp & (1 << 17))
                DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
-        BEGIN_LP_RING(4);
+        BEGIN_LP_RING(2);
-        OUT_RING(MI_FLUSH);
-        OUT_RING(MI_NOOP);
        OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
        OUT_RING(flip_addr);
        ADVANCE_LP_RING();
@@ -338,9 +329,7 @@ static int intel_overlay_off(struct intel_overlay *overlay)
        /* wait for overlay to go idle */
        overlay->hw_wedged = SWITCH_OFF_STAGE_1;
-        BEGIN_LP_RING(6);
+        BEGIN_LP_RING(4);
-        OUT_RING(MI_FLUSH);
-        OUT_RING(MI_NOOP);
        OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
        OUT_RING(flip_addr);
        OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
@@ -358,9 +347,7 @@ static int intel_overlay_off(struct intel_overlay *overlay)
        /* turn overlay off */
        overlay->hw_wedged = SWITCH_OFF_STAGE_2;
-        BEGIN_LP_RING(6);
+        BEGIN_LP_RING(4);
-        OUT_RING(MI_FLUSH);
-        OUT_RING(MI_NOOP);
        OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
        OUT_RING(flip_addr);
        OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
@@ -435,9 +422,7 @@ int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
                        overlay->hw_wedged = SWITCH_OFF_STAGE_2;
-                        BEGIN_LP_RING(6);
+                        BEGIN_LP_RING(4);
-                        OUT_RING(MI_FLUSH);
-                        OUT_RING(MI_NOOP);
                        OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
                        OUT_RING(flip_addr);
                        OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
@@ -1179,7 +1164,7 @@ int intel_overlay_put_image(struct drm_device *dev, void *data,
 out_unlock:
        mutex_unlock(&dev->struct_mutex);
        mutex_unlock(&dev->mode_config.mutex);
-        drm_gem_object_unreference(new_bo);
+        drm_gem_object_unreference_unlocked(new_bo);
        kfree(params);
        return ret;
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index dba5147f4064..82678d30ab06 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -462,14 +462,63 @@ static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
 }
 /**
- * Don't check status code from this as it switches the bus back to the
+ * Try to read the response after issuie the DDC switch command. But it
- * SDVO chips which defeats the purpose of doing a bus switch in the first
+ * is noted that we must do the action of reading response and issuing DDC
- * place.
+ * switch command in one I2C transaction. Otherwise when we try to start
+ * another I2C transaction after issuing the DDC bus switch, it will be
+ * switched to the internal SDVO register.
 */
 static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
                                              u8 target)
 {
-        intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
+        struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
+        u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
+        struct i2c_msg msgs[] = {
+                {
+                        .addr = sdvo_priv->slave_addr >> 1,
+                        .flags = 0,
+                        .len = 2,
+                        .buf = out_buf,
+                },
+                /* the following two are to read the response */
+                {
+                        .addr = sdvo_priv->slave_addr >> 1,
+                        .flags = 0,
+                        .len = 1,
+                        .buf = cmd_buf,
+                },
+                {
+                        .addr = sdvo_priv->slave_addr >> 1,
+                        .flags = I2C_M_RD,
+                        .len = 1,
+                        .buf = ret_value,
+                },
+        };
+        intel_sdvo_debug_write(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
+                                        &target, 1);
+        /* write the DDC switch command argument */
+        intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0, target);
+        out_buf[0] = SDVO_I2C_OPCODE;
+        out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
+        cmd_buf[0] = SDVO_I2C_CMD_STATUS;
+        cmd_buf[1] = 0;
+        ret_value[0] = 0;
+        ret_value[1] = 0;
+        ret = i2c_transfer(intel_output->i2c_bus, msgs, 3);
+        if (ret != 3) {
+                /* failure in I2C transfer */
+                DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
+                return;
+        }
+        if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
+                DRM_DEBUG_KMS("DDC switch command returns response %d\n",
+                                        ret_value[0]);
+                return;
+        }
+        return;
 }
 static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
@@ -1579,6 +1628,32 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
        edid = drm_get_edid(&intel_output->base,
                            intel_output->ddc_bus);
+        /* This is only applied to SDVO cards with multiple outputs */
+        if (edid == NULL && intel_sdvo_multifunc_encoder(intel_output)) {
+                uint8_t saved_ddc, temp_ddc;
+                saved_ddc = sdvo_priv->ddc_bus;
+                temp_ddc = sdvo_priv->ddc_bus >> 1;
+                /*
+                 * Don't use the 1 as the argument of DDC bus switch to get
+                 * the EDID. It is used for SDVO SPD ROM.
+                 */
+                while(temp_ddc > 1) {
+                        sdvo_priv->ddc_bus = temp_ddc;
+                        edid = drm_get_edid(&intel_output->base,
+                                intel_output->ddc_bus);
+                        if (edid) {
+                                /*
+                                 * When we can get the EDID, maybe it is the
+                                 * correct DDC bus. Update it.
+                                 */
+                                sdvo_priv->ddc_bus = temp_ddc;
+                                break;
+                        }
+                        temp_ddc >>= 1;
+                }
+                if (edid == NULL)
+                        sdvo_priv->ddc_bus = saved_ddc;
+        }
        /* when there is no edid and no monitor is connected with VGA
         * port, try to use the CRT ddc to read the EDID for DVI-connector
         */
@@ -2270,6 +2345,14 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
                connector->connector_type = DRM_MODE_CONNECTOR_VGA;
                intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
                                        (1 << INTEL_ANALOG_CLONE_BIT);
+        } else if (flags & SDVO_OUTPUT_CVBS0) {
+                sdvo_priv->controlled_output = SDVO_OUTPUT_CVBS0;
+                encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
+                connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
+                sdvo_priv->is_tv = true;
+                intel_output->needs_tv_clock = true;
+                intel_output->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
        } else if (flags & SDVO_OUTPUT_LVDS0) {
                sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
@@ -2662,6 +2745,7 @@ static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
 bool intel_sdvo_init(struct drm_device *dev, int output_device)
 {
+        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_connector *connector;
        struct intel_output *intel_output;
        struct intel_sdvo_priv *sdvo_priv;
@@ -2708,10 +2792,12 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
                intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
                sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
                                                "SDVOB/VGA DDC BUS");
+                dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
        } else {
                intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
                sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
                                                "SDVOC/VGA DDC BUS");
+                dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
        }
        if (intel_output->ddc_bus == NULL)
@@ -2720,7 +2806,7 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
        /* Wrap with our custom algo which switches to DDC mode */
        intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
-        /* In defaut case sdvo lvds is false */
+        /* In default case sdvo lvds is false */
        intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
        if (intel_sdvo_output_setup(intel_output,
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index 1cf488247a16..48227e744753 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -90,21 +90,21 @@ int nouveau_hybrid_setup(struct drm_device *dev)
 {
        int result;
-        if (nouveau_dsm(dev, NOUVEAU_DSM_ACTIVE, NOUVEAU_DSM_ACTIVE_QUERY,
+        if (nouveau_dsm(dev, NOUVEAU_DSM_POWER, NOUVEAU_DSM_POWER_STATE,
                                                                &result))
                return -ENODEV;
        NV_INFO(dev, "_DSM hardware status gave 0x%x\n", result);
-        if (result & 0x1) {     /* Stamina mode - disable the external GPU */
+        if (result) { /* Ensure that the external GPU is enabled */
+                nouveau_dsm(dev, NOUVEAU_DSM_LED, NOUVEAU_DSM_LED_SPEED, NULL);
+                nouveau_dsm(dev, NOUVEAU_DSM_POWER, NOUVEAU_DSM_POWER_SPEED,
+                                                                        NULL);
+        } else { /* Stamina mode - disable the external GPU */
                nouveau_dsm(dev, NOUVEAU_DSM_LED, NOUVEAU_DSM_LED_STAMINA,
                                                                        NULL);
                nouveau_dsm(dev, NOUVEAU_DSM_POWER, NOUVEAU_DSM_POWER_STAMINA,
                                                                        NULL);
-        } else {                /* Ensure that the external GPU is enabled */
-                nouveau_dsm(dev, NOUVEAU_DSM_LED, NOUVEAU_DSM_LED_SPEED, NULL);
-                nouveau_dsm(dev, NOUVEAU_DSM_POWER, NOUVEAU_DSM_POWER_SPEED,
-                                                                        NULL);
        }
        return 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index d7f8d8b4a4b8..0e9cd1d49130 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -1865,7 +1865,7 @@ init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
        struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
-        if (dev_priv->card_type >= NV_50)
+        if (dev_priv->card_type >= NV_40)
                return 1;
        /*
@@ -3765,7 +3765,6 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
         */
        struct drm_nouveau_private *dev_priv = dev->dev_private;
-        struct init_exec iexec = {true, false};
        struct nvbios *bios = &dev_priv->VBIOS;
        uint8_t *table = &bios->data[bios->display.script_table_ptr];
        uint8_t *otable = NULL;
@@ -3845,8 +3844,6 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
                }
        }
-        bios->display.output = dcbent;
        if (pxclk == 0) {
                script = ROM16(otable[6]);
                if (!script) {
@@ -3855,7 +3852,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
                }
                NV_TRACE(dev, "0x%04X: parsing output script 0\n", script);
-                parse_init_table(bios, script, &iexec);
+                nouveau_bios_run_init_table(dev, script, dcbent);
        } else
        if (pxclk == -1) {
                script = ROM16(otable[8]);
@@ -3865,7 +3862,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
                }
                NV_TRACE(dev, "0x%04X: parsing output script 1\n", script);
-                parse_init_table(bios, script, &iexec);
+                nouveau_bios_run_init_table(dev, script, dcbent);
        } else
        if (pxclk == -2) {
                if (table[4] >= 12)
@@ -3878,7 +3875,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
                }
                NV_TRACE(dev, "0x%04X: parsing output script 2\n", script);
-                parse_init_table(bios, script, &iexec);
+                nouveau_bios_run_init_table(dev, script, dcbent);
        } else
        if (pxclk > 0) {
                script = ROM16(otable[table[4] + i*6 + 2]);
@@ -3890,7 +3887,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
                }
                NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script);
-                parse_init_table(bios, script, &iexec);
+                nouveau_bios_run_init_table(dev, script, dcbent);
        } else
        if (pxclk < 0) {
                script = ROM16(otable[table[4] + i*6 + 4]);
@@ -3902,7 +3899,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
                }
                NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script);
-                parse_init_table(bios, script, &iexec);
+                nouveau_bios_run_init_table(dev, script, dcbent);
        }
        return 0;
@@ -5865,9 +5862,11 @@ nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
        struct nvbios *bios = &dev_priv->VBIOS;
        struct init_exec iexec = { true, false };
+        mutex_lock(&bios->lock);
        bios->display.output = dcbent;
        parse_init_table(bios, table, &iexec);
        bios->display.output = NULL;
+        mutex_unlock(&bios->lock);
 }
 static bool NVInitVBIOS(struct drm_device *dev)
@@ -5876,6 +5875,7 @@ static bool NVInitVBIOS(struct drm_device *dev)
        struct nvbios *bios = &dev_priv->VBIOS;
        memset(bios, 0, sizeof(struct nvbios));
+        mutex_init(&bios->lock);
        bios->dev = dev;
        if (!NVShadowVBIOS(dev, bios->data))
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h
index 058e98c76d89..fd94bd6dc264 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h
@@ -205,6 +205,8 @@ struct nvbios {
        struct drm_device *dev;
        struct nouveau_bios_info pub;
+        struct mutex lock;
        uint8_t data[NV_PROM_SIZE];
        unsigned int length;
        bool execute;
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index db0ed4c13f98..028719fddf76 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -65,8 +65,10 @@ nouveau_bo_fixup_align(struct drm_device *dev,
        /*
         * Some of the tile_flags have a periodic structure of N*4096 bytes,
-         * align to to that as well as the page size. Overallocate memory to
+         * align to to that as well as the page size. Align the size to the
-         * avoid corruption of other buffer objects.
+         * appropriate boundaries. This does imply that sizes are rounded up
+         * 3-7 pages, so be aware of this and do not waste memory by allocating
+         * many small buffers.
         */
        if (dev_priv->card_type == NV_50) {
                uint32_t block_size = nouveau_mem_fb_amount(dev) >> 15;
@@ -77,22 +79,20 @@ nouveau_bo_fixup_align(struct drm_device *dev,
                case 0x2800:
                case 0x4800:
                case 0x7a00:
-                        *size = roundup(*size, block_size);
                        if (is_power_of_2(block_size)) {
-                                *size += 3 * block_size;
                                for (i = 1; i < 10; i++) {
                                        *align = 12 * i * block_size;
                                        if (!(*align % 65536))
                                                break;
                                }
                        } else {
-                                *size += 6 * block_size;
                                for (i = 1; i < 10; i++) {
                                        *align = 8 * i * block_size;
                                        if (!(*align % 65536))
                                                break;
                                }
                        }
+                        *size = roundup(*size, *align);
                        break;
                default:
                        break;
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 343d718a9667..2281f99da7fc 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -278,12 +278,11 @@ nouveau_channel_free(struct nouveau_channel *chan)
        /* Ensure the channel is no longer active on the GPU */
        pfifo->reassign(dev, false);
-        if (pgraph->channel(dev) == chan) {
+        pgraph->fifo_access(dev, false);
-                pgraph->fifo_access(dev, false);
+        if (pgraph->channel(dev) == chan)
                pgraph->unload_context(dev);
-                pgraph->fifo_access(dev, true);
-        }
        pgraph->destroy_context(chan);
+        pgraph->fifo_access(dev, true);
        if (pfifo->channel_id(dev) == chan->id) {
                pfifo->disable(dev);
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 7e6d673f3a23..d2f63353ea97 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -88,13 +88,14 @@ nouveau_connector_destroy(struct drm_connector *drm_connector)
 {
        struct nouveau_connector *nv_connector =
                nouveau_connector(drm_connector);
-        struct drm_device *dev = nv_connector->base.dev;
+        struct drm_device *dev;
-        NV_DEBUG_KMS(dev, "\n");
        if (!nv_connector)
                return;
+        dev = nv_connector->base.dev;
+        NV_DEBUG_KMS(dev, "\n");
        kfree(nv_connector->edid);
        drm_sysfs_connector_remove(drm_connector);
        drm_connector_cleanup(drm_connector);
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index dfc94391d71e..cf1c5c0a0abe 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -39,11 +39,8 @@ nouveau_user_framebuffer_destroy(struct drm_framebuffer *drm_fb)
        if (drm_fb->fbdev)
                nouveau_fbcon_remove(dev, drm_fb);
-        if (fb->nvbo) {
+        if (fb->nvbo)
-                mutex_lock(&dev->struct_mutex);
+                drm_gem_object_unreference_unlocked(fb->nvbo->gem);
-                drm_gem_object_unreference(fb->nvbo->gem);
-                mutex_unlock(&dev->struct_mutex);
-        }
        drm_framebuffer_cleanup(drm_fb);
        kfree(fb);
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c
index dd4937224220..f954ad93e81f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -502,12 +502,12 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
                        break;
        }
-        if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) {
-                ret = -EREMOTEIO;
-                goto out;
-        }
        if (cmd & 1) {
+                if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) {
+                        ret = -EREMOTEIO;
+                        goto out;
+                }
                for (i = 0; i < 4; i++) {
                        data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i));
                        NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c
index 343ab7f17ccc..da3b93b84502 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.c
@@ -56,7 +56,7 @@ int nouveau_vram_pushbuf;
 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
 MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
-int nouveau_vram_notify;
+int nouveau_vram_notify = 1;
 module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
 MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
@@ -75,6 +75,14 @@ MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
 int nouveau_ignorelid = 0;
 module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
+MODULE_PARM_DESC(noagp, "Disable all acceleration");
+int nouveau_noaccel = 0;
+module_param_named(noaccel, nouveau_noaccel, int, 0400);
+MODULE_PARM_DESC(noagp, "Disable fbcon acceleration");
+int nouveau_nofbaccel = 0;
+module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
 MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
                 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
                 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 6b9690418bc7..1c15ef37b71c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -583,6 +583,7 @@ struct drm_nouveau_private {
        uint64_t vm_end;
        struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
        int vm_vram_pt_nr;
+        uint64_t vram_sys_base;
        /* the mtrr covering the FB */
        int fb_mtrr;
@@ -678,6 +679,8 @@ extern int nouveau_reg_debug;
 extern char *nouveau_vbios;
 extern int nouveau_ctxfw;
 extern int nouveau_ignorelid;
+extern int nouveau_nofbaccel;
+extern int nouveau_noaccel;
 /* nouveau_state.c */
 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 0b05c869e0e7..d48c59cdefe4 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -107,6 +107,34 @@ static struct fb_ops nouveau_fbcon_ops = {
        .fb_setcmap = drm_fb_helper_setcmap,
 };
+static struct fb_ops nv04_fbcon_ops = {
+        .owner = THIS_MODULE,
+        .fb_check_var = drm_fb_helper_check_var,
+        .fb_set_par = drm_fb_helper_set_par,
+        .fb_setcolreg = drm_fb_helper_setcolreg,
+        .fb_fillrect = nv04_fbcon_fillrect,
+        .fb_copyarea = nv04_fbcon_copyarea,
+        .fb_imageblit = nv04_fbcon_imageblit,
+        .fb_sync = nouveau_fbcon_sync,
+        .fb_pan_display = drm_fb_helper_pan_display,
+        .fb_blank = drm_fb_helper_blank,
+        .fb_setcmap = drm_fb_helper_setcmap,
+};
+static struct fb_ops nv50_fbcon_ops = {
+        .owner = THIS_MODULE,
+        .fb_check_var = drm_fb_helper_check_var,
+        .fb_set_par = drm_fb_helper_set_par,
+        .fb_setcolreg = drm_fb_helper_setcolreg,
+        .fb_fillrect = nv50_fbcon_fillrect,
+        .fb_copyarea = nv50_fbcon_copyarea,
+        .fb_imageblit = nv50_fbcon_imageblit,
+        .fb_sync = nouveau_fbcon_sync,
+        .fb_pan_display = drm_fb_helper_pan_display,
+        .fb_blank = drm_fb_helper_blank,
+        .fb_setcmap = drm_fb_helper_setcmap,
+};
 static void nouveau_fbcon_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
                                    u16 blue, int regno)
 {
@@ -267,8 +295,12 @@ nouveau_fbcon_create(struct drm_device *dev, uint32_t fb_width,
        dev_priv->fbdev_info = info;
        strcpy(info->fix.id, "nouveaufb");
-        info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
+        if (nouveau_nofbaccel)
-                      FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_IMAGEBLIT;
+                info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_DISABLED;
+        else
+                info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
+                              FBINFO_HWACCEL_FILLRECT |
+                              FBINFO_HWACCEL_IMAGEBLIT;
        info->fbops = &nouveau_fbcon_ops;
        info->fix.smem_start = dev->mode_config.fb_base + nvbo->bo.offset -
                               dev_priv->vm_vram_base;
@@ -316,13 +348,15 @@ nouveau_fbcon_create(struct drm_device *dev, uint32_t fb_width,
        par->nouveau_fb = nouveau_fb;
        par->dev = dev;
-        if (dev_priv->channel) {
+        if (dev_priv->channel && !nouveau_nofbaccel) {
                switch (dev_priv->card_type) {
                case NV_50:
                        nv50_fbcon_accel_init(info);
+                        info->fbops = &nv50_fbcon_ops;
                        break;
                default:
                        nv04_fbcon_accel_init(info);
+                        info->fbops = &nv04_fbcon_ops;
                        break;
                };
        }
@@ -367,10 +401,8 @@ nouveau_fbcon_remove(struct drm_device *dev, struct drm_framebuffer *fb)
                unregister_framebuffer(info);
                nouveau_bo_unmap(nouveau_fb->nvbo);
-                mutex_lock(&dev->struct_mutex);
+                drm_gem_object_unreference_unlocked(nouveau_fb->nvbo->gem);
-                drm_gem_object_unreference(nouveau_fb->nvbo->gem);
                nouveau_fb->nvbo = NULL;
-                mutex_unlock(&dev->struct_mutex);
                if (par)
                        drm_fb_helper_free(&par->helper);
                framebuffer_release(info);
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.h b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
index 462e0b87b4bd..f9c34e1a8c11 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.h
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
@@ -40,7 +40,13 @@ int nouveau_fbcon_remove(struct drm_device *dev, struct drm_framebuffer *fb);
 void nouveau_fbcon_restore(void);
 void nouveau_fbcon_zfill(struct drm_device *dev);
+void nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region);
+void nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
+void nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image);
 int nv04_fbcon_accel_init(struct fb_info *info);
+void nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
+void nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region);
+void nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image);
 int nv50_fbcon_accel_init(struct fb_info *info);
 void nouveau_fbcon_gpu_lockup(struct fb_info *info);
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 6ac804b0c9f9..34063c561899 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -167,12 +167,10 @@ nouveau_gem_ioctl_new(struct drm_device *dev, void *data,
        ret = drm_gem_handle_create(file_priv, nvbo->gem, &req->info.handle);
 out:
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_handle_unreference_unlocked(nvbo->gem);
-        drm_gem_object_handle_unreference(nvbo->gem);
-        mutex_unlock(&dev->struct_mutex);
        if (ret)
-                drm_gem_object_unreference(nvbo->gem);
+                drm_gem_object_unreference_unlocked(nvbo->gem);
        return ret;
 }
@@ -865,9 +863,7 @@ nouveau_gem_ioctl_pin(struct drm_device *dev, void *data,
                req->domain = NOUVEAU_GEM_DOMAIN_VRAM;
 out:
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(gem);
-        drm_gem_object_unreference(gem);
-        mutex_unlock(&dev->struct_mutex);
        return ret;
 }
@@ -891,9 +887,7 @@ nouveau_gem_ioctl_unpin(struct drm_device *dev, void *data,
        ret = nouveau_bo_unpin(nouveau_gem_object(gem));
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(gem);
-        drm_gem_object_unreference(gem);
-        mutex_unlock(&dev->struct_mutex);
        return ret;
 }
@@ -925,7 +919,9 @@ nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data,
        }
        if (req->flags & NOUVEAU_GEM_CPU_PREP_NOBLOCK) {
+                spin_lock(&nvbo->bo.lock);
                ret = ttm_bo_wait(&nvbo->bo, false, false, no_wait);
+                spin_unlock(&nvbo->bo.lock);
        } else {
                ret = ttm_bo_synccpu_write_grab(&nvbo->bo, no_wait);
                if (ret == 0)
@@ -933,9 +929,7 @@ nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data,
        }
 out:
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(gem);
-        drm_gem_object_unreference(gem);
-        mutex_unlock(&dev->struct_mutex);
        return ret;
 }
@@ -963,9 +957,7 @@ nouveau_gem_ioctl_cpu_fini(struct drm_device *dev, void *data,
        ret = 0;
 out:
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(gem);
-        drm_gem_object_unreference(gem);
-        mutex_unlock(&dev->struct_mutex);
        return ret;
 }
@@ -984,9 +976,7 @@ nouveau_gem_ioctl_info(struct drm_device *dev, void *data,
                return -EINVAL;
        ret = nouveau_gem_info(gem, req);
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(gem);
-        drm_gem_object_unreference(gem);
-        mutex_unlock(&dev->struct_mutex);
        return ret;
 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_grctx.c b/drivers/gpu/drm/nouveau/nouveau_grctx.c
index 419f4c2b3b89..c7ebec696747 100644
--- a/drivers/gpu/drm/nouveau/nouveau_grctx.c
+++ b/drivers/gpu/drm/nouveau/nouveau_grctx.c
@@ -97,8 +97,8 @@ nouveau_grctx_prog_load(struct drm_device *dev)
                }
                pgraph->ctxvals = kmalloc(fw->size, GFP_KERNEL);
-                if (!pgraph->ctxprog) {
+                if (!pgraph->ctxvals) {
-                        NV_ERROR(dev, "OOM copying ctxprog\n");
+                        NV_ERROR(dev, "OOM copying ctxvals\n");
                        release_firmware(fw);
                        nouveau_grctx_fini(dev);
                        return -ENOMEM;
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c
index 3b9bad66162a..447f9f69d6b1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_irq.c
+++ b/drivers/gpu/drm/nouveau/nouveau_irq.c
@@ -211,6 +211,20 @@ nouveau_fifo_irq_handler(struct drm_device *dev)
                                                                get + 4);
                }
+                if (status & NV_PFIFO_INTR_SEMAPHORE) {
+                        uint32_t sem;
+                        status &= ~NV_PFIFO_INTR_SEMAPHORE;
+                        nv_wr32(dev, NV03_PFIFO_INTR_0,
+                                NV_PFIFO_INTR_SEMAPHORE);
+                        sem = nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE);
+                        nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
+                        nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
+                        nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
+                }
                if (status) {
                        NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n",
                                status, chid);
@@ -566,86 +580,99 @@ nouveau_pgraph_irq_handler(struct drm_device *dev)
 static void
 nv50_pgraph_irq_handler(struct drm_device *dev)
 {
-        uint32_t status, nsource;
+        uint32_t status;
-        status = nv_rd32(dev, NV03_PGRAPH_INTR);
+        while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
-        nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
+                uint32_t nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
-        if (status & 0x00000001) {
+                if (status & 0x00000001) {
-                nouveau_pgraph_intr_notify(dev, nsource);
+                        nouveau_pgraph_intr_notify(dev, nsource);
-                status &= ~0x00000001;
+                        status &= ~0x00000001;
-                nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001);
+                        nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001);
-        }
+                }
-        if (status & 0x00000010) {
+                if (status & 0x00000010) {
-                nouveau_pgraph_intr_error(dev, nsource |
+                        nouveau_pgraph_intr_error(dev, nsource |
-                                          NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD);
+                                        NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD);
-                status &= ~0x00000010;
+                        status &= ~0x00000010;
-                nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010);
+                        nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010);
-        }
+                }
-        if (status & 0x00001000) {
+                if (status & 0x00001000) {
-                nv_wr32(dev, 0x400500, 0x00000000);
+                        nv_wr32(dev, 0x400500, 0x00000000);
-                nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
+                        nv_wr32(dev, NV03_PGRAPH_INTR,
-                nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
+                                NV_PGRAPH_INTR_CONTEXT_SWITCH);
-                        NV40_PGRAPH_INTR_EN) & ~NV_PGRAPH_INTR_CONTEXT_SWITCH);
+                        nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
-                nv_wr32(dev, 0x400500, 0x00010001);
+                                NV40_PGRAPH_INTR_EN) &
+                                ~NV_PGRAPH_INTR_CONTEXT_SWITCH);
+                        nv_wr32(dev, 0x400500, 0x00010001);
-                nv50_graph_context_switch(dev);
+                        nv50_graph_context_switch(dev);
-                status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
+                        status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
-        }
+                }
-        if (status & 0x00100000) {
+                if (status & 0x00100000) {
-                nouveau_pgraph_intr_error(dev, nsource |
+                        nouveau_pgraph_intr_error(dev, nsource |
-                                          NV03_PGRAPH_NSOURCE_DATA_ERROR);
+                                        NV03_PGRAPH_NSOURCE_DATA_ERROR);
-                status &= ~0x00100000;
+                        status &= ~0x00100000;
-                nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000);
+                        nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000);
-        }
+                }
-        if (status & 0x00200000) {
+                if (status & 0x00200000) {
-                int r;
+                        int r;
-                nouveau_pgraph_intr_error(dev, nsource |
+                        nouveau_pgraph_intr_error(dev, nsource |
-                                          NV03_PGRAPH_NSOURCE_PROTECTION_ERROR);
+                                        NV03_PGRAPH_NSOURCE_PROTECTION_ERROR);
-                NV_ERROR(dev, "magic set 1:\n");
+                        NV_ERROR(dev, "magic set 1:\n");
-                for (r = 0x408900; r <= 0x408910; r += 4)
+                        for (r = 0x408900; r <= 0x408910; r += 4)
-                        NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, nv_rd32(dev, r));
+                                NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
-                nv_wr32(dev, 0x408900, nv_rd32(dev, 0x408904) | 0xc0000000);
+                                        nv_rd32(dev, r));
-                for (r = 0x408e08; r <= 0x408e24; r += 4)
+                        nv_wr32(dev, 0x408900,
-                        NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, nv_rd32(dev, r));
+                                nv_rd32(dev, 0x408904) | 0xc0000000);
-                nv_wr32(dev, 0x408e08, nv_rd32(dev, 0x408e08) | 0xc0000000);
+                        for (r = 0x408e08; r <= 0x408e24; r += 4)
+                                NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
-                NV_ERROR(dev, "magic set 2:\n");
+                                                        nv_rd32(dev, r));
-                for (r = 0x409900; r <= 0x409910; r += 4)
+                        nv_wr32(dev, 0x408e08,
-                        NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, nv_rd32(dev, r));
+                                nv_rd32(dev, 0x408e08) | 0xc0000000);
-                nv_wr32(dev, 0x409900, nv_rd32(dev, 0x409904) | 0xc0000000);
-                for (r = 0x409e08; r <= 0x409e24; r += 4)
+                        NV_ERROR(dev, "magic set 2:\n");
-                        NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, nv_rd32(dev, r));
+                        for (r = 0x409900; r <= 0x409910; r += 4)
-                nv_wr32(dev, 0x409e08, nv_rd32(dev, 0x409e08) | 0xc0000000);
+                                NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
+                                        nv_rd32(dev, r));
-                status &= ~0x00200000;
+                        nv_wr32(dev, 0x409900,
-                nv_wr32(dev, NV03_PGRAPH_NSOURCE, nsource);
+                                nv_rd32(dev, 0x409904) | 0xc0000000);
-                nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000);
+                        for (r = 0x409e08; r <= 0x409e24; r += 4)
-        }
+                                NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
+                                        nv_rd32(dev, r));
+                        nv_wr32(dev, 0x409e08,
+                                nv_rd32(dev, 0x409e08) | 0xc0000000);
+                        status &= ~0x00200000;
+                        nv_wr32(dev, NV03_PGRAPH_NSOURCE, nsource);
+                        nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000);
+                }
-        if (status) {
+                if (status) {
-                NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n", status);
+                        NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n",
-                nv_wr32(dev, NV03_PGRAPH_INTR, status);
+                                status);
-        }
+                        nv_wr32(dev, NV03_PGRAPH_INTR, status);
+                }
-        {
+                {
-                const int isb = (1 << 16) | (1 << 0);
+                        const int isb = (1 << 16) | (1 << 0);
-                if ((nv_rd32(dev, 0x400500) & isb) != isb)
+                        if ((nv_rd32(dev, 0x400500) & isb) != isb)
-                        nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | isb);
+                                nv_wr32(dev, 0x400500,
-                nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
+                                        nv_rd32(dev, 0x400500) | isb);
+                }
        }
        nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
+        nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
 }
 static void
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 8f3a12f614ed..2dc09dbd817d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -285,53 +285,50 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
                        uint32_t flags, uint64_t phys)
 {
        struct drm_nouveau_private *dev_priv = dev->dev_private;
-        struct nouveau_gpuobj **pgt;
+        struct nouveau_gpuobj *pgt;
-        unsigned psz, pfl, pages;
+        unsigned block;
+        int i;
-        if (virt >= dev_priv->vm_gart_base &&
-            (virt + size) < (dev_priv->vm_gart_base + dev_priv->vm_gart_size)) {
-                psz = 12;
-                pgt = &dev_priv->gart_info.sg_ctxdma;
-                pfl = 0x21;
-                virt -= dev_priv->vm_gart_base;
-        } else
-        if (virt >= dev_priv->vm_vram_base &&
-            (virt + size) < (dev_priv->vm_vram_base + dev_priv->vm_vram_size)) {
-                psz = 16;
-                pgt = dev_priv->vm_vram_pt;
-                pfl = 0x01;
-                virt -= dev_priv->vm_vram_base;
-        } else {
-                NV_ERROR(dev, "Invalid address: 0x%16llx-0x%16llx\n",
-                         virt, virt + size - 1);
-                return -EINVAL;
-        }
-        pages = size >> psz;
+        virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
+        size = (size >> 16) << 1;
+        phys |= ((uint64_t)flags << 32);
+        phys |= 1;
+        if (dev_priv->vram_sys_base) {
+                phys += dev_priv->vram_sys_base;
+                phys |= 0x30;
+        }
        dev_priv->engine.instmem.prepare_access(dev, true);
-        if (flags & 0x80000000) {
+        while (size) {
-                while (pages--) {
+                unsigned offset_h = upper_32_bits(phys);
-                        struct nouveau_gpuobj *pt = pgt[virt >> 29];
+                unsigned offset_l = lower_32_bits(phys);
-                        unsigned pte = ((virt & 0x1fffffffULL) >> psz) << 1;
+                unsigned pte, end;
+                for (i = 7; i >= 0; i--) {
+                        block = 1 << (i + 1);
+                        if (size >= block && !(virt & (block - 1)))
+                                break;
+                }
+                offset_l |= (i << 7);
-                        nv_wo32(dev, pt, pte++, 0x00000000);
+                phys += block << 15;
-                        nv_wo32(dev, pt, pte++, 0x00000000);
+                size -= block;
-                        virt += (1 << psz);
+                while (block) {
-                }
+                        pgt = dev_priv->vm_vram_pt[virt >> 14];
-        } else {
+                        pte = virt & 0x3ffe;
-                while (pages--) {
-                        struct nouveau_gpuobj *pt = pgt[virt >> 29];
-                        unsigned pte = ((virt & 0x1fffffffULL) >> psz) << 1;
-                        unsigned offset_h = upper_32_bits(phys) & 0xff;
-                        unsigned offset_l = lower_32_bits(phys);
-                        nv_wo32(dev, pt, pte++, offset_l | pfl);
+                        end = pte + block;
-                        nv_wo32(dev, pt, pte++, offset_h | flags);
+                        if (end > 16384)
+                                end = 16384;
+                        block -= (end - pte);
+                        virt  += (end - pte);
-                        phys += (1 << psz);
+                        while (pte < end) {
-                        virt += (1 << psz);
+                                nv_wo32(dev, pgt, pte++, offset_l);
+                                nv_wo32(dev, pgt, pte++, offset_h);
+                        }
                }
        }
        dev_priv->engine.instmem.finish_access(dev);
@@ -356,7 +353,41 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
 void
 nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
 {
-        nv50_mem_vm_bind_linear(dev, virt, size, 0x80000000, 0);
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_gpuobj *pgt;
+        unsigned pages, pte, end;
+        virt -= dev_priv->vm_vram_base;
+        pages = (size >> 16) << 1;
+        dev_priv->engine.instmem.prepare_access(dev, true);
+        while (pages) {
+                pgt = dev_priv->vm_vram_pt[virt >> 29];
+                pte = (virt & 0x1ffe0000ULL) >> 15;
+                end = pte + pages;
+                if (end > 16384)
+                        end = 16384;
+                pages -= (end - pte);
+                virt  += (end - pte) << 15;
+                while (pte < end)
+                        nv_wo32(dev, pgt, pte++, 0);
+        }
+        dev_priv->engine.instmem.finish_access(dev);
+        nv_wr32(dev, 0x100c80, 0x00050001);
+        if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
+                NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
+                NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
+                return;
+        }
+        nv_wr32(dev, 0x100c80, 0x00000001);
+        if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
+                NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
+                NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
+        }
 }
 /*
diff --git a/drivers/gpu/drm/nouveau/nouveau_notifier.c b/drivers/gpu/drm/nouveau/nouveau_notifier.c
index 6c66a34b6345..9537f3e30115 100644
--- a/drivers/gpu/drm/nouveau/nouveau_notifier.c
+++ b/drivers/gpu/drm/nouveau/nouveau_notifier.c
@@ -34,15 +34,20 @@ nouveau_notifier_init_channel(struct nouveau_channel *chan)
 {
        struct drm_device *dev = chan->dev;
        struct nouveau_bo *ntfy = NULL;
+        uint32_t flags;
        int ret;
-        ret = nouveau_gem_new(dev, NULL, PAGE_SIZE, 0, nouveau_vram_notify ?
+        if (nouveau_vram_notify)
-                              TTM_PL_FLAG_VRAM : TTM_PL_FLAG_TT,
+                flags = TTM_PL_FLAG_VRAM;
+        else
+                flags = TTM_PL_FLAG_TT;
+        ret = nouveau_gem_new(dev, NULL, PAGE_SIZE, 0, flags,
                              0, 0x0000, false, true, &ntfy);
        if (ret)
                return ret;
-        ret = nouveau_bo_pin(ntfy, TTM_PL_FLAG_VRAM);
+        ret = nouveau_bo_pin(ntfy, flags);
        if (ret)
                goto out_err;
@@ -56,11 +61,8 @@ nouveau_notifier_init_channel(struct nouveau_channel *chan)
        chan->notifier_bo = ntfy;
 out_err:
-        if (ret) {
+        if (ret)
-                mutex_lock(&dev->struct_mutex);
+                drm_gem_object_unreference_unlocked(ntfy->gem);
-                drm_gem_object_unreference(ntfy->gem);
-                mutex_unlock(&dev->struct_mutex);
-        }
        return ret;
 }
@@ -76,8 +78,8 @@ nouveau_notifier_takedown_channel(struct nouveau_channel *chan)
        nouveau_bo_unmap(chan->notifier_bo);
        mutex_lock(&dev->struct_mutex);
        nouveau_bo_unpin(chan->notifier_bo);
-        drm_gem_object_unreference(chan->notifier_bo->gem);
        mutex_unlock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(chan->notifier_bo->gem);
        nouveau_mem_takedown(&chan->notifier_heap);
 }
@@ -128,6 +130,8 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle,
                        target = NV_DMA_TARGET_PCI;
                } else {
                        target = NV_DMA_TARGET_AGP;
+                        if (dev_priv->card_type >= NV_50)
+                                offset += dev_priv->vm_gart_base;
                }
        } else {
                NV_ERROR(dev, "Bad DMA target, mem_type %d!\n",
diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c
index 6c2cf81716df..e7c100ba63a1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_object.c
+++ b/drivers/gpu/drm/nouveau/nouveau_object.c
@@ -885,11 +885,12 @@ int
 nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class,
                      struct nouveau_gpuobj **gpuobj_ret)
 {
-        struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
+        struct drm_nouveau_private *dev_priv;
        struct nouveau_gpuobj *gpuobj;
        if (!chan || !gpuobj_ret || *gpuobj_ret != NULL)
                return -EINVAL;
+        dev_priv = chan->dev->dev_private;
        gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
        if (!gpuobj)
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h
index 251f1b3b38b9..aa9b310e41be 100644
--- a/drivers/gpu/drm/nouveau/nouveau_reg.h
+++ b/drivers/gpu/drm/nouveau/nouveau_reg.h
@@ -99,6 +99,7 @@
 * the card will hang early on in the X init process.
 */
 #    define NV_PMC_ENABLE_UNK13                               (1<<13)
+#define NV40_PMC_GRAPH_UNITS                               0x00001540
 #define NV40_PMC_BACKLIGHT                                 0x000015f0
 #       define NV40_PMC_BACKLIGHT_MASK                     0x001f0000
 #define NV40_PMC_1700                                      0x00001700
diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
index 4c7f1e403e80..ed1590577b6c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@ -54,11 +54,12 @@ static void
 nouveau_sgdma_clear(struct ttm_backend *be)
 {
        struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
-        struct drm_device *dev = nvbe->dev;
+        struct drm_device *dev;
-        NV_DEBUG(nvbe->dev, "\n");
        if (nvbe && nvbe->pages) {
+                dev = nvbe->dev;
+                NV_DEBUG(dev, "\n");
                if (nvbe->bound)
                        be->func->unbind(be);
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index f2d0187ba152..a4851af5b05e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -310,6 +310,14 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
 static unsigned int
 nouveau_vga_set_decode(void *priv, bool state)
 {
+        struct drm_device *dev = priv;
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        if (dev_priv->chipset >= 0x40)
+                nv_wr32(dev, 0x88054, state);
+        else
+                nv_wr32(dev, 0x1854, state);
        if (state)
                return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
                       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
@@ -427,15 +435,19 @@ nouveau_card_init(struct drm_device *dev)
        if (ret)
                goto out_timer;
-        /* PGRAPH */
+        if (nouveau_noaccel)
-        ret = engine->graph.init(dev);
+                engine->graph.accel_blocked = true;
-        if (ret)
+        else {
-                goto out_fb;
+                /* PGRAPH */
+                ret = engine->graph.init(dev);
+                if (ret)
+                        goto out_fb;
-        /* PFIFO */
+                /* PFIFO */
-        ret = engine->fifo.init(dev);
+                ret = engine->fifo.init(dev);
-        if (ret)
+                if (ret)
-                goto out_graph;
+                        goto out_graph;
+        }
        /* this call irq_preinstall, register irq handler and
         * call irq_postinstall
@@ -479,9 +491,11 @@ nouveau_card_init(struct drm_device *dev)
 out_irq:
        drm_irq_uninstall(dev);
 out_fifo:
-        engine->fifo.takedown(dev);
+        if (!nouveau_noaccel)
+                engine->fifo.takedown(dev);
 out_graph:
-        engine->graph.takedown(dev);
+        if (!nouveau_noaccel)
+                engine->graph.takedown(dev);
 out_fb:
        engine->fb.takedown(dev);
 out_timer:
@@ -518,8 +532,10 @@ static void nouveau_card_takedown(struct drm_device *dev)
                        dev_priv->channel = NULL;
                }
-                engine->fifo.takedown(dev);
+                if (!nouveau_noaccel) {
-                engine->graph.takedown(dev);
+                        engine->fifo.takedown(dev);
+                        engine->graph.takedown(dev);
+                }
                engine->fb.takedown(dev);
                engine->timer.takedown(dev);
                engine->mc.takedown(dev);
@@ -817,6 +833,15 @@ int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
        case NOUVEAU_GETPARAM_VM_VRAM_BASE:
                getparam->value = dev_priv->vm_vram_base;
                break;
+        case NOUVEAU_GETPARAM_GRAPH_UNITS:
+                /* NV40 and NV50 versions are quite different, but register
+                 * address is the same. User is supposed to know the card
+                 * family anyway... */
+                if (dev_priv->chipset >= 0x40) {
+                        getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
+                        break;
+                }
+                /* FALLTHRU */
        default:
                NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
                return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
index d2f143ed97c1..a1d1ebb073d9 100644
--- a/drivers/gpu/drm/nouveau/nv04_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
@@ -926,9 +926,7 @@ nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
        nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
        nv_crtc->cursor.show(nv_crtc, true);
 out:
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(gem);
-        drm_gem_object_unreference(gem);
-        mutex_unlock(&dev->struct_mutex);
        return ret;
 }
diff --git a/drivers/gpu/drm/nouveau/nv04_dac.c b/drivers/gpu/drm/nouveau/nv04_dac.c
index d0e038d28948..1d73b15d70da 100644
--- a/drivers/gpu/drm/nouveau/nv04_dac.c
+++ b/drivers/gpu/drm/nouveau/nv04_dac.c
@@ -119,7 +119,7 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
                                                 struct drm_connector *connector)
 {
        struct drm_device *dev = encoder->dev;
-        uint8_t saved_seq1, saved_pi, saved_rpc1;
+        uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode;
        uint8_t saved_palette0[3], saved_palette_mask;
        uint32_t saved_rtest_ctrl, saved_rgen_ctrl;
        int i;
@@ -135,6 +135,9 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
                /* only implemented for head A for now */
                NVSetOwner(dev, 0);
+        saved_cr_mode = NVReadVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX);
+        NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode | 0x80);
        saved_seq1 = NVReadVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX);
        NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20);
@@ -203,6 +206,7 @@ out:
        NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi);
        NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1);
        NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);
+        NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode);
        if (blue == 0x18) {
                NV_INFO(dev, "Load detected on head A\n");
diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c
index d910873c1368..fd01caabd5c3 100644
--- a/drivers/gpu/drm/nouveau/nv04_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c
@@ -27,7 +27,7 @@
 #include "nouveau_dma.h"
 #include "nouveau_fbcon.h"
-static void
+void
 nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
 {
        struct nouveau_fbcon_par *par = info->par;
@@ -54,7 +54,7 @@ nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
        FIRE_RING(chan);
 }
-static void
+void
 nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
 {
        struct nouveau_fbcon_par *par = info->par;
@@ -88,7 +88,7 @@ nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
        FIRE_RING(chan);
 }
-static void
+void
 nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
 {
        struct nouveau_fbcon_par *par = info->par;
@@ -307,9 +307,6 @@ nv04_fbcon_accel_init(struct fb_info *info)
        FIRE_RING(chan);
-        info->fbops->fb_fillrect = nv04_fbcon_fillrect;
-        info->fbops->fb_copyarea = nv04_fbcon_copyarea;
-        info->fbops->fb_imageblit = nv04_fbcon_imageblit;
        return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c
index 58b917c3341b..21ac6e49b6ee 100644
--- a/drivers/gpu/drm/nouveau/nv17_tv.c
+++ b/drivers/gpu/drm/nouveau/nv17_tv.c
@@ -579,6 +579,8 @@ static void nv17_tv_restore(struct drm_encoder *encoder)
                                nouveau_encoder(encoder)->restore.output);
        nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state);
+        nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED;
 }
 static int nv17_tv_create_resources(struct drm_encoder *encoder,
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
index 40b7360841f8..cfabeb974a56 100644
--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -298,14 +298,17 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
 static void
 nv50_crtc_destroy(struct drm_crtc *crtc)
 {
-        struct drm_device *dev = crtc->dev;
+        struct drm_device *dev;
-        struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
+        struct nouveau_crtc *nv_crtc;
-        NV_DEBUG_KMS(dev, "\n");
        if (!crtc)
                return;
+        dev = crtc->dev;
+        nv_crtc = nouveau_crtc(crtc);
+        NV_DEBUG_KMS(dev, "\n");
        drm_crtc_cleanup(&nv_crtc->base);
        nv50_cursor_fini(nv_crtc);
@@ -355,9 +358,7 @@ nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
        nv_crtc->cursor.show(nv_crtc, true);
 out:
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(gem);
-        drm_gem_object_unreference(gem);
-        mutex_unlock(&dev->struct_mutex);
        return ret;
 }
diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c
index e4f279ee61cf..0f57cdf7ccb2 100644
--- a/drivers/gpu/drm/nouveau/nv50_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c
@@ -3,7 +3,7 @@
 #include "nouveau_dma.h"
 #include "nouveau_fbcon.h"
-static void
+void
 nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
 {
        struct nouveau_fbcon_par *par = info->par;
@@ -46,7 +46,7 @@ nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
        FIRE_RING(chan);
 }
-static void
+void
 nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
 {
        struct nouveau_fbcon_par *par = info->par;
@@ -81,7 +81,7 @@ nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
        FIRE_RING(chan);
 }
-static void
+void
 nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
 {
        struct nouveau_fbcon_par *par = info->par;
@@ -262,9 +262,6 @@ nv50_fbcon_accel_init(struct fb_info *info)
        OUT_RING(chan, info->fix.smem_start - dev_priv->fb_phys +
                         dev_priv->vm_vram_base);
-        info->fbops->fb_fillrect = nv50_fbcon_fillrect;
-        info->fbops->fb_copyarea = nv50_fbcon_copyarea;
-        info->fbops->fb_imageblit = nv50_fbcon_imageblit;
        return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c
index 32b244bcb482..204a79ff10f4 100644
--- a/drivers/gpu/drm/nouveau/nv50_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv50_fifo.c
@@ -317,17 +317,20 @@ void
 nv50_fifo_destroy_context(struct nouveau_channel *chan)
 {
        struct drm_device *dev = chan->dev;
+        struct nouveau_gpuobj_ref *ramfc = chan->ramfc;
        NV_DEBUG(dev, "ch%d\n", chan->id);
-        nouveau_gpuobj_ref_del(dev, &chan->ramfc);
+        /* This will ensure the channel is seen as disabled. */
-        nouveau_gpuobj_ref_del(dev, &chan->cache);
+        chan->ramfc = NULL;
        nv50_fifo_channel_disable(dev, chan->id, false);
        /* Dummy channel, also used on ch 127 */
        if (chan->id == 0)
                nv50_fifo_channel_disable(dev, 127, false);
+        nouveau_gpuobj_ref_del(dev, &ramfc);
+        nouveau_gpuobj_ref_del(dev, &chan->cache);
 }
 int
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index 20319e59d368..6d504801b514 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -165,6 +165,12 @@ nv50_graph_channel(struct drm_device *dev)
        uint32_t inst;
        int i;
+        /* Be sure we're not in the middle of a context switch or bad things
+         * will happen, such as unloading the wrong pgraph context.
+         */
+        if (!nv_wait(0x400300, 0x00000001, 0x00000000))
+                NV_ERROR(dev, "Ctxprog is still running\n");
        inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
        if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
                return NULL;
@@ -275,7 +281,7 @@ nv50_graph_load_context(struct nouveau_channel *chan)
 int
 nv50_graph_unload_context(struct drm_device *dev)
 {
-        uint32_t inst, fifo = nv_rd32(dev, 0x400500);
+        uint32_t inst;
        inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
        if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
@@ -283,12 +289,10 @@ nv50_graph_unload_context(struct drm_device *dev)
        inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
        nouveau_wait_for_idle(dev);
-        nv_wr32(dev, 0x400500, fifo & ~1);
        nv_wr32(dev, 0x400784, inst);
        nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
        nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
        nouveau_wait_for_idle(dev);
-        nv_wr32(dev, 0x400500, fifo);
        nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
        return 0;
diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c
index 94400f777e7f..f0dc4e36ef05 100644
--- a/drivers/gpu/drm/nouveau/nv50_instmem.c
+++ b/drivers/gpu/drm/nouveau/nv50_instmem.c
@@ -76,6 +76,11 @@ nv50_instmem_init(struct drm_device *dev)
        for (i = 0x1700; i <= 0x1710; i += 4)
                priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i);
+        if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac)
+                dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10) << 12;
+        else
+                dev_priv->vram_sys_base = 0;
        /* Reserve the last MiB of VRAM, we should probably try to avoid
         * setting up the below tables over the top of the VBIOS image at
         * some point.
@@ -172,16 +177,28 @@ nv50_instmem_init(struct drm_device *dev)
         * We map the entire fake channel into the start of the PRAMIN BAR
         */
        ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pt_size, 0x1000,
-                                                        0, &priv->pramin_pt);
+                                     0, &priv->pramin_pt);
        if (ret)
                return ret;
-        for (i = 0, v = c_offset; i < pt_size; i += 8, v += 0x1000) {
+        v = c_offset | 1;
-                if (v < (c_offset + c_size))
+        if (dev_priv->vram_sys_base) {
-                        BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v | 1);
+                v += dev_priv->vram_sys_base;
-                else
+                v |= 0x30;
-                        BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000009);
+        }
+        i = 0;
+        while (v < dev_priv->vram_sys_base + c_offset + c_size) {
+                BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v);
+                BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
+                v += 0x1000;
+                i += 8;
+        }
+        while (i < pt_size) {
+                BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000000);
                BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
+                i += 8;
        }
        BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63);
@@ -416,7 +433,9 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 {
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
-        uint32_t pte, pte_end, vram;
+        struct nouveau_gpuobj *pramin_pt = priv->pramin_pt->gpuobj;
+        uint32_t pte, pte_end;
+        uint64_t vram;
        if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)
                return -EINVAL;
@@ -424,20 +443,24 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
        NV_DEBUG(dev, "st=0x%0llx sz=0x%0llx\n",
                 gpuobj->im_pramin->start, gpuobj->im_pramin->size);
-        pte     = (gpuobj->im_pramin->start >> 12) << 3;
+        pte     = (gpuobj->im_pramin->start >> 12) << 1;
-        pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte;
+        pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
        vram    = gpuobj->im_backing_start;
        NV_DEBUG(dev, "pramin=0x%llx, pte=%d, pte_end=%d\n",
                 gpuobj->im_pramin->start, pte, pte_end);
        NV_DEBUG(dev, "first vram page: 0x%08x\n", gpuobj->im_backing_start);
+        vram |= 1;
+        if (dev_priv->vram_sys_base) {
+                vram += dev_priv->vram_sys_base;
+                vram |= 0x30;
+        }
        dev_priv->engine.instmem.prepare_access(dev, true);
        while (pte < pte_end) {
-                nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 0)/4, vram | 1);
+                nv_wo32(dev, pramin_pt, pte++, lower_32_bits(vram));
-                nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000);
+                nv_wo32(dev, pramin_pt, pte++, upper_32_bits(vram));
-                pte += 8;
                vram += NV50_INSTMEM_PAGE_SIZE;
        }
        dev_priv->engine.instmem.finish_access(dev);
@@ -470,14 +493,13 @@ nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
        if (gpuobj->im_bound == 0)
                return -EINVAL;
-        pte     = (gpuobj->im_pramin->start >> 12) << 3;
+        pte     = (gpuobj->im_pramin->start >> 12) << 1;
-        pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte;
+        pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
        dev_priv->engine.instmem.prepare_access(dev, true);
        while (pte < pte_end) {
-                nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 0)/4, 0x00000009);
+                nv_wo32(dev, priv->pramin_pt->gpuobj, pte++, 0x00000000);
-                nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000);
+                nv_wo32(dev, priv->pramin_pt->gpuobj, pte++, 0x00000000);
-                pte += 8;
        }
        dev_priv->engine.instmem.finish_access(dev);
diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c
index ecf1936b8224..c2fff543b06f 100644
--- a/drivers/gpu/drm/nouveau/nv50_sor.c
+++ b/drivers/gpu/drm/nouveau/nv50_sor.c
@@ -101,6 +101,7 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
                struct nouveau_encoder *nvenc = nouveau_encoder(enc);
                if (nvenc == nv_encoder ||
+                    nvenc->disconnect != nv50_sor_disconnect ||
                    nvenc->dcb->or != nv_encoder->dcb->or)
                        continue;
diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig
index 5982321be4d5..1c02d23f6fcc 100644
--- a/drivers/gpu/drm/radeon/Kconfig
+++ b/drivers/gpu/drm/radeon/Kconfig
@@ -1,10 +1,14 @@
 config DRM_RADEON_KMS
-        bool "Enable modesetting on radeon by default"
+        bool "Enable modesetting on radeon by default - NEW DRIVER"
        depends on DRM_RADEON
        help
-          Choose this option if you want kernel modesetting enabled by default,
+          Choose this option if you want kernel modesetting enabled by default.
-          and you have a new enough userspace to support this. Running old
-          userspaces with this enabled will cause pain.
+          This is a completely new driver. It's only part of the existing drm
+          for compatibility reasons. It requires an entirely different graphics
+          stack above it and works very differently from the old drm stack.
+          i.e. don't enable this unless you know what you are doing it may
+          cause issues or bugs compared to the previous userspace driver stack.
          When kernel modesetting is enabled the IOCTL of radeon/drm
          driver are considered as invalid and an error message is printed
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index bd0c843872b2..d75788feac6c 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -24,6 +24,7 @@
 #include <linux/module.h>
 #include <linux/sched.h>
+#include <asm/unaligned.h>
 #define ATOM_DEBUG
@@ -212,7 +213,9 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
        case ATOM_ARG_PS:
                idx = U8(*ptr);
                (*ptr)++;
-                val = le32_to_cpu(ctx->ps[idx]);
+                /* get_unaligned_le32 avoids unaligned accesses from atombios
+                 * tables, noticed on a DEC Alpha. */
+                val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
                if (print)
                        DEBUG("PS[0x%02X,0x%04X]", idx, val);
                break;
@@ -641,7 +644,6 @@ static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
        SDEBUG("   count: %d\n", count);
        if (arg == ATOM_UNIT_MICROSEC)
                udelay(count);
-        //      schedule_timeout_uninterruptible(usecs_to_jiffies(count));
        else
                schedule_timeout_uninterruptible(msecs_to_jiffies(count));
 }
@@ -879,8 +881,6 @@ static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
        uint8_t attr = U8((*ptr)++), shift;
        uint32_t saved, dst;
        int dptr = *ptr;
-        attr &= 0x38;
-        attr |= atom_def_dst[attr >> 3] << 6;
        SDEBUG("   dst: ");
        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
        shift = atom_get_src(ctx, attr, ptr);
@@ -895,8 +895,6 @@ static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
        uint8_t attr = U8((*ptr)++), shift;
        uint32_t saved, dst;
        int dptr = *ptr;
-        attr &= 0x38;
-        attr |= atom_def_dst[attr >> 3] << 6;
        SDEBUG("   dst: ");
        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
        shift = atom_get_src(ctx, attr, ptr);
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 0b6f2cef1c52..8a133bda00a2 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -336,11 +336,13 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
        union aux_channel_transaction args;
        int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
        unsigned char *base;
+        int retry_count = 0;
        memset(&args, 0, sizeof(args));
        base = (unsigned char *)rdev->mode_info.atom_context->scratch;
+retry:
        memcpy(base, req_bytes, num_bytes);
        args.v1.lpAuxRequest = 0;
@@ -353,10 +355,12 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
-        if (args.v1.ucReplyStatus) {
+        if (args.v1.ucReplyStatus && !args.v1.ucDataOutLen) {
-                DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x\n",
+                if (args.v1.ucReplyStatus == 0x20 && retry_count++ < 10)
+                        goto retry;
+                DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x after %d retries\n",
                          req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],
-                          chan->rec.i2c_id, args.v1.ucReplyStatus);
+                          chan->rec.i2c_id, args.v1.ucReplyStatus, retry_count);
                return false;
        }
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index f9a83358aa5a..c52290197292 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1970,6 +1970,13 @@ int r600_resume(struct radeon_device *rdev)
                DRM_ERROR("radeon: failled testing IB (%d).\n", r);
                return r;
        }
+        r = r600_audio_init(rdev);
+        if (r) {
+                DRM_ERROR("radeon: audio resume failed\n");
+                return r;
+        }
        return r;
 }
@@ -1977,6 +1984,7 @@ int r600_suspend(struct radeon_device *rdev)
 {
        int r;
+        r600_audio_fini(rdev);
        /* FIXME: we should wait for ring to be empty */
        r600_cp_stop(rdev);
        rdev->cp.ready = false;
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
index d7f6909afc01..387abaa275a4 100644
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -270,6 +270,7 @@ void r600_audio_fini(struct radeon_device *rdev)
                return;
        del_timer(&rdev->audio_timer);
+        WREG32_P(R600_AUDIO_ENABLE, 0x0, ~0x81000000);
        r600_audio_engine_enable(rdev, false);
 }
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 6f8619cd1a0d..93783b15c81d 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -213,6 +213,15 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
                        *connector_type = DRM_MODE_CONNECTOR_DVID;
        }
+        /* Asrock RS600 board lists the DVI port as HDMI */
+        if ((dev->pdev->device == 0x7941) &&
+            (dev->pdev->subsystem_vendor == 0x1849) &&
+            (dev->pdev->subsystem_device == 0x7941)) {
+                if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
+                    (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
+                        *connector_type = DRM_MODE_CONNECTOR_DVID;
+        }
        /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
        if ((dev->pdev->device == 0x7941) &&
            (dev->pdev->subsystem_vendor == 0x147b) &&
@@ -294,6 +303,15 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
                        *connector_type = DRM_MODE_CONNECTOR_DVID;
        }
+        /* XFX Pine Group device rv730 reports no VGA DDC lines
+         * even though they are wired up to record 0x93
+         */
+        if ((dev->pdev->device == 0x9498) &&
+            (dev->pdev->subsystem_vendor == 0x1682) &&
+            (dev->pdev->subsystem_device == 0x2452)) {
+                struct radeon_device *rdev = dev->dev_private;
+                *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
+        }
        return true;
 }
diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c b/drivers/gpu/drm/radeon/radeon_benchmark.c
index 4ddfd4b5bc51..7932dc4d6b90 100644
--- a/drivers/gpu/drm/radeon/radeon_benchmark.c
+++ b/drivers/gpu/drm/radeon/radeon_benchmark.c
@@ -65,31 +65,42 @@ void radeon_benchmark_move(struct radeon_device *rdev, unsigned bsize,
        if (r) {
                goto out_cleanup;
        }
-        start_jiffies = jiffies;
-        for (i = 0; i < n; i++) {
+        /* r100 doesn't have dma engine so skip the test */
-                r = radeon_fence_create(rdev, &fence);
+        if (rdev->asic->copy_dma) {
-                if (r) {
-                        goto out_cleanup;
+                start_jiffies = jiffies;
+                for (i = 0; i < n; i++) {
+                        r = radeon_fence_create(rdev, &fence);
+                        if (r) {
+                                goto out_cleanup;
+                        }
+                        r = radeon_copy_dma(rdev, saddr, daddr,
+                                        size / RADEON_GPU_PAGE_SIZE, fence);
+                        if (r) {
+                                goto out_cleanup;
+                        }
+                        r = radeon_fence_wait(fence, false);
+                        if (r) {
+                                goto out_cleanup;
+                        }
+                        radeon_fence_unref(&fence);
                }
-                r = radeon_copy_dma(rdev, saddr, daddr, size / RADEON_GPU_PAGE_SIZE, fence);
+                end_jiffies = jiffies;
-                if (r) {
+                time = end_jiffies - start_jiffies;
-                        goto out_cleanup;
+                time = jiffies_to_msecs(time);
+                if (time > 0) {
+                        i = ((n * size) >> 10) / time;
+                        printk(KERN_INFO "radeon: dma %u bo moves of %ukb from"
+                                        " %d to %d in %lums (%ukb/ms %ukb/s %uM/s)\n",
+                                        n, size >> 10,
+                                        sdomain, ddomain, time,
+                                        i, i * 1000, (i * 1000) / 1024);
                }
-                r = radeon_fence_wait(fence, false);
-                if (r) {
-                        goto out_cleanup;
-                }
-                radeon_fence_unref(&fence);
-        }
-        end_jiffies = jiffies;
-        time = end_jiffies - start_jiffies;
-        time = jiffies_to_msecs(time);
-        if (time > 0) {
-                i = ((n * size) >> 10) / time;
-                printk(KERN_INFO "radeon: dma %u bo moves of %ukb from %d to %d"
-                       " in %lums (%ukb/ms %ukb/s %uM/s)\n", n, size >> 10,
-                       sdomain, ddomain, time, i, i * 1000, (i * 1000) / 1024);
        }
        start_jiffies = jiffies;
        for (i = 0; i < n; i++) {
                r = radeon_fence_create(rdev, &fence);
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 6e9e7b59d67e..ee0083f982d8 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -578,14 +578,15 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect
        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
        struct drm_encoder *encoder;
        struct drm_encoder_helper_funcs *encoder_funcs;
-        bool dret;
+        bool dret = false;
        enum drm_connector_status ret = connector_status_disconnected;
        encoder = radeon_best_single_encoder(connector);
        if (!encoder)
                ret = connector_status_disconnected;
-        dret = radeon_ddc_probe(radeon_connector);
+        if (radeon_connector->ddc_bus)
+                dret = radeon_ddc_probe(radeon_connector);
        if (dret) {
                if (radeon_connector->edid) {
                        kfree(radeon_connector->edid);
@@ -734,9 +735,10 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
        struct drm_mode_object *obj;
        int i;
        enum drm_connector_status ret = connector_status_disconnected;
-        bool dret;
+        bool dret = false;
-        dret = radeon_ddc_probe(radeon_connector);
+        if (radeon_connector->ddc_bus)
+                dret = radeon_ddc_probe(radeon_connector);
        if (dret) {
                if (radeon_connector->edid) {
                        kfree(radeon_connector->edid);
@@ -766,7 +768,7 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
                         * connected and the DVI port disconnected.  If the edid doesn't
                         * say HDMI, vice versa.
                         */
-                        if (radeon_connector->shared_ddc && connector_status_connected) {
+                        if (radeon_connector->shared_ddc && (ret == connector_status_connected)) {
                                struct drm_device *dev = connector->dev;
                                struct drm_connector *list_connector;
                                struct radeon_connector *list_radeon_connector;
@@ -1044,8 +1046,7 @@ radeon_add_atom_connector(struct drm_device *dev,
                        return;
                }
                if (radeon_connector->ddc_bus && i2c_bus->valid) {
-                        if (memcmp(&radeon_connector->ddc_bus->rec, i2c_bus,
+                        if (radeon_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
-                                    sizeof(struct radeon_i2c_bus_rec)) == 0) {
                                radeon_connector->shared_ddc = true;
                                shared_ddc = true;
                        }
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index e9d085021c1f..70ba02ed7723 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -194,11 +194,8 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
        }
        radeon_bo_list_unreserve(&parser->validated);
        for (i = 0; i < parser->nrelocs; i++) {
-                if (parser->relocs[i].gobj) {
+                if (parser->relocs[i].gobj)
-                        mutex_lock(&parser->rdev->ddev->struct_mutex);
+                        drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
-                        drm_gem_object_unreference(parser->relocs[i].gobj);
-                        mutex_unlock(&parser->rdev->ddev->struct_mutex);
-                }
        }
        kfree(parser->track);
        kfree(parser->relocs);
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
index 7ecf5e1b39c1..b7023fff89eb 100644
--- a/drivers/gpu/drm/radeon/radeon_cursor.c
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
@@ -186,17 +186,13 @@ int radeon_crtc_cursor_set(struct drm_crtc *crtc,
 unpin:
        if (radeon_crtc->cursor_bo) {
                radeon_gem_object_unpin(radeon_crtc->cursor_bo);
-                mutex_lock(&crtc->dev->struct_mutex);
+                drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
-                drm_gem_object_unreference(radeon_crtc->cursor_bo);
-                mutex_unlock(&crtc->dev->struct_mutex);
        }
        radeon_crtc->cursor_bo = obj;
        return 0;
 fail:
-        mutex_lock(&crtc->dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(obj);
-        drm_gem_object_unreference(obj);
-        mutex_unlock(&crtc->dev->struct_mutex);
        return 0;
 }
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index e35cc3da8f22..ba8d806dcf39 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -310,7 +310,7 @@ static void radeon_print_display_setup(struct drm_device *dev)
                DRM_INFO("  %s\n", connector_names[connector->connector_type]);
                if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
                        DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
-                if (radeon_connector->ddc_bus)
+                if (radeon_connector->ddc_bus) {
                        DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
                                 radeon_connector->ddc_bus->rec.mask_clk_reg,
                                 radeon_connector->ddc_bus->rec.mask_data_reg,
@@ -320,6 +320,15 @@ static void radeon_print_display_setup(struct drm_device *dev)
                                 radeon_connector->ddc_bus->rec.en_data_reg,
                                 radeon_connector->ddc_bus->rec.y_clk_reg,
                                 radeon_connector->ddc_bus->rec.y_data_reg);
+                } else {
+                        if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
+                            connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
+                            connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
+                            connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
+                            connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
+                            connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
+                                DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
+                }
                DRM_INFO("  Encoders:\n");
                list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
                        radeon_encoder = to_radeon_encoder(encoder);
@@ -801,11 +810,8 @@ static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
        if (fb->fbdev)
                radeonfb_remove(dev, fb);
-        if (radeon_fb->obj) {
+        if (radeon_fb->obj)
-                mutex_lock(&dev->struct_mutex);
+                drm_gem_object_unreference_unlocked(radeon_fb->obj);
-                drm_gem_object_unreference(radeon_fb->obj);
-                mutex_unlock(&dev->struct_mutex);
-        }
        drm_framebuffer_cleanup(fb);
        kfree(radeon_fb);
 }
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index f6d20cee5705..88f4d8669d84 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -106,9 +106,10 @@
 * 1.29- R500 3D cmd buffer support
 * 1.30- Add support for occlusion queries
 * 1.31- Add support for num Z pipes from GET_PARAM
+ * 1.32- fixes for rv740 setup
 */
 #define DRIVER_MAJOR            1
-#define DRIVER_MINOR            31
+#define DRIVER_MINOR            32
 #define DRIVER_PATCHLEVEL       0
 enum radeon_cp_microcode_version {
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index c39ddda13840..cda112cc7a6c 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -59,7 +59,7 @@ static struct fb_ops radeonfb_ops = {
 };
 /**
- * Curretly it is assumed that the old framebuffer is reused.
+ * Currently it is assumed that the old framebuffer is reused.
 *
 * LOCKING
 * caller should hold the mode config lock.
@@ -243,7 +243,7 @@ int radeonfb_create(struct drm_device *dev,
        if (ret)
                goto out_unref;
-        memset_io(fbptr, 0xff, aligned_size);
+        memset_io(fbptr, 0x0, aligned_size);
        strcpy(info->fix.id, "radeondrmfb");
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index db8e9a355a01..ef92d147d8f0 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -69,9 +69,7 @@ int radeon_gem_object_create(struct radeon_device *rdev, int size,
                if (r != -ERESTARTSYS)
                        DRM_ERROR("Failed to allocate GEM object (%d, %d, %u, %d)\n",
                                  size, initial_domain, alignment, r);
-                mutex_lock(&rdev->ddev->struct_mutex);
+                drm_gem_object_unreference_unlocked(gobj);
-                drm_gem_object_unreference(gobj);
-                mutex_unlock(&rdev->ddev->struct_mutex);
                return r;
        }
        gobj->driver_private = robj;
@@ -202,14 +200,10 @@ int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
        }
        r = drm_gem_handle_create(filp, gobj, &handle);
        if (r) {
-                mutex_lock(&dev->struct_mutex);
+                drm_gem_object_unreference_unlocked(gobj);
-                drm_gem_object_unreference(gobj);
-                mutex_unlock(&dev->struct_mutex);
                return r;
        }
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_handle_unreference_unlocked(gobj);
-        drm_gem_object_handle_unreference(gobj);
-        mutex_unlock(&dev->struct_mutex);
        args->handle = handle;
        return 0;
 }
@@ -236,9 +230,7 @@ int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
        r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain);
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(gobj);
-        drm_gem_object_unreference(gobj);
-        mutex_unlock(&dev->struct_mutex);
        return r;
 }
@@ -255,9 +247,7 @@ int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
        }
        robj = gobj->driver_private;
        args->addr_ptr = radeon_bo_mmap_offset(robj);
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(gobj);
-        drm_gem_object_unreference(gobj);
-        mutex_unlock(&dev->struct_mutex);
        return 0;
 }
@@ -288,9 +278,7 @@ int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
        default:
                break;
        }
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(gobj);
-        drm_gem_object_unreference(gobj);
-        mutex_unlock(&dev->struct_mutex);
        return r;
 }
@@ -311,9 +299,7 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
        /* callback hw specific functions if any */
        if (robj->rdev->asic->ioctl_wait_idle)
                robj->rdev->asic->ioctl_wait_idle(robj->rdev, robj);
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(gobj);
-        drm_gem_object_unreference(gobj);
-        mutex_unlock(&dev->struct_mutex);
        return r;
 }
@@ -331,9 +317,7 @@ int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
                return -EINVAL;
        robj = gobj->driver_private;
        r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch);
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(gobj);
-        drm_gem_object_unreference(gobj);
-        mutex_unlock(&dev->struct_mutex);
        return r;
 }
@@ -356,8 +340,6 @@ int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
        radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch);
        radeon_bo_unreserve(rbo);
 out:
-        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference_unlocked(gobj);
-        drm_gem_object_unreference(gobj);
-        mutex_unlock(&dev->struct_mutex);
        return r;
 }
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 38fa14429320..e50513a62735 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -130,6 +130,8 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
        if (tmp == NULL) {
                return;
        }
+        if (!tmp->fence->emited)
+                radeon_fence_unref(&tmp->fence);
        mutex_lock(&rdev->ib_pool.mutex);
        tmp->free = true;
        mutex_unlock(&rdev->ib_pool.mutex);
@@ -222,6 +224,7 @@ void radeon_ib_pool_fini(struct radeon_device *rdev)
        }
        mutex_lock(&rdev->ib_pool.mutex);
        radeon_ib_bogus_cleanup(rdev);
        if (rdev->ib_pool.robj) {
                r = radeon_bo_reserve(rdev->ib_pool.robj, false);
                if (likely(r == 0)) {
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index 44b6d66b0ab3..32971b8272cf 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -1972,7 +1972,7 @@ static void radeon_apply_surface_regs(int surf_index,
 * Note that refcount can be at most 2, since during a free refcount=3
 * might mean we have to allocate a new surface which might not always
 * be available.
- * For example : we allocate three contigous surfaces ABC. If B is
+ * For example : we allocate three contiguous surfaces ABC. If B is
 * freed, we suddenly need two surfaces to store A and C, which might
 * not always be available.
 */
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 1157e0f758fa..43c5ab34b634 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -409,7 +409,7 @@ static int radeon_bo_move(struct ttm_buffer_object *bo,
             new_mem->mem_type == TTM_PL_SYSTEM) ||
            (old_mem->mem_type == TTM_PL_SYSTEM &&
             new_mem->mem_type == TTM_PL_TT)) {
-                /* bind is enought */
+                /* bind is enough */
                radeon_move_null(bo, new_mem);
                return 0;
        }
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 1a3e909b7bba..c7320ce4567d 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -1020,6 +1020,12 @@ static int ttm_bo_mem_compat(struct ttm_placement *placement,
                             struct ttm_mem_reg *mem)
 {
        int i;
+        struct drm_mm_node *node = mem->mm_node;
+        if (node && placement->lpfn != 0 &&
+            (node->start < placement->fpfn ||
+             node->start + node->size > placement->lpfn))
+                return -1;
        for (i = 0; i < placement->num_placement; i++) {
                if ((placement->placement[i] & mem->placement &
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 3f72fe1ddf8b..5ca37a58a98c 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -424,7 +424,7 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo,
                /*
                 * We need to use vmap to get the desired page protection
-                 * or to make the buffer object look contigous.
+                 * or to make the buffer object look contiguous.
                 */
                prot = (mem->placement & TTM_PL_FLAG_CACHED) ?
                        PAGE_KERNEL :
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index e2123af7775a..a759170763bb 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -196,14 +196,15 @@ EXPORT_SYMBOL(ttm_tt_populate);
 #ifdef CONFIG_X86
 static inline int ttm_tt_set_page_caching(struct page *p,
-                                          enum ttm_caching_state c_state)
+                                          enum ttm_caching_state c_old,
+                                          enum ttm_caching_state c_new)
 {
        int ret = 0;
        if (PageHighMem(p))
                return 0;
-        if (get_page_memtype(p) != -1) {
+        if (c_old != tt_cached) {
                /* p isn't in the default caching state, set it to
                 * writeback first to free its current memtype. */
@@ -212,16 +213,17 @@ static inline int ttm_tt_set_page_caching(struct page *p,
                        return ret;
        }
-        if (c_state == tt_wc)
+        if (c_new == tt_wc)
                ret = set_memory_wc((unsigned long) page_address(p), 1);
-        else if (c_state == tt_uncached)
+        else if (c_new == tt_uncached)
                ret = set_pages_uc(p, 1);
        return ret;
 }
 #else /* CONFIG_X86 */
 static inline int ttm_tt_set_page_caching(struct page *p,
-                                          enum ttm_caching_state c_state)
+                                          enum ttm_caching_state c_old,
+                                          enum ttm_caching_state c_new)
 {
        return 0;
 }
@@ -254,7 +256,9 @@ static int ttm_tt_set_caching(struct ttm_tt *ttm,
        for (i = 0; i < ttm->num_pages; ++i) {
                cur_page = ttm->pages[i];
                if (likely(cur_page != NULL)) {
-                        ret = ttm_tt_set_page_caching(cur_page, c_state);
+                        ret = ttm_tt_set_page_caching(cur_page,
+                                                      ttm->caching_state,
+                                                      c_state);
                        if (unlikely(ret != 0))
                                goto out_err;
                }
@@ -268,7 +272,7 @@ out_err:
        for (j = 0; j < i; ++j) {
                cur_page = ttm->pages[j];
                if (likely(cur_page != NULL)) {
-                        (void)ttm_tt_set_page_caching(cur_page,
+                        (void)ttm_tt_set_page_caching(cur_page, c_state,
                                                      ttm->caching_state);
                }
        }
@@ -476,7 +480,7 @@ static int ttm_tt_swapin(struct ttm_tt *ttm)
        void *from_virtual;
        void *to_virtual;
        int i;
-        int ret;
+        int ret = -ENOMEM;
        if (ttm->page_flags & TTM_PAGE_FLAG_USER) {
                ret = ttm_tt_set_user(ttm, ttm->tsk, ttm->start,
@@ -495,8 +499,10 @@ static int ttm_tt_swapin(struct ttm_tt *ttm)
        for (i = 0; i < ttm->num_pages; ++i) {
                from_page = read_mapping_page(swap_space, i, NULL);
-                if (IS_ERR(from_page))
+                if (IS_ERR(from_page)) {
+                        ret = PTR_ERR(from_page);
                        goto out_err;
+                }
                to_page = __ttm_tt_get_page(ttm, i);
                if (unlikely(to_page == NULL))
                        goto out_err;
@@ -519,7 +525,7 @@ static int ttm_tt_swapin(struct ttm_tt *ttm)
        return 0;
 out_err:
        ttm_tt_free_alloced_pages(ttm);
-        return -ENOMEM;
+        return ret;
 }
 int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistant_swap_storage)
@@ -531,6 +537,7 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistant_swap_storage)
        void *from_virtual;
        void *to_virtual;
        int i;
+        int ret = -ENOMEM;
        BUG_ON(ttm->state != tt_unbound && ttm->state != tt_unpopulated);
        BUG_ON(ttm->caching_state != tt_cached);
@@ -553,7 +560,7 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistant_swap_storage)
                                                0);
                if (unlikely(IS_ERR(swap_storage))) {
                        printk(KERN_ERR "Failed allocating swap storage.\n");
-                        return -ENOMEM;
+                        return PTR_ERR(swap_storage);
                }
        } else
                swap_storage = persistant_swap_storage;
@@ -565,9 +572,10 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistant_swap_storage)
                if (unlikely(from_page == NULL))
                        continue;
                to_page = read_mapping_page(swap_space, i, NULL);
-                if (unlikely(to_page == NULL))
+                if (unlikely(IS_ERR(to_page))) {
+                        ret = PTR_ERR(to_page);
                        goto out_err;
+                }
                preempt_disable();
                from_virtual = kmap_atomic(from_page, KM_USER0);
                to_virtual = kmap_atomic(to_page, KM_USER1);
@@ -591,5 +599,5 @@ out_err:
        if (!persistant_swap_storage)
                fput(swap_storage);
-        return -ENOMEM;
+        return ret;
 }
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index a6e8f687fa64..0c9c0811f42d 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -348,22 +348,19 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
                 */
                DRM_INFO("It appears like vesafb is loaded. "
-                         "Ignore above error if any. Entering stealth mode.\n");
+                         "Ignore above error if any.\n");
                ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
                if (unlikely(ret != 0)) {
                        DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
                        goto out_no_device;
                }
-                vmw_kms_init(dev_priv);
-                vmw_overlay_init(dev_priv);
-        } else {
-                ret = vmw_request_device(dev_priv);
-                if (unlikely(ret != 0))
-                        goto out_no_device;
-                vmw_kms_init(dev_priv);
-                vmw_overlay_init(dev_priv);
-                vmw_fb_init(dev_priv);
        }
+        ret = vmw_request_device(dev_priv);
+        if (unlikely(ret != 0))
+                goto out_no_device;
+        vmw_kms_init(dev_priv);
+        vmw_overlay_init(dev_priv);
+        vmw_fb_init(dev_priv);
        dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
        register_pm_notifier(&dev_priv->pm_nb);
@@ -406,17 +403,15 @@ static int vmw_driver_unload(struct drm_device *dev)
        unregister_pm_notifier(&dev_priv->pm_nb);
-        if (!dev_priv->stealth) {
+        vmw_fb_close(dev_priv);
-                vmw_fb_close(dev_priv);
+        vmw_kms_close(dev_priv);
-                vmw_kms_close(dev_priv);
+        vmw_overlay_close(dev_priv);
-                vmw_overlay_close(dev_priv);
+        vmw_release_device(dev_priv);
-                vmw_release_device(dev_priv);
+        if (dev_priv->stealth)
-                pci_release_regions(dev->pdev);
-        } else {
-                vmw_kms_close(dev_priv);
-                vmw_overlay_close(dev_priv);
                pci_release_region(dev->pdev, 2);
-        }
+        else
+                pci_release_regions(dev->pdev);
        if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
                drm_irq_uninstall(dev_priv->dev);
        if (dev->devname == vmw_devname)
@@ -585,11 +580,6 @@ static int vmw_master_set(struct drm_device *dev,
        int ret = 0;
        DRM_INFO("Master set.\n");
-        if (dev_priv->stealth) {
-                ret = vmw_request_device(dev_priv);
-                if (unlikely(ret != 0))
-                        return ret;
-        }
        if (active) {
                BUG_ON(active != &dev_priv->fbdev_master);
@@ -649,18 +639,11 @@ static void vmw_master_drop(struct drm_device *dev,
        ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
-        if (dev_priv->stealth) {
-                ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
-                if (unlikely(ret != 0))
-                        DRM_ERROR("Unable to clean VRAM on master drop.\n");
-                vmw_release_device(dev_priv);
-        }
        dev_priv->active_master = &dev_priv->fbdev_master;
        ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
        ttm_vt_unlock(&dev_priv->fbdev_master.lock);
-        if (!dev_priv->stealth)
+        vmw_fb_on(dev_priv);
-                vmw_fb_on(dev_priv);
 }
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index 135be9688c90..356dc935ec13 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -39,10 +39,10 @@
 #include "ttm/ttm_execbuf_util.h"
 #include "ttm/ttm_module.h"
-#define VMWGFX_DRIVER_DATE "20090724"
+#define VMWGFX_DRIVER_DATE "20100209"
-#define VMWGFX_DRIVER_MAJOR 0
+#define VMWGFX_DRIVER_MAJOR 1
-#define VMWGFX_DRIVER_MINOR 1
+#define VMWGFX_DRIVER_MINOR 0
-#define VMWGFX_DRIVER_PATCHLEVEL 2
+#define VMWGFX_DRIVER_PATCHLEVEL 0
 #define VMWGFX_FILE_PAGE_OFFSET 0x00100000
 #define VMWGFX_FIFO_STATIC_SIZE (1024*1024)
 #define VMWGFX_MAX_RELOCATIONS 2048
@@ -113,6 +113,7 @@ struct vmw_fifo_state {
        unsigned long static_buffer_size;
        bool using_bounce_buffer;
        uint32_t capabilities;
+        struct mutex fifo_mutex;
        struct rw_semaphore rwsem;
 };
@@ -213,7 +214,7 @@ struct vmw_private {
         * Fencing and IRQs.
         */
-        uint32_t fence_seq;
+        atomic_t fence_seq;
        wait_queue_head_t fence_queue;
        wait_queue_head_t fifo_queue;
        atomic_t fence_queue_waiters;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index d69caf92ffe7..0897359b3e4e 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -182,25 +182,19 @@ static int vmw_cmd_present_check(struct vmw_private *dev_priv,
        return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.sid);
 }
-static int vmw_cmd_dma(struct vmw_private *dev_priv,
+static int vmw_translate_guest_ptr(struct vmw_private *dev_priv,
-                       struct vmw_sw_context *sw_context,
+                                   struct vmw_sw_context *sw_context,
-                       SVGA3dCmdHeader *header)
+                                   SVGAGuestPtr *ptr,
+                                   struct vmw_dma_buffer **vmw_bo_p)
 {
-        uint32_t handle;
        struct vmw_dma_buffer *vmw_bo = NULL;
        struct ttm_buffer_object *bo;
-        struct vmw_surface *srf = NULL;
+        uint32_t handle = ptr->gmrId;
-        struct vmw_dma_cmd {
-                SVGA3dCmdHeader header;
-                SVGA3dCmdSurfaceDMA dma;
-        } *cmd;
        struct vmw_relocation *reloc;
-        int ret;
        uint32_t cur_validate_node;
        struct ttm_validate_buffer *val_buf;
+        int ret;
-        cmd = container_of(header, struct vmw_dma_cmd, header);
-        handle = cmd->dma.guest.ptr.gmrId;
        ret = vmw_user_dmabuf_lookup(sw_context->tfile, handle, &vmw_bo);
        if (unlikely(ret != 0)) {
                DRM_ERROR("Could not find or use GMR region.\n");
@@ -209,14 +203,14 @@ static int vmw_cmd_dma(struct vmw_private *dev_priv,
        bo = &vmw_bo->base;
        if (unlikely(sw_context->cur_reloc >= VMWGFX_MAX_RELOCATIONS)) {
-                DRM_ERROR("Max number of DMA commands per submission"
+                DRM_ERROR("Max number relocations per submission"
                          " exceeded\n");
                ret = -EINVAL;
                goto out_no_reloc;
        }
        reloc = &sw_context->relocs[sw_context->cur_reloc++];
-        reloc->location = &cmd->dma.guest.ptr;
+        reloc->location = ptr;
        cur_validate_node = vmw_dmabuf_validate_node(bo, sw_context->cur_val_buf);
        if (unlikely(cur_validate_node >= VMWGFX_MAX_GMRS)) {
@@ -234,7 +228,89 @@ static int vmw_cmd_dma(struct vmw_private *dev_priv,
                list_add_tail(&val_buf->head, &sw_context->validate_nodes);
                ++sw_context->cur_val_buf;
        }
+        *vmw_bo_p = vmw_bo;
+        return 0;
+out_no_reloc:
+        vmw_dmabuf_unreference(&vmw_bo);
+        vmw_bo_p = NULL;
+        return ret;
+}
+static int vmw_cmd_end_query(struct vmw_private *dev_priv,
+                             struct vmw_sw_context *sw_context,
+                             SVGA3dCmdHeader *header)
+{
+        struct vmw_dma_buffer *vmw_bo;
+        struct vmw_query_cmd {
+                SVGA3dCmdHeader header;
+                SVGA3dCmdEndQuery q;
+        } *cmd;
+        int ret;
+        cmd = container_of(header, struct vmw_query_cmd, header);
+        ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
+        if (unlikely(ret != 0))
+                return ret;
+        ret = vmw_translate_guest_ptr(dev_priv, sw_context,
+                                      &cmd->q.guestResult,
+                                      &vmw_bo);
+        if (unlikely(ret != 0))
+                return ret;
+        vmw_dmabuf_unreference(&vmw_bo);
+        return 0;
+}
+static int vmw_cmd_wait_query(struct vmw_private *dev_priv,
+                              struct vmw_sw_context *sw_context,
+                              SVGA3dCmdHeader *header)
+{
+        struct vmw_dma_buffer *vmw_bo;
+        struct vmw_query_cmd {
+                SVGA3dCmdHeader header;
+                SVGA3dCmdWaitForQuery q;
+        } *cmd;
+        int ret;
+        cmd = container_of(header, struct vmw_query_cmd, header);
+        ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
+        if (unlikely(ret != 0))
+                return ret;
+        ret = vmw_translate_guest_ptr(dev_priv, sw_context,
+                                      &cmd->q.guestResult,
+                                      &vmw_bo);
+        if (unlikely(ret != 0))
+                return ret;
+        vmw_dmabuf_unreference(&vmw_bo);
+        return 0;
+}
+static int vmw_cmd_dma(struct vmw_private *dev_priv,
+                       struct vmw_sw_context *sw_context,
+                       SVGA3dCmdHeader *header)
+{
+        struct vmw_dma_buffer *vmw_bo = NULL;
+        struct ttm_buffer_object *bo;
+        struct vmw_surface *srf = NULL;
+        struct vmw_dma_cmd {
+                SVGA3dCmdHeader header;
+                SVGA3dCmdSurfaceDMA dma;
+        } *cmd;
+        int ret;
+        cmd = container_of(header, struct vmw_dma_cmd, header);
+        ret = vmw_translate_guest_ptr(dev_priv, sw_context,
+                                      &cmd->dma.guest.ptr,
+                                      &vmw_bo);
+        if (unlikely(ret != 0))
+                return ret;
+        bo = &vmw_bo->base;
        ret = vmw_user_surface_lookup_handle(dev_priv, sw_context->tfile,
                                             cmd->dma.host.sid, &srf);
        if (ret) {
@@ -379,8 +455,8 @@ static vmw_cmd_func vmw_cmd_funcs[SVGA_3D_CMD_MAX] = {
        VMW_CMD_DEF(SVGA_3D_CMD_DRAW_PRIMITIVES, &vmw_cmd_draw),
        VMW_CMD_DEF(SVGA_3D_CMD_SETSCISSORRECT, &vmw_cmd_cid_check),
        VMW_CMD_DEF(SVGA_3D_CMD_BEGIN_QUERY, &vmw_cmd_cid_check),
-        VMW_CMD_DEF(SVGA_3D_CMD_END_QUERY, &vmw_cmd_cid_check),
+        VMW_CMD_DEF(SVGA_3D_CMD_END_QUERY, &vmw_cmd_end_query),
-        VMW_CMD_DEF(SVGA_3D_CMD_WAIT_FOR_QUERY, &vmw_cmd_cid_check),
+        VMW_CMD_DEF(SVGA_3D_CMD_WAIT_FOR_QUERY, &vmw_cmd_wait_query),
        VMW_CMD_DEF(SVGA_3D_CMD_PRESENT_READBACK, &vmw_cmd_ok),
        VMW_CMD_DEF(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN,
                    &vmw_cmd_blt_surf_screen_check)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
index 4f4f6432be8b..a93367041cdc 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
@@ -559,6 +559,9 @@ int vmw_fb_init(struct vmw_private *vmw_priv)
        info->pixmap.scan_align = 1;
 #endif
+        info->aperture_base = vmw_priv->vram_start;
+        info->aperture_size = vmw_priv->vram_size;
        /*
         * Dirty & Deferred IO
         */
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
index 4157547cc6e4..39d43a01d846 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
@@ -74,6 +74,7 @@ int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
        fifo->reserved_size = 0;
        fifo->using_bounce_buffer = false;
+        mutex_init(&fifo->fifo_mutex);
        init_rwsem(&fifo->rwsem);
        /*
@@ -117,7 +118,7 @@ int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
                 (unsigned int) min,
                 (unsigned int) fifo->capabilities);
-        dev_priv->fence_seq = dev_priv->last_read_sequence;
+        atomic_set(&dev_priv->fence_seq, dev_priv->last_read_sequence);
        iowrite32(dev_priv->last_read_sequence, fifo_mem + SVGA_FIFO_FENCE);
        return vmw_fifo_send_fence(dev_priv, &dummy);
@@ -283,7 +284,7 @@ void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
        uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
        int ret;
-        down_write(&fifo_state->rwsem);
+        mutex_lock(&fifo_state->fifo_mutex);
        max = ioread32(fifo_mem + SVGA_FIFO_MAX);
        min = ioread32(fifo_mem + SVGA_FIFO_MIN);
        next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
@@ -351,7 +352,7 @@ void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
        }
 out_err:
        fifo_state->reserved_size = 0;
-        up_write(&fifo_state->rwsem);
+        mutex_unlock(&fifo_state->fifo_mutex);
        return NULL;
 }
@@ -426,6 +427,7 @@ void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
        }
+        down_write(&fifo_state->rwsem);
        if (fifo_state->using_bounce_buffer || reserveable) {
                next_cmd += bytes;
                if (next_cmd >= max)
@@ -437,8 +439,9 @@ void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
        if (reserveable)
                iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
        mb();
-        vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
        up_write(&fifo_state->rwsem);
+        vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
+        mutex_unlock(&fifo_state->fifo_mutex);
 }
 int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *sequence)
@@ -451,9 +454,7 @@ int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *sequence)
        fm = vmw_fifo_reserve(dev_priv, bytes);
        if (unlikely(fm == NULL)) {
-                down_write(&fifo_state->rwsem);
+                *sequence = atomic_read(&dev_priv->fence_seq);
-                *sequence = dev_priv->fence_seq;
-                up_write(&fifo_state->rwsem);
                ret = -ENOMEM;
                (void)vmw_fallback_wait(dev_priv, false, true, *sequence,
                                        false, 3*HZ);
@@ -461,7 +462,7 @@ int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *sequence)
        }
        do {
-                *sequence = dev_priv->fence_seq++;
+                *sequence = atomic_add_return(1, &dev_priv->fence_seq);
        } while (*sequence == 0);
        if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
index 778851f9f1d6..1c7a316454d8 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
@@ -48,6 +48,12 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
        case DRM_VMW_PARAM_FIFO_OFFSET:
                param->value = dev_priv->mmio_start;
                break;
+        case DRM_VMW_PARAM_HW_CAPS:
+                param->value = dev_priv->capabilities;
+                break;
+        case DRM_VMW_PARAM_FIFO_CAPS:
+                param->value = dev_priv->fifo.capabilities;
+                break;
        default:
                DRM_ERROR("Illegal vmwgfx get param request: %d\n",
                          param->param);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c b/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c
index d40086fc8647..4d7cb5393860 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c
@@ -85,19 +85,12 @@ bool vmw_fence_signaled(struct vmw_private *dev_priv,
                return true;
        /**
-         * Below is to signal stale fences that have wrapped.
-         * First, block fence submission.
-         */
-        down_read(&fifo_state->rwsem);
-        /**
         * Then check if the sequence is higher than what we've actually
         * emitted. Then the fence is stale and signaled.
         */
-        ret = ((dev_priv->fence_seq - sequence) > VMW_FENCE_WRAP);
+        ret = ((atomic_read(&dev_priv->fence_seq) - sequence)
-        up_read(&fifo_state->rwsem);
+               > VMW_FENCE_WRAP);
        return ret;
 }
@@ -127,7 +120,7 @@ int vmw_fallback_wait(struct vmw_private *dev_priv,
        if (fifo_idle)
                down_read(&fifo_state->rwsem);
-        signal_seq = dev_priv->fence_seq;
+        signal_seq = atomic_read(&dev_priv->fence_seq);
        ret = 0;
        for (;;) {
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index eeba6d1d06e4..31f9afed0a63 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -769,10 +769,10 @@ int vmw_kms_init(struct vmw_private *dev_priv)
        drm_mode_config_init(dev);
        dev->mode_config.funcs = &vmw_kms_funcs;
-        dev->mode_config.min_width = 640;
+        dev->mode_config.min_width = 1;
-        dev->mode_config.min_height = 480;
+        dev->mode_config.min_height = 1;
-        dev->mode_config.max_width = 2048;
+        dev->mode_config.max_width = dev_priv->fb_max_width;
-        dev->mode_config.max_height = 2048;
+        dev->mode_config.max_height = dev_priv->fb_max_height;
        ret = vmw_kms_init_legacy_display_system(dev_priv);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
index c7efbd47ab84..f8fbbc67a406 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
@@ -35,11 +35,6 @@
 #define VMW_RES_SURFACE ttm_driver_type1
 #define VMW_RES_STREAM ttm_driver_type2
-/* XXX: This isn't a real hardware flag, but just a hack for kernel to
- * know about primary surfaces. Find a better way to accomplish this.
- */
-#define SVGA3D_SURFACE_HINT_SCANOUT (1 << 9)
 struct vmw_user_context {
        struct ttm_base_object base;
        struct vmw_resource res;
@@ -579,6 +574,7 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
        srf->flags = req->flags;
        srf->format = req->format;
+        srf->scanout = req->scanout;
        memcpy(srf->mip_levels, req->mip_levels, sizeof(srf->mip_levels));
        srf->num_sizes = 0;
        for (i = 0; i < DRM_VMW_MAX_SURFACE_FACES; ++i)
@@ -604,16 +600,6 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
        if (unlikely(ret != 0))
                goto out_err1;
-        if (srf->flags & SVGA3D_SURFACE_HINT_SCANOUT) {
-                /* we should not send this flag down to hardware since
-                 * its not a official one
-                 */
-                srf->flags &= ~SVGA3D_SURFACE_HINT_SCANOUT;
-                srf->scanout = true;
-        } else {
-                srf->scanout = false;
-        }
        if (srf->scanout &&
            srf->num_sizes == 1 &&
            srf->sizes[0].width == 64 &&