diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/rv515d.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/rv515d.h | 385 |
1 files changed, 384 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/rv515d.h b/drivers/gpu/drm/radeon/rv515d.h index a65e17ec1c08..fc216e49384d 100644 --- a/drivers/gpu/drm/radeon/rv515d.h +++ b/drivers/gpu/drm/radeon/rv515d.h | |||
| @@ -216,5 +216,388 @@ | |||
| 216 | #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) | 216 | #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) |
| 217 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) | 217 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
| 218 | 218 | ||
| 219 | #endif | 219 | /* Registers */ |
| 220 | #define R_0000F8_CONFIG_MEMSIZE 0x0000F8 | ||
| 221 | #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) | ||
| 222 | #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) | ||
| 223 | #define C_0000F8_CONFIG_MEMSIZE 0x00000000 | ||
| 224 | #define R_000134_HDP_FB_LOCATION 0x000134 | ||
| 225 | #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) | ||
| 226 | #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) | ||
| 227 | #define C_000134_HDP_FB_START 0xFFFF0000 | ||
| 228 | #define R_000300_VGA_RENDER_CONTROL 0x000300 | ||
| 229 | #define S_000300_VGA_BLINK_RATE(x) (((x) & 0x1F) << 0) | ||
| 230 | #define G_000300_VGA_BLINK_RATE(x) (((x) >> 0) & 0x1F) | ||
| 231 | #define C_000300_VGA_BLINK_RATE 0xFFFFFFE0 | ||
| 232 | #define S_000300_VGA_BLINK_MODE(x) (((x) & 0x3) << 5) | ||
| 233 | #define G_000300_VGA_BLINK_MODE(x) (((x) >> 5) & 0x3) | ||
| 234 | #define C_000300_VGA_BLINK_MODE 0xFFFFFF9F | ||
| 235 | #define S_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) & 0x1) << 7) | ||
| 236 | #define G_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) >> 7) & 0x1) | ||
| 237 | #define C_000300_VGA_CURSOR_BLINK_INVERT 0xFFFFFF7F | ||
| 238 | #define S_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) & 0x1) << 8) | ||
| 239 | #define G_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) >> 8) & 0x1) | ||
| 240 | #define C_000300_VGA_EXTD_ADDR_COUNT_ENABLE 0xFFFFFEFF | ||
| 241 | #define S_000300_VGA_VSTATUS_CNTL(x) (((x) & 0x3) << 16) | ||
| 242 | #define G_000300_VGA_VSTATUS_CNTL(x) (((x) >> 16) & 0x3) | ||
| 243 | #define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF | ||
| 244 | #define S_000300_VGA_LOCK_8DOT(x) (((x) & 0x1) << 24) | ||
| 245 | #define G_000300_VGA_LOCK_8DOT(x) (((x) >> 24) & 0x1) | ||
| 246 | #define C_000300_VGA_LOCK_8DOT 0xFEFFFFFF | ||
| 247 | #define S_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) & 0x1) << 25) | ||
| 248 | #define G_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) >> 25) & 0x1) | ||
| 249 | #define C_000300_VGAREG_LINECMP_COMPATIBILITY_SEL 0xFDFFFFFF | ||
| 250 | #define R_000310_VGA_MEMORY_BASE_ADDRESS 0x000310 | ||
| 251 | #define S_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) | ||
| 252 | #define G_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) | ||
| 253 | #define C_000310_VGA_MEMORY_BASE_ADDRESS 0x00000000 | ||
| 254 | #define R_000328_VGA_HDP_CONTROL 0x000328 | ||
| 255 | #define S_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) & 0x1) << 0) | ||
| 256 | #define G_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) >> 0) & 0x1) | ||
| 257 | #define C_000328_VGA_MEM_PAGE_SELECT_EN 0xFFFFFFFE | ||
| 258 | #define S_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) & 0x1) << 8) | ||
| 259 | #define G_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) >> 8) & 0x1) | ||
| 260 | #define C_000328_VGA_RBBM_LOCK_DISABLE 0xFFFFFEFF | ||
| 261 | #define S_000328_VGA_SOFT_RESET(x) (((x) & 0x1) << 16) | ||
| 262 | #define G_000328_VGA_SOFT_RESET(x) (((x) >> 16) & 0x1) | ||
| 263 | #define C_000328_VGA_SOFT_RESET 0xFFFEFFFF | ||
| 264 | #define S_000328_VGA_TEST_RESET_CONTROL(x) (((x) & 0x1) << 24) | ||
| 265 | #define G_000328_VGA_TEST_RESET_CONTROL(x) (((x) >> 24) & 0x1) | ||
| 266 | #define C_000328_VGA_TEST_RESET_CONTROL 0xFEFFFFFF | ||
| 267 | #define R_000330_D1VGA_CONTROL 0x000330 | ||
| 268 | #define S_000330_D1VGA_MODE_ENABLE(x) (((x) & 0x1) << 0) | ||
| 269 | #define G_000330_D1VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1) | ||
| 270 | #define C_000330_D1VGA_MODE_ENABLE 0xFFFFFFFE | ||
| 271 | #define S_000330_D1VGA_TIMING_SELECT(x) (((x) & 0x1) << 8) | ||
| 272 | #define G_000330_D1VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1) | ||
| 273 | #define C_000330_D1VGA_TIMING_SELECT 0xFFFFFEFF | ||
| 274 | #define S_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9) | ||
| 275 | #define G_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1) | ||
| 276 | #define C_000330_D1VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF | ||
| 277 | #define S_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10) | ||
| 278 | #define G_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1) | ||
| 279 | #define C_000330_D1VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF | ||
| 280 | #define S_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16) | ||
| 281 | #define G_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1) | ||
| 282 | #define C_000330_D1VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF | ||
| 283 | #define S_000330_D1VGA_ROTATE(x) (((x) & 0x3) << 24) | ||
| 284 | #define G_000330_D1VGA_ROTATE(x) (((x) >> 24) & 0x3) | ||
| 285 | #define C_000330_D1VGA_ROTATE 0xFCFFFFFF | ||
| 286 | #define R_000338_D2VGA_CONTROL 0x000338 | ||
| 287 | #define S_000338_D2VGA_MODE_ENABLE(x) (((x) & 0x1) << 0) | ||
| 288 | #define G_000338_D2VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1) | ||
| 289 | #define C_000338_D2VGA_MODE_ENABLE 0xFFFFFFFE | ||
| 290 | #define S_000338_D2VGA_TIMING_SELECT(x) (((x) & 0x1) << 8) | ||
| 291 | #define G_000338_D2VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1) | ||
| 292 | #define C_000338_D2VGA_TIMING_SELECT 0xFFFFFEFF | ||
| 293 | #define S_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9) | ||
| 294 | #define G_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1) | ||
| 295 | #define C_000338_D2VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF | ||
| 296 | #define S_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10) | ||
| 297 | #define G_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1) | ||
| 298 | #define C_000338_D2VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF | ||
| 299 | #define S_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16) | ||
| 300 | #define G_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1) | ||
| 301 | #define C_000338_D2VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF | ||
| 302 | #define S_000338_D2VGA_ROTATE(x) (((x) & 0x3) << 24) | ||
| 303 | #define G_000338_D2VGA_ROTATE(x) (((x) >> 24) & 0x3) | ||
| 304 | #define C_000338_D2VGA_ROTATE 0xFCFFFFFF | ||
| 305 | #define R_0007C0_CP_STAT 0x0007C0 | ||
| 306 | #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) | ||
| 307 | #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) | ||
| 308 | #define C_0007C0_MRU_BUSY 0xFFFFFFFE | ||
| 309 | #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) | ||
| 310 | #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) | ||
| 311 | #define C_0007C0_MWU_BUSY 0xFFFFFFFD | ||
| 312 | #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) | ||
| 313 | #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) | ||
| 314 | #define C_0007C0_RSIU_BUSY 0xFFFFFFFB | ||
| 315 | #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) | ||
| 316 | #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) | ||
| 317 | #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 | ||
| 318 | #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) | ||
| 319 | #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) | ||
| 320 | #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF | ||
| 321 | #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) | ||
| 322 | #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) | ||
| 323 | #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF | ||
| 324 | #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) | ||
| 325 | #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) | ||
| 326 | #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF | ||
| 327 | #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) | ||
| 328 | #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) | ||
| 329 | #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF | ||
| 330 | #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) | ||
| 331 | #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) | ||
| 332 | #define C_0007C0_CSI_BUSY 0xFFFFDFFF | ||
| 333 | #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) | ||
| 334 | #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) | ||
| 335 | #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF | ||
| 336 | #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) | ||
| 337 | #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) | ||
| 338 | #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF | ||
| 339 | #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) | ||
| 340 | #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) | ||
| 341 | #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF | ||
| 342 | #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) | ||
| 343 | #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) | ||
| 344 | #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF | ||
| 345 | #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) | ||
| 346 | #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) | ||
| 347 | #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF | ||
| 348 | #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) | ||
| 349 | #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) | ||
| 350 | #define C_0007C0_CP_BUSY 0x7FFFFFFF | ||
| 351 | #define R_000E40_RBBM_STATUS 0x000E40 | ||
| 352 | #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) | ||
| 353 | #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) | ||
| 354 | #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 | ||
| 355 | #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) | ||
| 356 | #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) | ||
| 357 | #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF | ||
| 358 | #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) | ||
| 359 | #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) | ||
| 360 | #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF | ||
| 361 | #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) | ||
| 362 | #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) | ||
| 363 | #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF | ||
| 364 | #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) | ||
| 365 | #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) | ||
| 366 | #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF | ||
| 367 | #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) | ||
| 368 | #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) | ||
| 369 | #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF | ||
| 370 | #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) | ||
| 371 | #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) | ||
| 372 | #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF | ||
| 373 | #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) | ||
| 374 | #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) | ||
| 375 | #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF | ||
| 376 | #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) | ||
| 377 | #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) | ||
| 378 | #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF | ||
| 379 | #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) | ||
| 380 | #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) | ||
| 381 | #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF | ||
| 382 | #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) | ||
| 383 | #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) | ||
| 384 | #define C_000E40_E2_BUSY 0xFFFDFFFF | ||
| 385 | #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) | ||
| 386 | #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) | ||
| 387 | #define C_000E40_RB2D_BUSY 0xFFFBFFFF | ||
| 388 | #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) | ||
| 389 | #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) | ||
| 390 | #define C_000E40_RB3D_BUSY 0xFFF7FFFF | ||
| 391 | #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) | ||
| 392 | #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) | ||
| 393 | #define C_000E40_VAP_BUSY 0xFFEFFFFF | ||
| 394 | #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) | ||
| 395 | #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) | ||
| 396 | #define C_000E40_RE_BUSY 0xFFDFFFFF | ||
| 397 | #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) | ||
| 398 | #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) | ||
| 399 | #define C_000E40_TAM_BUSY 0xFFBFFFFF | ||
| 400 | #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) | ||
| 401 | #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) | ||
| 402 | #define C_000E40_TDM_BUSY 0xFF7FFFFF | ||
| 403 | #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) | ||
| 404 | #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) | ||
| 405 | #define C_000E40_PB_BUSY 0xFEFFFFFF | ||
| 406 | #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) | ||
| 407 | #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) | ||
| 408 | #define C_000E40_TIM_BUSY 0xFDFFFFFF | ||
| 409 | #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) | ||
| 410 | #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) | ||
| 411 | #define C_000E40_GA_BUSY 0xFBFFFFFF | ||
| 412 | #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) | ||
| 413 | #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) | ||
| 414 | #define C_000E40_CBA2D_BUSY 0xF7FFFFFF | ||
| 415 | #define S_000E40_RBBM_HIBUSY(x) (((x) & 0x1) << 28) | ||
| 416 | #define G_000E40_RBBM_HIBUSY(x) (((x) >> 28) & 0x1) | ||
| 417 | #define C_000E40_RBBM_HIBUSY 0xEFFFFFFF | ||
| 418 | #define S_000E40_SKID_CFBUSY(x) (((x) & 0x1) << 29) | ||
| 419 | #define G_000E40_SKID_CFBUSY(x) (((x) >> 29) & 0x1) | ||
| 420 | #define C_000E40_SKID_CFBUSY 0xDFFFFFFF | ||
| 421 | #define S_000E40_VAP_VF_BUSY(x) (((x) & 0x1) << 30) | ||
| 422 | #define G_000E40_VAP_VF_BUSY(x) (((x) >> 30) & 0x1) | ||
| 423 | #define C_000E40_VAP_VF_BUSY 0xBFFFFFFF | ||
| 424 | #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) | ||
| 425 | #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) | ||
| 426 | #define C_000E40_GUI_ACTIVE 0x7FFFFFFF | ||
| 427 | #define R_006080_D1CRTC_CONTROL 0x006080 | ||
| 428 | #define S_006080_D1CRTC_MASTER_EN(x) (((x) & 0x1) << 0) | ||
| 429 | #define G_006080_D1CRTC_MASTER_EN(x) (((x) >> 0) & 0x1) | ||
| 430 | #define C_006080_D1CRTC_MASTER_EN 0xFFFFFFFE | ||
| 431 | #define S_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4) | ||
| 432 | #define G_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1) | ||
| 433 | #define C_006080_D1CRTC_SYNC_RESET_SEL 0xFFFFFFEF | ||
| 434 | #define S_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8) | ||
| 435 | #define G_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3) | ||
| 436 | #define C_006080_D1CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF | ||
| 437 | #define S_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16) | ||
| 438 | #define G_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1) | ||
| 439 | #define C_006080_D1CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF | ||
| 440 | #define S_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24) | ||
| 441 | #define G_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1) | ||
| 442 | #define C_006080_D1CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF | ||
| 443 | #define R_0060E8_D1CRTC_UPDATE_LOCK 0x0060E8 | ||
| 444 | #define S_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0) | ||
| 445 | #define G_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1) | ||
| 446 | #define C_0060E8_D1CRTC_UPDATE_LOCK 0xFFFFFFFE | ||
| 447 | #define R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x006110 | ||
| 448 | #define S_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) | ||
| 449 | #define G_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) | ||
| 450 | #define C_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000 | ||
| 451 | #define R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x006118 | ||
| 452 | #define S_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) | ||
| 453 | #define G_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) | ||
| 454 | #define C_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000 | ||
| 455 | #define R_006880_D2CRTC_CONTROL 0x006880 | ||
| 456 | #define S_006880_D2CRTC_MASTER_EN(x) (((x) & 0x1) << 0) | ||
| 457 | #define G_006880_D2CRTC_MASTER_EN(x) (((x) >> 0) & 0x1) | ||
| 458 | #define C_006880_D2CRTC_MASTER_EN 0xFFFFFFFE | ||
| 459 | #define S_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4) | ||
| 460 | #define G_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1) | ||
| 461 | #define C_006880_D2CRTC_SYNC_RESET_SEL 0xFFFFFFEF | ||
| 462 | #define S_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8) | ||
| 463 | #define G_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3) | ||
| 464 | #define C_006880_D2CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF | ||
| 465 | #define S_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16) | ||
| 466 | #define G_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1) | ||
| 467 | #define C_006880_D2CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF | ||
| 468 | #define S_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24) | ||
| 469 | #define G_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1) | ||
| 470 | #define C_006880_D2CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF | ||
| 471 | #define R_0068E8_D2CRTC_UPDATE_LOCK 0x0068E8 | ||
| 472 | #define S_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0) | ||
| 473 | #define G_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1) | ||
| 474 | #define C_0068E8_D2CRTC_UPDATE_LOCK 0xFFFFFFFE | ||
| 475 | #define R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x006910 | ||
| 476 | #define S_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) | ||
| 477 | #define G_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) | ||
| 478 | #define C_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000 | ||
| 479 | #define R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x006918 | ||
| 480 | #define S_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) | ||
| 481 | #define G_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) | ||
| 482 | #define C_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000 | ||
| 483 | |||
| 484 | |||
| 485 | #define R_000001_MC_FB_LOCATION 0x000001 | ||
| 486 | #define S_000001_MC_FB_START(x) (((x) & 0xFFFF) << 0) | ||
| 487 | #define G_000001_MC_FB_START(x) (((x) >> 0) & 0xFFFF) | ||
| 488 | #define C_000001_MC_FB_START 0xFFFF0000 | ||
| 489 | #define S_000001_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) | ||
| 490 | #define G_000001_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) | ||
| 491 | #define C_000001_MC_FB_TOP 0x0000FFFF | ||
| 492 | #define R_000002_MC_AGP_LOCATION 0x000002 | ||
| 493 | #define S_000002_MC_AGP_START(x) (((x) & 0xFFFF) << 0) | ||
| 494 | #define G_000002_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) | ||
| 495 | #define C_000002_MC_AGP_START 0xFFFF0000 | ||
| 496 | #define S_000002_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) | ||
| 497 | #define G_000002_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) | ||
| 498 | #define C_000002_MC_AGP_TOP 0x0000FFFF | ||
| 499 | #define R_000003_MC_AGP_BASE 0x000003 | ||
| 500 | #define S_000003_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) | ||
| 501 | #define G_000003_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) | ||
| 502 | #define C_000003_AGP_BASE_ADDR 0x00000000 | ||
| 503 | #define R_000004_MC_AGP_BASE_2 0x000004 | ||
| 504 | #define S_000004_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) | ||
| 505 | #define G_000004_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) | ||
| 506 | #define C_000004_AGP_BASE_ADDR_2 0xFFFFFFF0 | ||
| 220 | 507 | ||
| 508 | |||
| 509 | #define R_00000F_CP_DYN_CNTL 0x00000F | ||
| 510 | #define S_00000F_CP_FORCEON(x) (((x) & 0x1) << 0) | ||
| 511 | #define G_00000F_CP_FORCEON(x) (((x) >> 0) & 0x1) | ||
| 512 | #define C_00000F_CP_FORCEON 0xFFFFFFFE | ||
| 513 | #define S_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) | ||
| 514 | #define G_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) | ||
| 515 | #define C_00000F_CP_MAX_DYN_STOP_LAT 0xFFFFFFFD | ||
| 516 | #define S_00000F_CP_CLOCK_STATUS(x) (((x) & 0x1) << 2) | ||
| 517 | #define G_00000F_CP_CLOCK_STATUS(x) (((x) >> 2) & 0x1) | ||
| 518 | #define C_00000F_CP_CLOCK_STATUS 0xFFFFFFFB | ||
| 519 | #define S_00000F_CP_PROG_SHUTOFF(x) (((x) & 0x1) << 3) | ||
| 520 | #define G_00000F_CP_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) | ||
| 521 | #define C_00000F_CP_PROG_SHUTOFF 0xFFFFFFF7 | ||
| 522 | #define S_00000F_CP_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) | ||
| 523 | #define G_00000F_CP_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) | ||
| 524 | #define C_00000F_CP_PROG_DELAY_VALUE 0xFFFFF00F | ||
| 525 | #define S_00000F_CP_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) | ||
| 526 | #define G_00000F_CP_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) | ||
| 527 | #define C_00000F_CP_LOWER_POWER_IDLE 0xFFF00FFF | ||
| 528 | #define S_00000F_CP_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) | ||
| 529 | #define G_00000F_CP_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) | ||
| 530 | #define C_00000F_CP_LOWER_POWER_IGNORE 0xFFEFFFFF | ||
| 531 | #define S_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) | ||
| 532 | #define G_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) | ||
| 533 | #define C_00000F_CP_NORMAL_POWER_IGNORE 0xFFDFFFFF | ||
| 534 | #define S_00000F_SPARE(x) (((x) & 0x3) << 22) | ||
| 535 | #define G_00000F_SPARE(x) (((x) >> 22) & 0x3) | ||
| 536 | #define C_00000F_SPARE 0xFF3FFFFF | ||
| 537 | #define S_00000F_CP_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) | ||
| 538 | #define G_00000F_CP_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) | ||
| 539 | #define C_00000F_CP_NORMAL_POWER_BUSY 0x00FFFFFF | ||
| 540 | #define R_000011_E2_DYN_CNTL 0x000011 | ||
| 541 | #define S_000011_E2_FORCEON(x) (((x) & 0x1) << 0) | ||
| 542 | #define G_000011_E2_FORCEON(x) (((x) >> 0) & 0x1) | ||
| 543 | #define C_000011_E2_FORCEON 0xFFFFFFFE | ||
| 544 | #define S_000011_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) | ||
| 545 | #define G_000011_E2_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) | ||
| 546 | #define C_000011_E2_MAX_DYN_STOP_LAT 0xFFFFFFFD | ||
| 547 | #define S_000011_E2_CLOCK_STATUS(x) (((x) & 0x1) << 2) | ||
| 548 | #define G_000011_E2_CLOCK_STATUS(x) (((x) >> 2) & 0x1) | ||
| 549 | #define C_000011_E2_CLOCK_STATUS 0xFFFFFFFB | ||
| 550 | #define S_000011_E2_PROG_SHUTOFF(x) (((x) & 0x1) << 3) | ||
| 551 | #define G_000011_E2_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) | ||
| 552 | #define C_000011_E2_PROG_SHUTOFF 0xFFFFFFF7 | ||
| 553 | #define S_000011_E2_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) | ||
| 554 | #define G_000011_E2_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) | ||
| 555 | #define C_000011_E2_PROG_DELAY_VALUE 0xFFFFF00F | ||
| 556 | #define S_000011_E2_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) | ||
| 557 | #define G_000011_E2_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) | ||
| 558 | #define C_000011_E2_LOWER_POWER_IDLE 0xFFF00FFF | ||
| 559 | #define S_000011_E2_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) | ||
| 560 | #define G_000011_E2_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) | ||
| 561 | #define C_000011_E2_LOWER_POWER_IGNORE 0xFFEFFFFF | ||
| 562 | #define S_000011_E2_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) | ||
| 563 | #define G_000011_E2_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) | ||
| 564 | #define C_000011_E2_NORMAL_POWER_IGNORE 0xFFDFFFFF | ||
| 565 | #define S_000011_SPARE(x) (((x) & 0x3) << 22) | ||
| 566 | #define G_000011_SPARE(x) (((x) >> 22) & 0x3) | ||
| 567 | #define C_000011_SPARE 0xFF3FFFFF | ||
| 568 | #define S_000011_E2_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) | ||
| 569 | #define G_000011_E2_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) | ||
| 570 | #define C_000011_E2_NORMAL_POWER_BUSY 0x00FFFFFF | ||
| 571 | #define R_000013_IDCT_DYN_CNTL 0x000013 | ||
| 572 | #define S_000013_IDCT_FORCEON(x) (((x) & 0x1) << 0) | ||
| 573 | #define G_000013_IDCT_FORCEON(x) (((x) >> 0) & 0x1) | ||
| 574 | #define C_000013_IDCT_FORCEON 0xFFFFFFFE | ||
| 575 | #define S_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) | ||
| 576 | #define G_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) | ||
| 577 | #define C_000013_IDCT_MAX_DYN_STOP_LAT 0xFFFFFFFD | ||
| 578 | #define S_000013_IDCT_CLOCK_STATUS(x) (((x) & 0x1) << 2) | ||
| 579 | #define G_000013_IDCT_CLOCK_STATUS(x) (((x) >> 2) & 0x1) | ||
| 580 | #define C_000013_IDCT_CLOCK_STATUS 0xFFFFFFFB | ||
| 581 | #define S_000013_IDCT_PROG_SHUTOFF(x) (((x) & 0x1) << 3) | ||
| 582 | #define G_000013_IDCT_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) | ||
| 583 | #define C_000013_IDCT_PROG_SHUTOFF 0xFFFFFFF7 | ||
| 584 | #define S_000013_IDCT_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) | ||
| 585 | #define G_000013_IDCT_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) | ||
| 586 | #define C_000013_IDCT_PROG_DELAY_VALUE 0xFFFFF00F | ||
| 587 | #define S_000013_IDCT_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) | ||
| 588 | #define G_000013_IDCT_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) | ||
| 589 | #define C_000013_IDCT_LOWER_POWER_IDLE 0xFFF00FFF | ||
| 590 | #define S_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) | ||
| 591 | #define G_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) | ||
| 592 | #define C_000013_IDCT_LOWER_POWER_IGNORE 0xFFEFFFFF | ||
| 593 | #define S_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) | ||
| 594 | #define G_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) | ||
| 595 | #define C_000013_IDCT_NORMAL_POWER_IGNORE 0xFFDFFFFF | ||
| 596 | #define S_000013_SPARE(x) (((x) & 0x3) << 22) | ||
| 597 | #define G_000013_SPARE(x) (((x) >> 22) & 0x3) | ||
| 598 | #define C_000013_SPARE 0xFF3FFFFF | ||
| 599 | #define S_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) | ||
| 600 | #define G_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) | ||
| 601 | #define C_000013_IDCT_NORMAL_POWER_BUSY 0x00FFFFFF | ||
| 602 | |||
| 603 | #endif | ||