diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_mode.h')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_mode.h | 56 |
1 files changed, 20 insertions, 36 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 402369db5ba0..e81b2aeb6a8f 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h | |||
@@ -46,32 +46,6 @@ struct radeon_device; | |||
46 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) | 46 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) |
47 | #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) | 47 | #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) |
48 | 48 | ||
49 | enum radeon_connector_type { | ||
50 | CONNECTOR_NONE, | ||
51 | CONNECTOR_VGA, | ||
52 | CONNECTOR_DVI_I, | ||
53 | CONNECTOR_DVI_D, | ||
54 | CONNECTOR_DVI_A, | ||
55 | CONNECTOR_STV, | ||
56 | CONNECTOR_CTV, | ||
57 | CONNECTOR_LVDS, | ||
58 | CONNECTOR_DIGITAL, | ||
59 | CONNECTOR_SCART, | ||
60 | CONNECTOR_HDMI_TYPE_A, | ||
61 | CONNECTOR_HDMI_TYPE_B, | ||
62 | CONNECTOR_0XC, | ||
63 | CONNECTOR_0XD, | ||
64 | CONNECTOR_DIN, | ||
65 | CONNECTOR_DISPLAY_PORT, | ||
66 | CONNECTOR_UNSUPPORTED | ||
67 | }; | ||
68 | |||
69 | enum radeon_dvi_type { | ||
70 | DVI_AUTO, | ||
71 | DVI_DIGITAL, | ||
72 | DVI_ANALOG | ||
73 | }; | ||
74 | |||
75 | enum radeon_rmx_type { | 49 | enum radeon_rmx_type { |
76 | RMX_OFF, | 50 | RMX_OFF, |
77 | RMX_FULL, | 51 | RMX_FULL, |
@@ -151,16 +125,24 @@ struct radeon_tmds_pll { | |||
151 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) | 125 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
152 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) | 126 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) |
153 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) | 127 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
128 | #define RADEON_PLL_USE_POST_DIV (1 << 12) | ||
154 | 129 | ||
155 | struct radeon_pll { | 130 | struct radeon_pll { |
156 | uint16_t reference_freq; | 131 | /* reference frequency */ |
157 | uint16_t reference_div; | 132 | uint32_t reference_freq; |
133 | |||
134 | /* fixed dividers */ | ||
135 | uint32_t reference_div; | ||
136 | uint32_t post_div; | ||
137 | |||
138 | /* pll in/out limits */ | ||
158 | uint32_t pll_in_min; | 139 | uint32_t pll_in_min; |
159 | uint32_t pll_in_max; | 140 | uint32_t pll_in_max; |
160 | uint32_t pll_out_min; | 141 | uint32_t pll_out_min; |
161 | uint32_t pll_out_max; | 142 | uint32_t pll_out_max; |
162 | uint16_t xclk; | 143 | uint32_t best_vco; |
163 | 144 | ||
145 | /* divider limits */ | ||
164 | uint32_t min_ref_div; | 146 | uint32_t min_ref_div; |
165 | uint32_t max_ref_div; | 147 | uint32_t max_ref_div; |
166 | uint32_t min_post_div; | 148 | uint32_t min_post_div; |
@@ -169,7 +151,12 @@ struct radeon_pll { | |||
169 | uint32_t max_feedback_div; | 151 | uint32_t max_feedback_div; |
170 | uint32_t min_frac_feedback_div; | 152 | uint32_t min_frac_feedback_div; |
171 | uint32_t max_frac_feedback_div; | 153 | uint32_t max_frac_feedback_div; |
172 | uint32_t best_vco; | 154 | |
155 | /* flags for the current clock */ | ||
156 | uint32_t flags; | ||
157 | |||
158 | /* pll id */ | ||
159 | uint32_t id; | ||
173 | }; | 160 | }; |
174 | 161 | ||
175 | struct radeon_i2c_chan { | 162 | struct radeon_i2c_chan { |
@@ -312,7 +299,7 @@ struct radeon_atom_ss { | |||
312 | struct radeon_encoder_atom_dig { | 299 | struct radeon_encoder_atom_dig { |
313 | /* atom dig */ | 300 | /* atom dig */ |
314 | bool coherent_mode; | 301 | bool coherent_mode; |
315 | int dig_block; | 302 | int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */ |
316 | /* atom lvds */ | 303 | /* atom lvds */ |
317 | uint32_t lvds_misc; | 304 | uint32_t lvds_misc; |
318 | uint16_t panel_pwr_delay; | 305 | uint16_t panel_pwr_delay; |
@@ -443,8 +430,7 @@ extern void radeon_compute_pll(struct radeon_pll *pll, | |||
443 | uint32_t *fb_div_p, | 430 | uint32_t *fb_div_p, |
444 | uint32_t *frac_fb_div_p, | 431 | uint32_t *frac_fb_div_p, |
445 | uint32_t *ref_div_p, | 432 | uint32_t *ref_div_p, |
446 | uint32_t *post_div_p, | 433 | uint32_t *post_div_p); |
447 | int flags); | ||
448 | 434 | ||
449 | extern void radeon_compute_pll_avivo(struct radeon_pll *pll, | 435 | extern void radeon_compute_pll_avivo(struct radeon_pll *pll, |
450 | uint64_t freq, | 436 | uint64_t freq, |
@@ -452,8 +438,7 @@ extern void radeon_compute_pll_avivo(struct radeon_pll *pll, | |||
452 | uint32_t *fb_div_p, | 438 | uint32_t *fb_div_p, |
453 | uint32_t *frac_fb_div_p, | 439 | uint32_t *frac_fb_div_p, |
454 | uint32_t *ref_div_p, | 440 | uint32_t *ref_div_p, |
455 | uint32_t *post_div_p, | 441 | uint32_t *post_div_p); |
456 | int flags); | ||
457 | 442 | ||
458 | extern void radeon_setup_encoder_clones(struct drm_device *dev); | 443 | extern void radeon_setup_encoder_clones(struct drm_device *dev); |
459 | 444 | ||
@@ -479,7 +464,6 @@ extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); | |||
479 | 464 | ||
480 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, | 465 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
481 | struct drm_framebuffer *old_fb); | 466 | struct drm_framebuffer *old_fb); |
482 | extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc); | ||
483 | 467 | ||
484 | extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, | 468 | extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, |
485 | struct drm_file *file_priv, | 469 | struct drm_file *file_priv, |