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path: root/drivers/gpu/drm/nouveau/nv50_software.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_software.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv50_software.c214
1 files changed, 214 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_software.c b/drivers/gpu/drm/nouveau/nv50_software.c
new file mode 100644
index 000000000000..114d2517d4a8
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_software.c
@@ -0,0 +1,214 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26
27#include "nouveau_drv.h"
28#include "nouveau_ramht.h"
29#include "nouveau_software.h"
30
31#include "nv50_display.h"
32
33struct nv50_software_priv {
34 struct nouveau_software_priv base;
35};
36
37struct nv50_software_chan {
38 struct nouveau_software_chan base;
39 struct {
40 struct nouveau_gpuobj *object;
41 } vblank;
42};
43
44static int
45mthd_dma_vblsem(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
46{
47 struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
48 struct nouveau_gpuobj *gpuobj;
49
50 gpuobj = nouveau_ramht_find(chan, data);
51 if (!gpuobj)
52 return -ENOENT;
53
54 if (nouveau_notifier_offset(gpuobj, NULL))
55 return -EINVAL;
56
57 pch->vblank.object = gpuobj;
58 pch->base.vblank.offset = ~0;
59 return 0;
60}
61
62static int
63mthd_vblsem_offset(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
64{
65 struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
66
67 if (nouveau_notifier_offset(pch->vblank.object, &data))
68 return -ERANGE;
69
70 pch->base.vblank.offset = data >> 2;
71 return 0;
72}
73
74static int
75mthd_vblsem_value(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
76{
77 struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
78 pch->base.vblank.value = data;
79 return 0;
80}
81
82static int
83mthd_vblsem_release(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
84{
85 struct nv50_software_priv *psw = nv_engine(chan->dev, NVOBJ_ENGINE_SW);
86 struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
87 struct drm_device *dev = chan->dev;
88
89 if (!pch->vblank.object || pch->base.vblank.offset == ~0 || data > 1)
90 return -EINVAL;
91
92 drm_vblank_get(dev, data);
93
94 pch->base.vblank.head = data;
95 list_add(&pch->base.vblank.list, &psw->base.vblank);
96 return 0;
97}
98
99static int
100mthd_flip(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
101{
102 nouveau_finish_page_flip(chan, NULL);
103 return 0;
104}
105
106static int
107nv50_software_context_new(struct nouveau_channel *chan, int engine)
108{
109 struct nv50_software_priv *psw = nv_engine(chan->dev, NVOBJ_ENGINE_SW);
110 struct nv50_display *pdisp = nv50_display(chan->dev);
111 struct nv50_software_chan *pch;
112 int ret = 0, i;
113
114 pch = kzalloc(sizeof(*pch), GFP_KERNEL);
115 if (!pch)
116 return -ENOMEM;
117
118 nouveau_software_context_new(&pch->base);
119 pch->base.vblank.bo = chan->notifier_bo;
120 chan->engctx[engine] = pch;
121
122 /* dma objects for display sync channel semaphore blocks */
123 for (i = 0; i < chan->dev->mode_config.num_crtc; i++) {
124 struct nv50_display_crtc *dispc = &pdisp->crtc[i];
125 struct nouveau_gpuobj *obj = NULL;
126
127 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
128 dispc->sem.bo->bo.offset, 0x1000,
129 NV_MEM_ACCESS_RW,
130 NV_MEM_TARGET_VRAM, &obj);
131 if (ret)
132 break;
133
134 ret = nouveau_ramht_insert(chan, NvEvoSema0 + i, obj);
135 nouveau_gpuobj_ref(NULL, &obj);
136 }
137
138 if (ret)
139 psw->base.base.context_del(chan, engine);
140 return ret;
141}
142
143static void
144nv50_software_context_del(struct nouveau_channel *chan, int engine)
145{
146 struct nv50_software_chan *pch = chan->engctx[engine];
147 chan->engctx[engine] = NULL;
148 kfree(pch);
149}
150
151static int
152nv50_software_object_new(struct nouveau_channel *chan, int engine,
153 u32 handle, u16 class)
154{
155 struct drm_device *dev = chan->dev;
156 struct nouveau_gpuobj *obj = NULL;
157 int ret;
158
159 ret = nouveau_gpuobj_new(dev, chan, 16, 16, 0, &obj);
160 if (ret)
161 return ret;
162 obj->engine = 0;
163 obj->class = class;
164
165 ret = nouveau_ramht_insert(chan, handle, obj);
166 nouveau_gpuobj_ref(NULL, &obj);
167 return ret;
168}
169
170static int
171nv50_software_init(struct drm_device *dev, int engine)
172{
173 return 0;
174}
175
176static int
177nv50_software_fini(struct drm_device *dev, int engine, bool suspend)
178{
179 return 0;
180}
181
182static void
183nv50_software_destroy(struct drm_device *dev, int engine)
184{
185 struct nv50_software_priv *psw = nv_engine(dev, engine);
186
187 NVOBJ_ENGINE_DEL(dev, SW);
188 kfree(psw);
189}
190
191int
192nv50_software_create(struct drm_device *dev)
193{
194 struct nv50_software_priv *psw = kzalloc(sizeof(*psw), GFP_KERNEL);
195 if (!psw)
196 return -ENOMEM;
197
198 psw->base.base.destroy = nv50_software_destroy;
199 psw->base.base.init = nv50_software_init;
200 psw->base.base.fini = nv50_software_fini;
201 psw->base.base.context_new = nv50_software_context_new;
202 psw->base.base.context_del = nv50_software_context_del;
203 psw->base.base.object_new = nv50_software_object_new;
204 nouveau_software_create(&psw->base);
205
206 NVOBJ_ENGINE_ADD(dev, SW, &psw->base.base);
207 NVOBJ_CLASS(dev, 0x506e, SW);
208 NVOBJ_MTHD (dev, 0x506e, 0x018c, mthd_dma_vblsem);
209 NVOBJ_MTHD (dev, 0x506e, 0x0400, mthd_vblsem_offset);
210 NVOBJ_MTHD (dev, 0x506e, 0x0404, mthd_vblsem_value);
211 NVOBJ_MTHD (dev, 0x506e, 0x0408, mthd_vblsem_release);
212 NVOBJ_MTHD (dev, 0x506e, 0x0500, mthd_flip);
213 return 0;
214}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 18:01:22 -0500