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path: root/drivers/gpu/drm/i915/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c874
1 files changed, 520 insertions, 354 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 52cd9b006da2..1b5cd833bc70 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -70,8 +70,6 @@ struct intel_limit {
70 intel_p2_t p2; 70 intel_p2_t p2;
71 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, 71 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
72 int, int, intel_clock_t *); 72 int, int, intel_clock_t *);
73 bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
74 int, int, intel_clock_t *);
75}; 73};
76 74
77#define I8XX_DOT_MIN 25000 75#define I8XX_DOT_MIN 25000
@@ -242,38 +240,93 @@ struct intel_limit {
242#define IRONLAKE_DOT_MAX 350000 240#define IRONLAKE_DOT_MAX 350000
243#define IRONLAKE_VCO_MIN 1760000 241#define IRONLAKE_VCO_MIN 1760000
244#define IRONLAKE_VCO_MAX 3510000 242#define IRONLAKE_VCO_MAX 3510000
245#define IRONLAKE_N_MIN 1
246#define IRONLAKE_N_MAX 5
247#define IRONLAKE_M_MIN 79
248#define IRONLAKE_M_MAX 118
249#define IRONLAKE_M1_MIN 12 243#define IRONLAKE_M1_MIN 12
250#define IRONLAKE_M1_MAX 23 244#define IRONLAKE_M1_MAX 22
251#define IRONLAKE_M2_MIN 5 245#define IRONLAKE_M2_MIN 5
252#define IRONLAKE_M2_MAX 9 246#define IRONLAKE_M2_MAX 9
253#define IRONLAKE_P_SDVO_DAC_MIN 5
254#define IRONLAKE_P_SDVO_DAC_MAX 80
255#define IRONLAKE_P_LVDS_MIN 28
256#define IRONLAKE_P_LVDS_MAX 112
257#define IRONLAKE_P1_MIN 1
258#define IRONLAKE_P1_MAX 8
259#define IRONLAKE_P2_SDVO_DAC_SLOW 10
260#define IRONLAKE_P2_SDVO_DAC_FAST 5
261#define IRONLAKE_P2_LVDS_SLOW 14 /* single channel */
262#define IRONLAKE_P2_LVDS_FAST 7 /* double channel */
263#define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */ 247#define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
264 248
249/* We have parameter ranges for different type of outputs. */
250
251/* DAC & HDMI Refclk 120Mhz */
252#define IRONLAKE_DAC_N_MIN 1
253#define IRONLAKE_DAC_N_MAX 5
254#define IRONLAKE_DAC_M_MIN 79
255#define IRONLAKE_DAC_M_MAX 127
256#define IRONLAKE_DAC_P_MIN 5
257#define IRONLAKE_DAC_P_MAX 80
258#define IRONLAKE_DAC_P1_MIN 1
259#define IRONLAKE_DAC_P1_MAX 8
260#define IRONLAKE_DAC_P2_SLOW 10
261#define IRONLAKE_DAC_P2_FAST 5
262
263/* LVDS single-channel 120Mhz refclk */
264#define IRONLAKE_LVDS_S_N_MIN 1
265#define IRONLAKE_LVDS_S_N_MAX 3
266#define IRONLAKE_LVDS_S_M_MIN 79
267#define IRONLAKE_LVDS_S_M_MAX 118
268#define IRONLAKE_LVDS_S_P_MIN 28
269#define IRONLAKE_LVDS_S_P_MAX 112
270#define IRONLAKE_LVDS_S_P1_MIN 2
271#define IRONLAKE_LVDS_S_P1_MAX 8
272#define IRONLAKE_LVDS_S_P2_SLOW 14
273#define IRONLAKE_LVDS_S_P2_FAST 14
274
275/* LVDS dual-channel 120Mhz refclk */
276#define IRONLAKE_LVDS_D_N_MIN 1
277#define IRONLAKE_LVDS_D_N_MAX 3
278#define IRONLAKE_LVDS_D_M_MIN 79
279#define IRONLAKE_LVDS_D_M_MAX 127
280#define IRONLAKE_LVDS_D_P_MIN 14
281#define IRONLAKE_LVDS_D_P_MAX 56
282#define IRONLAKE_LVDS_D_P1_MIN 2
283#define IRONLAKE_LVDS_D_P1_MAX 8
284#define IRONLAKE_LVDS_D_P2_SLOW 7
285#define IRONLAKE_LVDS_D_P2_FAST 7
286
287/* LVDS single-channel 100Mhz refclk */
288#define IRONLAKE_LVDS_S_SSC_N_MIN 1
289#define IRONLAKE_LVDS_S_SSC_N_MAX 2
290#define IRONLAKE_LVDS_S_SSC_M_MIN 79
291#define IRONLAKE_LVDS_S_SSC_M_MAX 126
292#define IRONLAKE_LVDS_S_SSC_P_MIN 28
293#define IRONLAKE_LVDS_S_SSC_P_MAX 112
294#define IRONLAKE_LVDS_S_SSC_P1_MIN 2
295#define IRONLAKE_LVDS_S_SSC_P1_MAX 8
296#define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
297#define IRONLAKE_LVDS_S_SSC_P2_FAST 14
298
299/* LVDS dual-channel 100Mhz refclk */
300#define IRONLAKE_LVDS_D_SSC_N_MIN 1
301#define IRONLAKE_LVDS_D_SSC_N_MAX 3
302#define IRONLAKE_LVDS_D_SSC_M_MIN 79
303#define IRONLAKE_LVDS_D_SSC_M_MAX 126
304#define IRONLAKE_LVDS_D_SSC_P_MIN 14
305#define IRONLAKE_LVDS_D_SSC_P_MAX 42
306#define IRONLAKE_LVDS_D_SSC_P1_MIN 2
307#define IRONLAKE_LVDS_D_SSC_P1_MAX 6
308#define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
309#define IRONLAKE_LVDS_D_SSC_P2_FAST 7
310
311/* DisplayPort */
312#define IRONLAKE_DP_N_MIN 1
313#define IRONLAKE_DP_N_MAX 2
314#define IRONLAKE_DP_M_MIN 81
315#define IRONLAKE_DP_M_MAX 90
316#define IRONLAKE_DP_P_MIN 10
317#define IRONLAKE_DP_P_MAX 20
318#define IRONLAKE_DP_P2_FAST 10
319#define IRONLAKE_DP_P2_SLOW 10
320#define IRONLAKE_DP_P2_LIMIT 0
321#define IRONLAKE_DP_P1_MIN 1
322#define IRONLAKE_DP_P1_MAX 2
323
265static bool 324static bool
266intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 325intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
267 int target, int refclk, intel_clock_t *best_clock); 326 int target, int refclk, intel_clock_t *best_clock);
268static bool 327static bool
269intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
270 int target, int refclk, intel_clock_t *best_clock);
271static bool
272intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 328intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
273 int target, int refclk, intel_clock_t *best_clock); 329 int target, int refclk, intel_clock_t *best_clock);
274static bool
275intel_ironlake_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
276 int target, int refclk, intel_clock_t *best_clock);
277 330
278static bool 331static bool
279intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, 332intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
@@ -294,7 +347,6 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
294 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, 347 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
295 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, 348 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
296 .find_pll = intel_find_best_PLL, 349 .find_pll = intel_find_best_PLL,
297 .find_reduced_pll = intel_find_best_reduced_PLL,
298}; 350};
299 351
300static const intel_limit_t intel_limits_i8xx_lvds = { 352static const intel_limit_t intel_limits_i8xx_lvds = {
@@ -309,7 +361,6 @@ static const intel_limit_t intel_limits_i8xx_lvds = {
309 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, 361 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
310 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, 362 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
311 .find_pll = intel_find_best_PLL, 363 .find_pll = intel_find_best_PLL,
312 .find_reduced_pll = intel_find_best_reduced_PLL,
313}; 364};
314 365
315static const intel_limit_t intel_limits_i9xx_sdvo = { 366static const intel_limit_t intel_limits_i9xx_sdvo = {
@@ -324,7 +375,6 @@ static const intel_limit_t intel_limits_i9xx_sdvo = {
324 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, 375 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
325 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, 376 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
326 .find_pll = intel_find_best_PLL, 377 .find_pll = intel_find_best_PLL,
327 .find_reduced_pll = intel_find_best_reduced_PLL,
328}; 378};
329 379
330static const intel_limit_t intel_limits_i9xx_lvds = { 380static const intel_limit_t intel_limits_i9xx_lvds = {
@@ -342,7 +392,6 @@ static const intel_limit_t intel_limits_i9xx_lvds = {
342 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, 392 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
343 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, 393 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
344 .find_pll = intel_find_best_PLL, 394 .find_pll = intel_find_best_PLL,
345 .find_reduced_pll = intel_find_best_reduced_PLL,
346}; 395};
347 396
348 /* below parameter and function is for G4X Chipset Family*/ 397 /* below parameter and function is for G4X Chipset Family*/
@@ -360,7 +409,6 @@ static const intel_limit_t intel_limits_g4x_sdvo = {
360 .p2_fast = G4X_P2_SDVO_FAST 409 .p2_fast = G4X_P2_SDVO_FAST
361 }, 410 },
362 .find_pll = intel_g4x_find_best_PLL, 411 .find_pll = intel_g4x_find_best_PLL,
363 .find_reduced_pll = intel_g4x_find_best_PLL,
364}; 412};
365 413
366static const intel_limit_t intel_limits_g4x_hdmi = { 414static const intel_limit_t intel_limits_g4x_hdmi = {
@@ -377,7 +425,6 @@ static const intel_limit_t intel_limits_g4x_hdmi = {
377 .p2_fast = G4X_P2_HDMI_DAC_FAST 425 .p2_fast = G4X_P2_HDMI_DAC_FAST
378 }, 426 },
379 .find_pll = intel_g4x_find_best_PLL, 427 .find_pll = intel_g4x_find_best_PLL,
380 .find_reduced_pll = intel_g4x_find_best_PLL,
381}; 428};
382 429
383static const intel_limit_t intel_limits_g4x_single_channel_lvds = { 430static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
@@ -402,7 +449,6 @@ static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
402 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST 449 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
403 }, 450 },
404 .find_pll = intel_g4x_find_best_PLL, 451 .find_pll = intel_g4x_find_best_PLL,
405 .find_reduced_pll = intel_g4x_find_best_PLL,
406}; 452};
407 453
408static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { 454static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
@@ -427,7 +473,6 @@ static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
427 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST 473 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
428 }, 474 },
429 .find_pll = intel_g4x_find_best_PLL, 475 .find_pll = intel_g4x_find_best_PLL,
430 .find_reduced_pll = intel_g4x_find_best_PLL,
431}; 476};
432 477
433static const intel_limit_t intel_limits_g4x_display_port = { 478static const intel_limit_t intel_limits_g4x_display_port = {
@@ -465,7 +510,6 @@ static const intel_limit_t intel_limits_pineview_sdvo = {
465 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, 510 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
466 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, 511 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
467 .find_pll = intel_find_best_PLL, 512 .find_pll = intel_find_best_PLL,
468 .find_reduced_pll = intel_find_best_reduced_PLL,
469}; 513};
470 514
471static const intel_limit_t intel_limits_pineview_lvds = { 515static const intel_limit_t intel_limits_pineview_lvds = {
@@ -481,46 +525,135 @@ static const intel_limit_t intel_limits_pineview_lvds = {
481 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, 525 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
482 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, 526 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
483 .find_pll = intel_find_best_PLL, 527 .find_pll = intel_find_best_PLL,
484 .find_reduced_pll = intel_find_best_reduced_PLL,
485}; 528};
486 529
487static const intel_limit_t intel_limits_ironlake_sdvo = { 530static const intel_limit_t intel_limits_ironlake_dac = {
531 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
532 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
533 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
534 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
535 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
536 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
537 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
538 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
539 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
540 .p2_slow = IRONLAKE_DAC_P2_SLOW,
541 .p2_fast = IRONLAKE_DAC_P2_FAST },
542 .find_pll = intel_g4x_find_best_PLL,
543};
544
545static const intel_limit_t intel_limits_ironlake_single_lvds = {
546 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
547 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
548 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
549 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
550 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
551 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
552 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
553 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
554 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
555 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
556 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
557 .find_pll = intel_g4x_find_best_PLL,
558};
559
560static const intel_limit_t intel_limits_ironlake_dual_lvds = {
561 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
562 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
563 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
564 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
565 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
566 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
567 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
568 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
569 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
570 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
571 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
572 .find_pll = intel_g4x_find_best_PLL,
573};
574
575static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
488 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, 576 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
489 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, 577 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
490 .n = { .min = IRONLAKE_N_MIN, .max = IRONLAKE_N_MAX }, 578 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
491 .m = { .min = IRONLAKE_M_MIN, .max = IRONLAKE_M_MAX }, 579 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
492 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, 580 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
493 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, 581 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
494 .p = { .min = IRONLAKE_P_SDVO_DAC_MIN, .max = IRONLAKE_P_SDVO_DAC_MAX }, 582 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
495 .p1 = { .min = IRONLAKE_P1_MIN, .max = IRONLAKE_P1_MAX }, 583 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
496 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, 584 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
497 .p2_slow = IRONLAKE_P2_SDVO_DAC_SLOW, 585 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
498 .p2_fast = IRONLAKE_P2_SDVO_DAC_FAST }, 586 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
499 .find_pll = intel_ironlake_find_best_PLL, 587 .find_pll = intel_g4x_find_best_PLL,
500}; 588};
501 589
502static const intel_limit_t intel_limits_ironlake_lvds = { 590static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
503 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, 591 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
504 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, 592 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
505 .n = { .min = IRONLAKE_N_MIN, .max = IRONLAKE_N_MAX }, 593 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
506 .m = { .min = IRONLAKE_M_MIN, .max = IRONLAKE_M_MAX }, 594 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
507 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, 595 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
508 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, 596 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
509 .p = { .min = IRONLAKE_P_LVDS_MIN, .max = IRONLAKE_P_LVDS_MAX }, 597 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
510 .p1 = { .min = IRONLAKE_P1_MIN, .max = IRONLAKE_P1_MAX }, 598 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
511 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, 599 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
512 .p2_slow = IRONLAKE_P2_LVDS_SLOW, 600 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
513 .p2_fast = IRONLAKE_P2_LVDS_FAST }, 601 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
514 .find_pll = intel_ironlake_find_best_PLL, 602 .find_pll = intel_g4x_find_best_PLL,
603};
604
605static const intel_limit_t intel_limits_ironlake_display_port = {
606 .dot = { .min = IRONLAKE_DOT_MIN,
607 .max = IRONLAKE_DOT_MAX },
608 .vco = { .min = IRONLAKE_VCO_MIN,
609 .max = IRONLAKE_VCO_MAX},
610 .n = { .min = IRONLAKE_DP_N_MIN,
611 .max = IRONLAKE_DP_N_MAX },
612 .m = { .min = IRONLAKE_DP_M_MIN,
613 .max = IRONLAKE_DP_M_MAX },
614 .m1 = { .min = IRONLAKE_M1_MIN,
615 .max = IRONLAKE_M1_MAX },
616 .m2 = { .min = IRONLAKE_M2_MIN,
617 .max = IRONLAKE_M2_MAX },
618 .p = { .min = IRONLAKE_DP_P_MIN,
619 .max = IRONLAKE_DP_P_MAX },
620 .p1 = { .min = IRONLAKE_DP_P1_MIN,
621 .max = IRONLAKE_DP_P1_MAX},
622 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
623 .p2_slow = IRONLAKE_DP_P2_SLOW,
624 .p2_fast = IRONLAKE_DP_P2_FAST },
625 .find_pll = intel_find_pll_ironlake_dp,
515}; 626};
516 627
517static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc) 628static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
518{ 629{
630 struct drm_device *dev = crtc->dev;
631 struct drm_i915_private *dev_priv = dev->dev_private;
519 const intel_limit_t *limit; 632 const intel_limit_t *limit;
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 633 int refclk = 120;
521 limit = &intel_limits_ironlake_lvds; 634
635 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
636 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
637 refclk = 100;
638
639 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
640 LVDS_CLKB_POWER_UP) {
641 /* LVDS dual channel */
642 if (refclk == 100)
643 limit = &intel_limits_ironlake_dual_lvds_100m;
644 else
645 limit = &intel_limits_ironlake_dual_lvds;
646 } else {
647 if (refclk == 100)
648 limit = &intel_limits_ironlake_single_lvds_100m;
649 else
650 limit = &intel_limits_ironlake_single_lvds;
651 }
652 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
653 HAS_eDP)
654 limit = &intel_limits_ironlake_display_port;
522 else 655 else
523 limit = &intel_limits_ironlake_sdvo; 656 limit = &intel_limits_ironlake_dac;
524 657
525 return limit; 658 return limit;
526} 659}
@@ -737,46 +870,6 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
737 return (err != target); 870 return (err != target);
738} 871}
739 872
740
741static bool
742intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
743 int target, int refclk, intel_clock_t *best_clock)
744
745{
746 struct drm_device *dev = crtc->dev;
747 intel_clock_t clock;
748 int err = target;
749 bool found = false;
750
751 memcpy(&clock, best_clock, sizeof(intel_clock_t));
752
753 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
754 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
755 /* m1 is always 0 in Pineview */
756 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
757 break;
758 for (clock.n = limit->n.min; clock.n <= limit->n.max;
759 clock.n++) {
760 int this_err;
761
762 intel_clock(dev, refclk, &clock);
763
764 if (!intel_PLL_is_valid(crtc, &clock))
765 continue;
766
767 this_err = abs(clock.dot - target);
768 if (this_err < err) {
769 *best_clock = clock;
770 err = this_err;
771 found = true;
772 }
773 }
774 }
775 }
776
777 return found;
778}
779
780static bool 873static bool
781intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 874intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
782 int target, int refclk, intel_clock_t *best_clock) 875 int target, int refclk, intel_clock_t *best_clock)
@@ -791,7 +884,13 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
791 found = false; 884 found = false;
792 885
793 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 886 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
794 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 887 int lvds_reg;
888
889 if (IS_IRONLAKE(dev))
890 lvds_reg = PCH_LVDS;
891 else
892 lvds_reg = LVDS;
893 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
795 LVDS_CLKB_POWER_UP) 894 LVDS_CLKB_POWER_UP)
796 clock.p2 = limit->p2.p2_fast; 895 clock.p2 = limit->p2.p2_fast;
797 else 896 else
@@ -839,6 +938,11 @@ intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
839{ 938{
840 struct drm_device *dev = crtc->dev; 939 struct drm_device *dev = crtc->dev;
841 intel_clock_t clock; 940 intel_clock_t clock;
941
942 /* return directly when it is eDP */
943 if (HAS_eDP)
944 return true;
945
842 if (target < 200000) { 946 if (target < 200000) {
843 clock.n = 1; 947 clock.n = 1;
844 clock.p1 = 2; 948 clock.p1 = 2;
@@ -857,68 +961,6 @@ intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
857 return true; 961 return true;
858} 962}
859 963
860static bool
861intel_ironlake_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
862 int target, int refclk, intel_clock_t *best_clock)
863{
864 struct drm_device *dev = crtc->dev;
865 struct drm_i915_private *dev_priv = dev->dev_private;
866 intel_clock_t clock;
867 int err_most = 47;
868 int err_min = 10000;
869
870 /* eDP has only 2 clock choice, no n/m/p setting */
871 if (HAS_eDP)
872 return true;
873
874 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
875 return intel_find_pll_ironlake_dp(limit, crtc, target,
876 refclk, best_clock);
877
878 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
879 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
880 LVDS_CLKB_POWER_UP)
881 clock.p2 = limit->p2.p2_fast;
882 else
883 clock.p2 = limit->p2.p2_slow;
884 } else {
885 if (target < limit->p2.dot_limit)
886 clock.p2 = limit->p2.p2_slow;
887 else
888 clock.p2 = limit->p2.p2_fast;
889 }
890
891 memset(best_clock, 0, sizeof(*best_clock));
892 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
893 /* based on hardware requriment prefer smaller n to precision */
894 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
895 /* based on hardware requirment prefere larger m1,m2 */
896 for (clock.m1 = limit->m1.max;
897 clock.m1 >= limit->m1.min; clock.m1--) {
898 for (clock.m2 = limit->m2.max;
899 clock.m2 >= limit->m2.min; clock.m2--) {
900 int this_err;
901
902 intel_clock(dev, refclk, &clock);
903 if (!intel_PLL_is_valid(crtc, &clock))
904 continue;
905 this_err = abs((10000 - (target*10000/clock.dot)));
906 if (this_err < err_most) {
907 *best_clock = clock;
908 /* found on first matching */
909 goto out;
910 } else if (this_err < err_min) {
911 *best_clock = clock;
912 err_min = this_err;
913 }
914 }
915 }
916 }
917 }
918out:
919 return true;
920}
921
922/* DisplayPort has only two frequencies, 162MHz and 270MHz */ 964/* DisplayPort has only two frequencies, 162MHz and 270MHz */
923static bool 965static bool
924intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 966intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
@@ -989,6 +1031,8 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
989 1031
990 /* enable it... */ 1032 /* enable it... */
991 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; 1033 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1034 if (IS_I945GM(dev))
1035 fbc_ctl |= FBC_C3_IDLE; /* 945 needs special SR handling */
992 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; 1036 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
993 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; 1037 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
994 if (obj_priv->tiling_mode != I915_TILING_NONE) 1038 if (obj_priv->tiling_mode != I915_TILING_NONE)
@@ -1144,25 +1188,30 @@ static void intel_update_fbc(struct drm_crtc *crtc,
1144 if (intel_fb->obj->size > dev_priv->cfb_size) { 1188 if (intel_fb->obj->size > dev_priv->cfb_size) {
1145 DRM_DEBUG_KMS("framebuffer too large, disabling " 1189 DRM_DEBUG_KMS("framebuffer too large, disabling "
1146 "compression\n"); 1190 "compression\n");
1191 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1147 goto out_disable; 1192 goto out_disable;
1148 } 1193 }
1149 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 1194 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1150 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) { 1195 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1151 DRM_DEBUG_KMS("mode incompatible with compression, " 1196 DRM_DEBUG_KMS("mode incompatible with compression, "
1152 "disabling\n"); 1197 "disabling\n");
1198 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1153 goto out_disable; 1199 goto out_disable;
1154 } 1200 }
1155 if ((mode->hdisplay > 2048) || 1201 if ((mode->hdisplay > 2048) ||
1156 (mode->vdisplay > 1536)) { 1202 (mode->vdisplay > 1536)) {
1157 DRM_DEBUG_KMS("mode too large for compression, disabling\n"); 1203 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1204 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1158 goto out_disable; 1205 goto out_disable;
1159 } 1206 }
1160 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) { 1207 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1161 DRM_DEBUG_KMS("plane not 0, disabling compression\n"); 1208 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1209 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1162 goto out_disable; 1210 goto out_disable;
1163 } 1211 }
1164 if (obj_priv->tiling_mode != I915_TILING_X) { 1212 if (obj_priv->tiling_mode != I915_TILING_X) {
1165 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n"); 1213 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1214 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1166 goto out_disable; 1215 goto out_disable;
1167 } 1216 }
1168 1217
@@ -1282,7 +1331,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1282 return ret; 1331 return ret;
1283 } 1332 }
1284 1333
1285 ret = i915_gem_object_set_to_gtt_domain(obj, 1); 1334 ret = i915_gem_object_set_to_display_plane(obj);
1286 if (ret != 0) { 1335 if (ret != 0) {
1287 i915_gem_object_unpin(obj); 1336 i915_gem_object_unpin(obj);
1288 mutex_unlock(&dev->struct_mutex); 1337 mutex_unlock(&dev->struct_mutex);
@@ -1493,6 +1542,10 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1493 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; 1542 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1494 u32 temp; 1543 u32 temp;
1495 int tries = 5, j, n; 1544 int tries = 5, j, n;
1545 u32 pipe_bpc;
1546
1547 temp = I915_READ(pipeconf_reg);
1548 pipe_bpc = temp & PIPE_BPC_MASK;
1496 1549
1497 /* XXX: When our outputs are all unaware of DPMS modes other than off 1550 /* XXX: When our outputs are all unaware of DPMS modes other than off
1498 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 1551 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
@@ -1524,6 +1577,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1524 1577
1525 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 1578 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1526 temp = I915_READ(fdi_rx_reg); 1579 temp = I915_READ(fdi_rx_reg);
1580 /*
1581 * make the BPC in FDI Rx be consistent with that in
1582 * pipeconf reg.
1583 */
1584 temp &= ~(0x7 << 16);
1585 temp |= (pipe_bpc << 11);
1527 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE | 1586 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1528 FDI_SEL_PCDCLK | 1587 FDI_SEL_PCDCLK |
1529 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */ 1588 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
@@ -1666,6 +1725,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1666 1725
1667 /* enable PCH transcoder */ 1726 /* enable PCH transcoder */
1668 temp = I915_READ(transconf_reg); 1727 temp = I915_READ(transconf_reg);
1728 /*
1729 * make the BPC in transcoder be consistent with
1730 * that in pipeconf reg.
1731 */
1732 temp &= ~PIPE_BPC_MASK;
1733 temp |= pipe_bpc;
1669 I915_WRITE(transconf_reg, temp | TRANS_ENABLE); 1734 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1670 I915_READ(transconf_reg); 1735 I915_READ(transconf_reg);
1671 1736
@@ -1697,6 +1762,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1697 case DRM_MODE_DPMS_OFF: 1762 case DRM_MODE_DPMS_OFF:
1698 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe); 1763 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1699 1764
1765 drm_vblank_off(dev, pipe);
1700 /* Disable display plane */ 1766 /* Disable display plane */
1701 temp = I915_READ(dspcntr_reg); 1767 temp = I915_READ(dspcntr_reg);
1702 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { 1768 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
@@ -1745,6 +1811,9 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1745 I915_READ(fdi_tx_reg); 1811 I915_READ(fdi_tx_reg);
1746 1812
1747 temp = I915_READ(fdi_rx_reg); 1813 temp = I915_READ(fdi_rx_reg);
1814 /* BPC in FDI rx is consistent with that in pipeconf */
1815 temp &= ~(0x07 << 16);
1816 temp |= (pipe_bpc << 11);
1748 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE); 1817 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1749 I915_READ(fdi_rx_reg); 1818 I915_READ(fdi_rx_reg);
1750 1819
@@ -1789,7 +1858,12 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1789 } 1858 }
1790 } 1859 }
1791 } 1860 }
1792 1861 temp = I915_READ(transconf_reg);
1862 /* BPC in transcoder is consistent with that in pipeconf */
1863 temp &= ~PIPE_BPC_MASK;
1864 temp |= pipe_bpc;
1865 I915_WRITE(transconf_reg, temp);
1866 I915_READ(transconf_reg);
1793 udelay(100); 1867 udelay(100);
1794 1868
1795 /* disable PCH DPLL */ 1869 /* disable PCH DPLL */
@@ -2448,7 +2522,7 @@ static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2448 * A value of 5us seems to be a good balance; safe for very low end 2522 * A value of 5us seems to be a good balance; safe for very low end
2449 * platforms but not overly aggressive on lower latency configs. 2523 * platforms but not overly aggressive on lower latency configs.
2450 */ 2524 */
2451const static int latency_ns = 5000; 2525static const int latency_ns = 5000;
2452 2526
2453static int i9xx_get_fifo_size(struct drm_device *dev, int plane) 2527static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2454{ 2528{
@@ -2559,7 +2633,7 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2559 /* Calc sr entries for one plane configs */ 2633 /* Calc sr entries for one plane configs */
2560 if (sr_hdisplay && (!planea_clock || !planeb_clock)) { 2634 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2561 /* self-refresh has much higher latency */ 2635 /* self-refresh has much higher latency */
2562 const static int sr_latency_ns = 12000; 2636 static const int sr_latency_ns = 12000;
2563 2637
2564 sr_clock = planea_clock ? planea_clock : planeb_clock; 2638 sr_clock = planea_clock ? planea_clock : planeb_clock;
2565 line_time_us = ((sr_hdisplay * 1000) / sr_clock); 2639 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
@@ -2570,6 +2644,10 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2570 sr_entries = roundup(sr_entries / cacheline_size, 1); 2644 sr_entries = roundup(sr_entries / cacheline_size, 1);
2571 DRM_DEBUG("self-refresh entries: %d\n", sr_entries); 2645 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2572 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 2646 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2647 } else {
2648 /* Turn off self refresh if both pipes are enabled */
2649 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2650 & ~FW_BLC_SELF_EN);
2573 } 2651 }
2574 2652
2575 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", 2653 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
@@ -2598,7 +2676,7 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
2598 /* Calc sr entries for one plane configs */ 2676 /* Calc sr entries for one plane configs */
2599 if (sr_hdisplay && (!planea_clock || !planeb_clock)) { 2677 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2600 /* self-refresh has much higher latency */ 2678 /* self-refresh has much higher latency */
2601 const static int sr_latency_ns = 12000; 2679 static const int sr_latency_ns = 12000;
2602 2680
2603 sr_clock = planea_clock ? planea_clock : planeb_clock; 2681 sr_clock = planea_clock ? planea_clock : planeb_clock;
2604 line_time_us = ((sr_hdisplay * 1000) / sr_clock); 2682 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
@@ -2613,6 +2691,10 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
2613 srwm = 1; 2691 srwm = 1;
2614 srwm &= 0x3f; 2692 srwm &= 0x3f;
2615 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 2693 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2694 } else {
2695 /* Turn off self refresh if both pipes are enabled */
2696 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2697 & ~FW_BLC_SELF_EN);
2616 } 2698 }
2617 2699
2618 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", 2700 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
@@ -2667,7 +2749,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2667 if (HAS_FW_BLC(dev) && sr_hdisplay && 2749 if (HAS_FW_BLC(dev) && sr_hdisplay &&
2668 (!planea_clock || !planeb_clock)) { 2750 (!planea_clock || !planeb_clock)) {
2669 /* self-refresh has much higher latency */ 2751 /* self-refresh has much higher latency */
2670 const static int sr_latency_ns = 6000; 2752 static const int sr_latency_ns = 6000;
2671 2753
2672 sr_clock = planea_clock ? planea_clock : planeb_clock; 2754 sr_clock = planea_clock ? planea_clock : planeb_clock;
2673 line_time_us = ((sr_hdisplay * 1000) / sr_clock); 2755 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
@@ -2680,7 +2762,22 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2680 srwm = total_size - sr_entries; 2762 srwm = total_size - sr_entries;
2681 if (srwm < 0) 2763 if (srwm < 0)
2682 srwm = 1; 2764 srwm = 1;
2683 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); 2765
2766 if (IS_I945G(dev) || IS_I945GM(dev))
2767 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2768 else if (IS_I915GM(dev)) {
2769 /* 915M has a smaller SRWM field */
2770 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2771 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
2772 }
2773 } else {
2774 /* Turn off self refresh if both pipes are enabled */
2775 if (IS_I945G(dev) || IS_I945GM(dev)) {
2776 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2777 & ~FW_BLC_SELF_EN);
2778 } else if (IS_I915GM(dev)) {
2779 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
2780 }
2684 } 2781 }
2685 2782
2686 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 2783 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
@@ -2906,10 +3003,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2906 return -EINVAL; 3003 return -EINVAL;
2907 } 3004 }
2908 3005
2909 if (is_lvds && limit->find_reduced_pll && 3006 if (is_lvds && dev_priv->lvds_downclock_avail) {
2910 dev_priv->lvds_downclock_avail) { 3007 has_reduced_clock = limit->find_pll(limit, crtc,
2911 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2912 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2913 dev_priv->lvds_downclock, 3008 dev_priv->lvds_downclock,
2914 refclk, 3009 refclk,
2915 &reduced_clock); 3010 &reduced_clock);
@@ -2969,6 +3064,33 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2969 3064
2970 /* determine panel color depth */ 3065 /* determine panel color depth */
2971 temp = I915_READ(pipeconf_reg); 3066 temp = I915_READ(pipeconf_reg);
3067 temp &= ~PIPE_BPC_MASK;
3068 if (is_lvds) {
3069 int lvds_reg = I915_READ(PCH_LVDS);
3070 /* the BPC will be 6 if it is 18-bit LVDS panel */
3071 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3072 temp |= PIPE_8BPC;
3073 else
3074 temp |= PIPE_6BPC;
3075 } else if (is_edp) {
3076 switch (dev_priv->edp_bpp/3) {
3077 case 8:
3078 temp |= PIPE_8BPC;
3079 break;
3080 case 10:
3081 temp |= PIPE_10BPC;
3082 break;
3083 case 6:
3084 temp |= PIPE_6BPC;
3085 break;
3086 case 12:
3087 temp |= PIPE_12BPC;
3088 break;
3089 }
3090 } else
3091 temp |= PIPE_8BPC;
3092 I915_WRITE(pipeconf_reg, temp);
3093 I915_READ(pipeconf_reg);
2972 3094
2973 switch (temp & PIPE_BPC_MASK) { 3095 switch (temp & PIPE_BPC_MASK) {
2974 case PIPE_8BPC: 3096 case PIPE_8BPC:
@@ -3195,7 +3317,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3195 * appropriately here, but we need to look more thoroughly into how 3317 * appropriately here, but we need to look more thoroughly into how
3196 * panels behave in the two modes. 3318 * panels behave in the two modes.
3197 */ 3319 */
3198 3320 /* set the dithering flag */
3321 if (IS_I965G(dev)) {
3322 if (dev_priv->lvds_dither) {
3323 if (IS_IRONLAKE(dev))
3324 pipeconf |= PIPE_ENABLE_DITHER;
3325 else
3326 lvds |= LVDS_ENABLE_DITHER;
3327 } else {
3328 if (IS_IRONLAKE(dev))
3329 pipeconf &= ~PIPE_ENABLE_DITHER;
3330 else
3331 lvds &= ~LVDS_ENABLE_DITHER;
3332 }
3333 }
3199 I915_WRITE(lvds_reg, lvds); 3334 I915_WRITE(lvds_reg, lvds);
3200 I915_READ(lvds_reg); 3335 I915_READ(lvds_reg);
3201 } 3336 }
@@ -3385,7 +3520,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3385 3520
3386 /* we only need to pin inside GTT if cursor is non-phy */ 3521 /* we only need to pin inside GTT if cursor is non-phy */
3387 mutex_lock(&dev->struct_mutex); 3522 mutex_lock(&dev->struct_mutex);
3388 if (!dev_priv->cursor_needs_physical) { 3523 if (!dev_priv->info->cursor_needs_physical) {
3389 ret = i915_gem_object_pin(bo, PAGE_SIZE); 3524 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3390 if (ret) { 3525 if (ret) {
3391 DRM_ERROR("failed to pin cursor bo\n"); 3526 DRM_ERROR("failed to pin cursor bo\n");
@@ -3420,7 +3555,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3420 I915_WRITE(base, addr); 3555 I915_WRITE(base, addr);
3421 3556
3422 if (intel_crtc->cursor_bo) { 3557 if (intel_crtc->cursor_bo) {
3423 if (dev_priv->cursor_needs_physical) { 3558 if (dev_priv->info->cursor_needs_physical) {
3424 if (intel_crtc->cursor_bo != bo) 3559 if (intel_crtc->cursor_bo != bo)
3425 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); 3560 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3426 } else 3561 } else
@@ -3434,11 +3569,10 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3434 intel_crtc->cursor_bo = bo; 3569 intel_crtc->cursor_bo = bo;
3435 3570
3436 return 0; 3571 return 0;
3437fail:
3438 mutex_lock(&dev->struct_mutex);
3439fail_locked: 3572fail_locked:
3440 drm_gem_object_unreference(bo);
3441 mutex_unlock(&dev->struct_mutex); 3573 mutex_unlock(&dev->struct_mutex);
3574fail:
3575 drm_gem_object_unreference_unlocked(bo);
3442 return ret; 3576 return ret;
3443} 3577}
3444 3578
@@ -3779,125 +3913,6 @@ static void intel_gpu_idle_timer(unsigned long arg)
3779 queue_work(dev_priv->wq, &dev_priv->idle_work); 3913 queue_work(dev_priv->wq, &dev_priv->idle_work);
3780} 3914}
3781 3915
3782void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3783{
3784 drm_i915_private_t *dev_priv = dev->dev_private;
3785
3786 if (IS_IRONLAKE(dev))
3787 return;
3788
3789 if (!dev_priv->render_reclock_avail) {
3790 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3791 return;
3792 }
3793
3794 /* Restore render clock frequency to original value */
3795 if (IS_G4X(dev) || IS_I9XX(dev))
3796 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3797 else if (IS_I85X(dev))
3798 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3799 DRM_DEBUG_DRIVER("increasing render clock frequency\n");
3800
3801 /* Schedule downclock */
3802 if (schedule)
3803 mod_timer(&dev_priv->idle_timer, jiffies +
3804 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3805}
3806
3807void intel_decrease_renderclock(struct drm_device *dev)
3808{
3809 drm_i915_private_t *dev_priv = dev->dev_private;
3810
3811 if (IS_IRONLAKE(dev))
3812 return;
3813
3814 if (!dev_priv->render_reclock_avail) {
3815 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3816 return;
3817 }
3818
3819 if (IS_G4X(dev)) {
3820 u16 gcfgc;
3821
3822 /* Adjust render clock... */
3823 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3824
3825 /* Down to minimum... */
3826 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3827 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3828
3829 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3830 } else if (IS_I965G(dev)) {
3831 u16 gcfgc;
3832
3833 /* Adjust render clock... */
3834 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3835
3836 /* Down to minimum... */
3837 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3838 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3839
3840 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3841 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3842 u16 gcfgc;
3843
3844 /* Adjust render clock... */
3845 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3846
3847 /* Down to minimum... */
3848 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3849 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3850
3851 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3852 } else if (IS_I915G(dev)) {
3853 u16 gcfgc;
3854
3855 /* Adjust render clock... */
3856 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3857
3858 /* Down to minimum... */
3859 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3860 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3861
3862 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3863 } else if (IS_I85X(dev)) {
3864 u16 hpllcc;
3865
3866 /* Adjust render clock... */
3867 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3868
3869 /* Up to maximum... */
3870 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3871 hpllcc |= GC_CLOCK_133_200;
3872
3873 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3874 }
3875 DRM_DEBUG_DRIVER("decreasing render clock frequency\n");
3876}
3877
3878/* Note that no increase function is needed for this - increase_renderclock()
3879 * will also rewrite these bits
3880 */
3881void intel_decrease_displayclock(struct drm_device *dev)
3882{
3883 if (IS_IRONLAKE(dev))
3884 return;
3885
3886 if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3887 IS_I915GM(dev)) {
3888 u16 gcfgc;
3889
3890 /* Adjust render clock... */
3891 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3892
3893 /* Down to minimum... */
3894 gcfgc &= ~0xf0;
3895 gcfgc |= 0x80;
3896
3897 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3898 }
3899}
3900
3901#define CRTC_IDLE_TIMEOUT 1000 /* ms */ 3916#define CRTC_IDLE_TIMEOUT 1000 /* ms */
3902 3917
3903static void intel_crtc_idle_timer(unsigned long arg) 3918static void intel_crtc_idle_timer(unsigned long arg)
@@ -4011,10 +4026,9 @@ static void intel_idle_update(struct work_struct *work)
4011 4026
4012 mutex_lock(&dev->struct_mutex); 4027 mutex_lock(&dev->struct_mutex);
4013 4028
4014 /* GPU isn't processing, downclock it. */ 4029 if (IS_I945G(dev) || IS_I945GM(dev)) {
4015 if (!dev_priv->busy) { 4030 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4016 intel_decrease_renderclock(dev); 4031 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4017 intel_decrease_displayclock(dev);
4018 } 4032 }
4019 4033
4020 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 4034 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
@@ -4051,12 +4065,18 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4051 return; 4065 return;
4052 4066
4053 if (!dev_priv->busy) { 4067 if (!dev_priv->busy) {
4068 if (IS_I945G(dev) || IS_I945GM(dev)) {
4069 u32 fw_blc_self;
4070
4071 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4072 fw_blc_self = I915_READ(FW_BLC_SELF);
4073 fw_blc_self &= ~FW_BLC_SELF_EN;
4074 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4075 }
4054 dev_priv->busy = true; 4076 dev_priv->busy = true;
4055 intel_increase_renderclock(dev, true); 4077 } else
4056 } else {
4057 mod_timer(&dev_priv->idle_timer, jiffies + 4078 mod_timer(&dev_priv->idle_timer, jiffies +
4058 msecs_to_jiffies(GPU_IDLE_TIMEOUT)); 4079 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4059 }
4060 4080
4061 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 4081 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4062 if (!crtc->fb) 4082 if (!crtc->fb)
@@ -4066,6 +4086,14 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4066 intel_fb = to_intel_framebuffer(crtc->fb); 4086 intel_fb = to_intel_framebuffer(crtc->fb);
4067 if (intel_fb->obj == obj) { 4087 if (intel_fb->obj == obj) {
4068 if (!intel_crtc->busy) { 4088 if (!intel_crtc->busy) {
4089 if (IS_I945G(dev) || IS_I945GM(dev)) {
4090 u32 fw_blc_self;
4091
4092 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4093 fw_blc_self = I915_READ(FW_BLC_SELF);
4094 fw_blc_self &= ~FW_BLC_SELF_EN;
4095 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4096 }
4069 /* Non-busy -> busy, upclock */ 4097 /* Non-busy -> busy, upclock */
4070 intel_increase_pllclock(crtc, true); 4098 intel_increase_pllclock(crtc, true);
4071 intel_crtc->busy = true; 4099 intel_crtc->busy = true;
@@ -4089,7 +4117,8 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
4089struct intel_unpin_work { 4117struct intel_unpin_work {
4090 struct work_struct work; 4118 struct work_struct work;
4091 struct drm_device *dev; 4119 struct drm_device *dev;
4092 struct drm_gem_object *obj; 4120 struct drm_gem_object *old_fb_obj;
4121 struct drm_gem_object *pending_flip_obj;
4093 struct drm_pending_vblank_event *event; 4122 struct drm_pending_vblank_event *event;
4094 int pending; 4123 int pending;
4095}; 4124};
@@ -4100,8 +4129,9 @@ static void intel_unpin_work_fn(struct work_struct *__work)
4100 container_of(__work, struct intel_unpin_work, work); 4129 container_of(__work, struct intel_unpin_work, work);
4101 4130
4102 mutex_lock(&work->dev->struct_mutex); 4131 mutex_lock(&work->dev->struct_mutex);
4103 i915_gem_object_unpin(work->obj); 4132 i915_gem_object_unpin(work->old_fb_obj);
4104 drm_gem_object_unreference(work->obj); 4133 drm_gem_object_unreference(work->pending_flip_obj);
4134 drm_gem_object_unreference(work->old_fb_obj);
4105 mutex_unlock(&work->dev->struct_mutex); 4135 mutex_unlock(&work->dev->struct_mutex);
4106 kfree(work); 4136 kfree(work);
4107} 4137}
@@ -4124,6 +4154,12 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe)
4124 spin_lock_irqsave(&dev->event_lock, flags); 4154 spin_lock_irqsave(&dev->event_lock, flags);
4125 work = intel_crtc->unpin_work; 4155 work = intel_crtc->unpin_work;
4126 if (work == NULL || !work->pending) { 4156 if (work == NULL || !work->pending) {
4157 if (work && !work->pending) {
4158 obj_priv = work->pending_flip_obj->driver_private;
4159 DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4160 obj_priv,
4161 atomic_read(&obj_priv->pending_flip));
4162 }
4127 spin_unlock_irqrestore(&dev->event_lock, flags); 4163 spin_unlock_irqrestore(&dev->event_lock, flags);
4128 return; 4164 return;
4129 } 4165 }
@@ -4144,8 +4180,11 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe)
4144 4180
4145 spin_unlock_irqrestore(&dev->event_lock, flags); 4181 spin_unlock_irqrestore(&dev->event_lock, flags);
4146 4182
4147 obj_priv = work->obj->driver_private; 4183 obj_priv = work->pending_flip_obj->driver_private;
4148 if (atomic_dec_and_test(&obj_priv->pending_flip)) 4184
4185 /* Initial scanout buffer will have a 0 pending flip count */
4186 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4187 atomic_dec_and_test(&obj_priv->pending_flip))
4149 DRM_WAKEUP(&dev_priv->pending_flip_queue); 4188 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4150 schedule_work(&work->work); 4189 schedule_work(&work->work);
4151} 4190}
@@ -4158,8 +4197,11 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane)
4158 unsigned long flags; 4197 unsigned long flags;
4159 4198
4160 spin_lock_irqsave(&dev->event_lock, flags); 4199 spin_lock_irqsave(&dev->event_lock, flags);
4161 if (intel_crtc->unpin_work) 4200 if (intel_crtc->unpin_work) {
4162 intel_crtc->unpin_work->pending = 1; 4201 intel_crtc->unpin_work->pending = 1;
4202 } else {
4203 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4204 }
4163 spin_unlock_irqrestore(&dev->event_lock, flags); 4205 spin_unlock_irqrestore(&dev->event_lock, flags);
4164} 4206}
4165 4207
@@ -4175,7 +4217,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
4175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4176 struct intel_unpin_work *work; 4218 struct intel_unpin_work *work;
4177 unsigned long flags; 4219 unsigned long flags;
4178 int ret; 4220 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4221 int ret, pipesrc;
4179 RING_LOCALS; 4222 RING_LOCALS;
4180 4223
4181 work = kzalloc(sizeof *work, GFP_KERNEL); 4224 work = kzalloc(sizeof *work, GFP_KERNEL);
@@ -4187,12 +4230,13 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
4187 work->event = event; 4230 work->event = event;
4188 work->dev = crtc->dev; 4231 work->dev = crtc->dev;
4189 intel_fb = to_intel_framebuffer(crtc->fb); 4232 intel_fb = to_intel_framebuffer(crtc->fb);
4190 work->obj = intel_fb->obj; 4233 work->old_fb_obj = intel_fb->obj;
4191 INIT_WORK(&work->work, intel_unpin_work_fn); 4234 INIT_WORK(&work->work, intel_unpin_work_fn);
4192 4235
4193 /* We borrow the event spin lock for protecting unpin_work */ 4236 /* We borrow the event spin lock for protecting unpin_work */
4194 spin_lock_irqsave(&dev->event_lock, flags); 4237 spin_lock_irqsave(&dev->event_lock, flags);
4195 if (intel_crtc->unpin_work) { 4238 if (intel_crtc->unpin_work) {
4239 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4196 spin_unlock_irqrestore(&dev->event_lock, flags); 4240 spin_unlock_irqrestore(&dev->event_lock, flags);
4197 kfree(work); 4241 kfree(work);
4198 mutex_unlock(&dev->struct_mutex); 4242 mutex_unlock(&dev->struct_mutex);
@@ -4206,19 +4250,24 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
4206 4250
4207 ret = intel_pin_and_fence_fb_obj(dev, obj); 4251 ret = intel_pin_and_fence_fb_obj(dev, obj);
4208 if (ret != 0) { 4252 if (ret != 0) {
4253 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4254 obj->driver_private);
4209 kfree(work); 4255 kfree(work);
4256 intel_crtc->unpin_work = NULL;
4210 mutex_unlock(&dev->struct_mutex); 4257 mutex_unlock(&dev->struct_mutex);
4211 return ret; 4258 return ret;
4212 } 4259 }
4213 4260
4214 /* Reference the old fb object for the scheduled work. */ 4261 /* Reference the objects for the scheduled work. */
4215 drm_gem_object_reference(work->obj); 4262 drm_gem_object_reference(work->old_fb_obj);
4263 drm_gem_object_reference(obj);
4216 4264
4217 crtc->fb = fb; 4265 crtc->fb = fb;
4218 i915_gem_object_flush_write_domain(obj); 4266 i915_gem_object_flush_write_domain(obj);
4219 drm_vblank_get(dev, intel_crtc->pipe); 4267 drm_vblank_get(dev, intel_crtc->pipe);
4220 obj_priv = obj->driver_private; 4268 obj_priv = obj->driver_private;
4221 atomic_inc(&obj_priv->pending_flip); 4269 atomic_inc(&obj_priv->pending_flip);
4270 work->pending_flip_obj = obj;
4222 4271
4223 BEGIN_LP_RING(4); 4272 BEGIN_LP_RING(4);
4224 OUT_RING(MI_DISPLAY_FLIP | 4273 OUT_RING(MI_DISPLAY_FLIP |
@@ -4226,7 +4275,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
4226 OUT_RING(fb->pitch); 4275 OUT_RING(fb->pitch);
4227 if (IS_I965G(dev)) { 4276 if (IS_I965G(dev)) {
4228 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode); 4277 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4229 OUT_RING((fb->width << 16) | fb->height); 4278 pipesrc = I915_READ(pipesrc_reg);
4279 OUT_RING(pipesrc & 0x0fff0fff);
4230 } else { 4280 } else {
4231 OUT_RING(obj_priv->gtt_offset); 4281 OUT_RING(obj_priv->gtt_offset);
4232 OUT_RING(MI_NOOP); 4282 OUT_RING(MI_NOOP);
@@ -4400,29 +4450,43 @@ static void intel_setup_outputs(struct drm_device *dev)
4400 bool found = false; 4450 bool found = false;
4401 4451
4402 if (I915_READ(SDVOB) & SDVO_DETECTED) { 4452 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4453 DRM_DEBUG_KMS("probing SDVOB\n");
4403 found = intel_sdvo_init(dev, SDVOB); 4454 found = intel_sdvo_init(dev, SDVOB);
4404 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) 4455 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4456 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4405 intel_hdmi_init(dev, SDVOB); 4457 intel_hdmi_init(dev, SDVOB);
4458 }
4406 4459
4407 if (!found && SUPPORTS_INTEGRATED_DP(dev)) 4460 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4461 DRM_DEBUG_KMS("probing DP_B\n");
4408 intel_dp_init(dev, DP_B); 4462 intel_dp_init(dev, DP_B);
4463 }
4409 } 4464 }
4410 4465
4411 /* Before G4X SDVOC doesn't have its own detect register */ 4466 /* Before G4X SDVOC doesn't have its own detect register */
4412 4467
4413 if (I915_READ(SDVOB) & SDVO_DETECTED) 4468 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4469 DRM_DEBUG_KMS("probing SDVOC\n");
4414 found = intel_sdvo_init(dev, SDVOC); 4470 found = intel_sdvo_init(dev, SDVOC);
4471 }
4415 4472
4416 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { 4473 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4417 4474
4418 if (SUPPORTS_INTEGRATED_HDMI(dev)) 4475 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4476 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4419 intel_hdmi_init(dev, SDVOC); 4477 intel_hdmi_init(dev, SDVOC);
4420 if (SUPPORTS_INTEGRATED_DP(dev)) 4478 }
4479 if (SUPPORTS_INTEGRATED_DP(dev)) {
4480 DRM_DEBUG_KMS("probing DP_C\n");
4421 intel_dp_init(dev, DP_C); 4481 intel_dp_init(dev, DP_C);
4482 }
4422 } 4483 }
4423 4484
4424 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED)) 4485 if (SUPPORTS_INTEGRATED_DP(dev) &&
4486 (I915_READ(DP_D) & DP_DETECTED)) {
4487 DRM_DEBUG_KMS("probing DP_D\n");
4425 intel_dp_init(dev, DP_D); 4488 intel_dp_init(dev, DP_D);
4489 }
4426 } else if (IS_I8XX(dev)) 4490 } else if (IS_I8XX(dev))
4427 intel_dvo_init(dev); 4491 intel_dvo_init(dev);
4428 4492
@@ -4448,9 +4512,7 @@ static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4448 intelfb_remove(dev, fb); 4512 intelfb_remove(dev, fb);
4449 4513
4450 drm_framebuffer_cleanup(fb); 4514 drm_framebuffer_cleanup(fb);
4451 mutex_lock(&dev->struct_mutex); 4515 drm_gem_object_unreference_unlocked(intel_fb->obj);
4452 drm_gem_object_unreference(intel_fb->obj);
4453 mutex_unlock(&dev->struct_mutex);
4454 4516
4455 kfree(intel_fb); 4517 kfree(intel_fb);
4456} 4518}
@@ -4513,9 +4575,7 @@ intel_user_framebuffer_create(struct drm_device *dev,
4513 4575
4514 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj); 4576 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4515 if (ret) { 4577 if (ret) {
4516 mutex_lock(&dev->struct_mutex); 4578 drm_gem_object_unreference_unlocked(obj);
4517 drm_gem_object_unreference(obj);
4518 mutex_unlock(&dev->struct_mutex);
4519 return NULL; 4579 return NULL;
4520 } 4580 }
4521 4581
@@ -4527,6 +4587,127 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
4527 .fb_changed = intelfb_probe, 4587 .fb_changed = intelfb_probe,
4528}; 4588};
4529 4589
4590static struct drm_gem_object *
4591intel_alloc_power_context(struct drm_device *dev)
4592{
4593 struct drm_gem_object *pwrctx;
4594 int ret;
4595
4596 pwrctx = drm_gem_object_alloc(dev, 4096);
4597 if (!pwrctx) {
4598 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4599 return NULL;
4600 }
4601
4602 mutex_lock(&dev->struct_mutex);
4603 ret = i915_gem_object_pin(pwrctx, 4096);
4604 if (ret) {
4605 DRM_ERROR("failed to pin power context: %d\n", ret);
4606 goto err_unref;
4607 }
4608
4609 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4610 if (ret) {
4611 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4612 goto err_unpin;
4613 }
4614 mutex_unlock(&dev->struct_mutex);
4615
4616 return pwrctx;
4617
4618err_unpin:
4619 i915_gem_object_unpin(pwrctx);
4620err_unref:
4621 drm_gem_object_unreference(pwrctx);
4622 mutex_unlock(&dev->struct_mutex);
4623 return NULL;
4624}
4625
4626void ironlake_enable_drps(struct drm_device *dev)
4627{
4628 struct drm_i915_private *dev_priv = dev->dev_private;
4629 u32 rgvmodectl = I915_READ(MEMMODECTL), rgvswctl;
4630 u8 fmax, fmin, fstart, vstart;
4631 int i = 0;
4632
4633 /* 100ms RC evaluation intervals */
4634 I915_WRITE(RCUPEI, 100000);
4635 I915_WRITE(RCDNEI, 100000);
4636
4637 /* Set max/min thresholds to 90ms and 80ms respectively */
4638 I915_WRITE(RCBMAXAVG, 90000);
4639 I915_WRITE(RCBMINAVG, 80000);
4640
4641 I915_WRITE(MEMIHYST, 1);
4642
4643 /* Set up min, max, and cur for interrupt handling */
4644 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4645 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4646 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4647 MEMMODE_FSTART_SHIFT;
4648 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4649 PXVFREQ_PX_SHIFT;
4650
4651 dev_priv->max_delay = fstart; /* can't go to fmax w/o IPS */
4652 dev_priv->min_delay = fmin;
4653 dev_priv->cur_delay = fstart;
4654
4655 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4656
4657 /*
4658 * Interrupts will be enabled in ironlake_irq_postinstall
4659 */
4660
4661 I915_WRITE(VIDSTART, vstart);
4662 POSTING_READ(VIDSTART);
4663
4664 rgvmodectl |= MEMMODE_SWMODE_EN;
4665 I915_WRITE(MEMMODECTL, rgvmodectl);
4666
4667 while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
4668 if (i++ > 100) {
4669 DRM_ERROR("stuck trying to change perf mode\n");
4670 break;
4671 }
4672 msleep(1);
4673 }
4674 msleep(1);
4675
4676 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4677 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4678 I915_WRITE(MEMSWCTL, rgvswctl);
4679 POSTING_READ(MEMSWCTL);
4680
4681 rgvswctl |= MEMCTL_CMD_STS;
4682 I915_WRITE(MEMSWCTL, rgvswctl);
4683}
4684
4685void ironlake_disable_drps(struct drm_device *dev)
4686{
4687 struct drm_i915_private *dev_priv = dev->dev_private;
4688 u32 rgvswctl;
4689 u8 fstart;
4690
4691 /* Ack interrupts, disable EFC interrupt */
4692 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4693 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4694 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4695 I915_WRITE(DEIIR, DE_PCU_EVENT);
4696 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4697
4698 /* Go back to the starting frequency */
4699 fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >>
4700 MEMMODE_FSTART_SHIFT;
4701 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4702 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4703 I915_WRITE(MEMSWCTL, rgvswctl);
4704 msleep(1);
4705 rgvswctl |= MEMCTL_CMD_STS;
4706 I915_WRITE(MEMSWCTL, rgvswctl);
4707 msleep(1);
4708
4709}
4710
4530void intel_init_clock_gating(struct drm_device *dev) 4711void intel_init_clock_gating(struct drm_device *dev)
4531{ 4712{
4532 struct drm_i915_private *dev_priv = dev->dev_private; 4713 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4579,42 +4760,27 @@ void intel_init_clock_gating(struct drm_device *dev)
4579 * GPU can automatically power down the render unit if given a page 4760 * GPU can automatically power down the render unit if given a page
4580 * to save state. 4761 * to save state.
4581 */ 4762 */
4582 if (I915_HAS_RC6(dev)) { 4763 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
4583 struct drm_gem_object *pwrctx; 4764 struct drm_i915_gem_object *obj_priv = NULL;
4584 struct drm_i915_gem_object *obj_priv;
4585 int ret;
4586 4765
4587 if (dev_priv->pwrctx) { 4766 if (dev_priv->pwrctx) {
4588 obj_priv = dev_priv->pwrctx->driver_private; 4767 obj_priv = dev_priv->pwrctx->driver_private;
4589 } else { 4768 } else {
4590 pwrctx = drm_gem_object_alloc(dev, 4096); 4769 struct drm_gem_object *pwrctx;
4591 if (!pwrctx) {
4592 DRM_DEBUG("failed to alloc power context, "
4593 "RC6 disabled\n");
4594 goto out;
4595 }
4596 4770
4597 ret = i915_gem_object_pin(pwrctx, 4096); 4771 pwrctx = intel_alloc_power_context(dev);
4598 if (ret) { 4772 if (pwrctx) {
4599 DRM_ERROR("failed to pin power context: %d\n", 4773 dev_priv->pwrctx = pwrctx;
4600 ret); 4774 obj_priv = pwrctx->driver_private;
4601 drm_gem_object_unreference(pwrctx);
4602 goto out;
4603 } 4775 }
4604
4605 i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4606
4607 dev_priv->pwrctx = pwrctx;
4608 obj_priv = pwrctx->driver_private;
4609 } 4776 }
4610 4777
4611 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN); 4778 if (obj_priv) {
4612 I915_WRITE(MCHBAR_RENDER_STANDBY, 4779 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4613 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT); 4780 I915_WRITE(MCHBAR_RENDER_STANDBY,
4781 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4782 }
4614 } 4783 }
4615
4616out:
4617 return;
4618} 4784}
4619 4785
4620/* Set up chip specific display functions */ 4786/* Set up chip specific display functions */
@@ -4725,11 +4891,6 @@ void intel_modeset_init(struct drm_device *dev)
4725 DRM_DEBUG_KMS("%d display pipe%s available.\n", 4891 DRM_DEBUG_KMS("%d display pipe%s available.\n",
4726 num_pipe, num_pipe > 1 ? "s" : ""); 4892 num_pipe, num_pipe > 1 ? "s" : "");
4727 4893
4728 if (IS_I85X(dev))
4729 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4730 else if (IS_I9XX(dev) || IS_G4X(dev))
4731 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4732
4733 for (i = 0; i < num_pipe; i++) { 4894 for (i = 0; i < num_pipe; i++) {
4734 intel_crtc_init(dev, i); 4895 intel_crtc_init(dev, i);
4735 } 4896 }
@@ -4738,6 +4899,9 @@ void intel_modeset_init(struct drm_device *dev)
4738 4899
4739 intel_init_clock_gating(dev); 4900 intel_init_clock_gating(dev);
4740 4901
4902 if (IS_IRONLAKE_M(dev))
4903 ironlake_enable_drps(dev);
4904
4741 INIT_WORK(&dev_priv->idle_work, intel_idle_update); 4905 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4742 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, 4906 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4743 (unsigned long)dev); 4907 (unsigned long)dev);
@@ -4770,7 +4934,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
4770 del_timer_sync(&intel_crtc->idle_timer); 4934 del_timer_sync(&intel_crtc->idle_timer);
4771 } 4935 }
4772 4936
4773 intel_increase_renderclock(dev, false);
4774 del_timer_sync(&dev_priv->idle_timer); 4937 del_timer_sync(&dev_priv->idle_timer);
4775 4938
4776 if (dev_priv->display.disable_fbc) 4939 if (dev_priv->display.disable_fbc)
@@ -4786,6 +4949,9 @@ void intel_modeset_cleanup(struct drm_device *dev)
4786 drm_gem_object_unreference(dev_priv->pwrctx); 4949 drm_gem_object_unreference(dev_priv->pwrctx);
4787 } 4950 }
4788 4951
4952 if (IS_IRONLAKE_M(dev))
4953 ironlake_disable_drps(dev);
4954
4789 mutex_unlock(&dev->struct_mutex); 4955 mutex_unlock(&dev->struct_mutex);
4790 4956
4791 drm_mode_config_cleanup(dev); 4957 drm_mode_config_cleanup(dev);
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-17 22:01:16 -0400