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path: root/drivers/gpu/drm/i915/i915_suspend.c
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_suspend.c')
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c22
1 files changed, 10 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index d5ebb00a9d49..ac0d1a73ac22 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -682,6 +682,8 @@ void i915_restore_display(struct drm_device *dev)
682 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); 682 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
683 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR); 683 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
684 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL); 684 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
685 I915_WRITE(MCHBAR_RENDER_STANDBY,
686 dev_priv->saveMCHBAR_RENDER_STANDBY);
685 } else { 687 } else {
686 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); 688 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
687 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); 689 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
@@ -732,12 +734,6 @@ int i915_save_state(struct drm_device *dev)
732 734
733 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); 735 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
734 736
735 /* Render Standby */
736 if (I915_HAS_RC6(dev)) {
737 dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
738 dev_priv->savePWRCTXA = I915_READ(PWRCTXA);
739 }
740
741 /* Hardware status page */ 737 /* Hardware status page */
742 dev_priv->saveHWS = I915_READ(HWS_PGA); 738 dev_priv->saveHWS = I915_READ(HWS_PGA);
743 739
@@ -751,11 +747,16 @@ int i915_save_state(struct drm_device *dev)
751 dev_priv->saveGTIMR = I915_READ(GTIMR); 747 dev_priv->saveGTIMR = I915_READ(GTIMR);
752 dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR); 748 dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR);
753 dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR); 749 dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR);
750 dev_priv->saveMCHBAR_RENDER_STANDBY =
751 I915_READ(MCHBAR_RENDER_STANDBY);
754 } else { 752 } else {
755 dev_priv->saveIER = I915_READ(IER); 753 dev_priv->saveIER = I915_READ(IER);
756 dev_priv->saveIMR = I915_READ(IMR); 754 dev_priv->saveIMR = I915_READ(IMR);
757 } 755 }
758 756
757 if (IS_IRONLAKE_M(dev))
758 ironlake_disable_drps(dev);
759
759 /* Cache mode state */ 760 /* Cache mode state */
760 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); 761 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
761 762
@@ -793,12 +794,6 @@ int i915_restore_state(struct drm_device *dev)
793 794
794 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 795 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
795 796
796 /* Render Standby */
797 if (I915_HAS_RC6(dev)) {
798 I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
799 I915_WRITE(PWRCTXA, dev_priv->savePWRCTXA);
800 }
801
802 /* Hardware status page */ 797 /* Hardware status page */
803 I915_WRITE(HWS_PGA, dev_priv->saveHWS); 798 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
804 799
@@ -832,6 +827,9 @@ int i915_restore_state(struct drm_device *dev)
832 /* Clock gating state */ 827 /* Clock gating state */
833 intel_init_clock_gating(dev); 828 intel_init_clock_gating(dev);
834 829
830 if (IS_IRONLAKE_M(dev))
831 ironlake_enable_drps(dev);
832
835 /* Cache mode state */ 833 /* Cache mode state */
836 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); 834 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
837 835