1 files changed, 23 insertions, 13 deletions

diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index e5a256f5429c..f45cd7f147a5 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -133,15 +133,16 @@ enum radeon_cp_microcode_version {
  * Chip flags
  */
 enum radeon_chip_flags {
-        CHIP_FAMILY_MASK = 0x0000ffffUL,
-        CHIP_FLAGS_MASK = 0xffff0000UL,
-        CHIP_IS_MOBILITY = 0x00010000UL,
-        CHIP_IS_IGP = 0x00020000UL,
-        CHIP_SINGLE_CRTC = 0x00040000UL,
-        CHIP_IS_AGP = 0x00080000UL,
-        CHIP_HAS_HIERZ = 0x00100000UL,
-        CHIP_IS_PCIE = 0x00200000UL,
-        CHIP_NEW_MEMMAP = 0x00400000UL,
+        RADEON_FAMILY_MASK = 0x0000ffffUL,
+        RADEON_FLAGS_MASK = 0xffff0000UL,
+        RADEON_IS_MOBILITY = 0x00010000UL,
+        RADEON_IS_IGP = 0x00020000UL,
+        RADEON_SINGLE_CRTC = 0x00040000UL,
+        RADEON_IS_AGP = 0x00080000UL,
+        RADEON_HAS_HIERZ = 0x00100000UL,
+        RADEON_IS_PCIE = 0x00200000UL,
+        RADEON_NEW_MEMMAP = 0x00400000UL,
+        RADEON_IS_PCI = 0x00800000UL,
 };
 
 #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
@@ -424,6 +425,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
 #define RADEON_RB3D_COLOROFFSET         0x1c40
 #define RADEON_RB3D_COLORPITCH          0x1c48
 
+#define RADEON_SRC_X_Y                  0x1590
+
 #define RADEON_DP_GUI_MASTER_CNTL       0x146c
 #       define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
 #       define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
@@ -441,6 +444,7 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
 #       define RADEON_ROP3_S                    0x00cc0000
 #       define RADEON_ROP3_P                    0x00f00000
 #define RADEON_DP_WRITE_MASK            0x16cc
+#define RADEON_SRC_PITCH_OFFSET         0x1428
 #define RADEON_DST_PITCH_OFFSET         0x142c
 #define RADEON_DST_PITCH_OFFSET_C       0x1c80
 #       define RADEON_DST_TILE_LINEAR           (0 << 30)
@@ -545,6 +549,11 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
 #       define RADEON_RB3D_ZC_FREE              (1 << 2)
 #       define RADEON_RB3D_ZC_FLUSH_ALL         0x5
 #       define RADEON_RB3D_ZC_BUSY              (1 << 31)
+#define RADEON_RB3D_DSTCACHE_CTLSTAT    0x325c
+#       define RADEON_RB3D_DC_FLUSH             (3 << 0)
+#       define RADEON_RB3D_DC_FREE              (3 << 2)
+#       define RADEON_RB3D_DC_FLUSH_ALL         0xf
+#       define RADEON_RB3D_DC_BUSY              (1 << 31)
 #define RADEON_RB3D_ZSTENCILCNTL        0x1c2c
 #       define RADEON_Z_TEST_MASK               (7 << 4)
 #       define RADEON_Z_TEST_ALWAYS             (7 << 4)
@@ -681,6 +690,7 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
 #define RADEON_CP_RB_BASE               0x0700
 #define RADEON_CP_RB_CNTL               0x0704
 #       define RADEON_BUF_SWAP_32BIT            (2 << 16)
+#       define RADEON_RB_NO_UPDATE              (1 << 27)
 #define RADEON_CP_RB_RPTR_ADDR          0x070c
 #define RADEON_CP_RB_RPTR               0x0710
 #define RADEON_CP_RB_WPTR               0x0714
@@ -986,13 +996,13 @@ do {									\
 } while (0)
 
 #define RADEON_FLUSH_CACHE() do {                                       \
-        OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) );      \
-        OUT_RING( RADEON_RB2D_DC_FLUSH );                               \
+        OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) );      \
+        OUT_RING( RADEON_RB3D_DC_FLUSH );                               \
 } while (0)
 
 #define RADEON_PURGE_CACHE() do {                                       \
-        OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) );      \
-        OUT_RING( RADEON_RB2D_DC_FLUSH_ALL );                           \
+        OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) );      \
+        OUT_RING( RADEON_RB3D_DC_FLUSH_ALL );                           \
 } while (0)
 
 #define RADEON_FLUSH_ZCACHE() do {                                      \