diff options
Diffstat (limited to 'drivers/block/rsxx/rsxx_priv.h')
-rw-r--r-- | drivers/block/rsxx/rsxx_priv.h | 34 |
1 files changed, 27 insertions, 7 deletions
diff --git a/drivers/block/rsxx/rsxx_priv.h b/drivers/block/rsxx/rsxx_priv.h index a1ac907d8f4c..382e8bf5c03b 100644 --- a/drivers/block/rsxx/rsxx_priv.h +++ b/drivers/block/rsxx/rsxx_priv.h | |||
@@ -45,16 +45,13 @@ | |||
45 | 45 | ||
46 | struct proc_cmd; | 46 | struct proc_cmd; |
47 | 47 | ||
48 | #define PCI_VENDOR_ID_TMS_IBM 0x15B6 | 48 | #define PCI_DEVICE_ID_FS70_FLASH 0x04A9 |
49 | #define PCI_DEVICE_ID_RS70_FLASH 0x0019 | 49 | #define PCI_DEVICE_ID_FS80_FLASH 0x04AA |
50 | #define PCI_DEVICE_ID_RS70D_FLASH 0x001A | ||
51 | #define PCI_DEVICE_ID_RS80_FLASH 0x001C | ||
52 | #define PCI_DEVICE_ID_RS81_FLASH 0x001E | ||
53 | 50 | ||
54 | #define RS70_PCI_REV_SUPPORTED 4 | 51 | #define RS70_PCI_REV_SUPPORTED 4 |
55 | 52 | ||
56 | #define DRIVER_NAME "rsxx" | 53 | #define DRIVER_NAME "rsxx" |
57 | #define DRIVER_VERSION "3.7" | 54 | #define DRIVER_VERSION "4.0" |
58 | 55 | ||
59 | /* Block size is 4096 */ | 56 | /* Block size is 4096 */ |
60 | #define RSXX_HW_BLK_SHIFT 12 | 57 | #define RSXX_HW_BLK_SHIFT 12 |
@@ -67,6 +64,9 @@ struct proc_cmd; | |||
67 | #define RSXX_MAX_OUTSTANDING_CMDS 255 | 64 | #define RSXX_MAX_OUTSTANDING_CMDS 255 |
68 | #define RSXX_CS_IDX_MASK 0xff | 65 | #define RSXX_CS_IDX_MASK 0xff |
69 | 66 | ||
67 | #define STATUS_BUFFER_SIZE8 4096 | ||
68 | #define COMMAND_BUFFER_SIZE8 4096 | ||
69 | |||
70 | #define RSXX_MAX_TARGETS 8 | 70 | #define RSXX_MAX_TARGETS 8 |
71 | 71 | ||
72 | struct dma_tracker_list; | 72 | struct dma_tracker_list; |
@@ -91,6 +91,9 @@ struct rsxx_dma_stats { | |||
91 | u32 discards_failed; | 91 | u32 discards_failed; |
92 | u32 done_rescheduled; | 92 | u32 done_rescheduled; |
93 | u32 issue_rescheduled; | 93 | u32 issue_rescheduled; |
94 | u32 dma_sw_err; | ||
95 | u32 dma_hw_fault; | ||
96 | u32 dma_cancelled; | ||
94 | u32 sw_q_depth; /* Number of DMAs on the SW queue. */ | 97 | u32 sw_q_depth; /* Number of DMAs on the SW queue. */ |
95 | atomic_t hw_q_depth; /* Number of DMAs queued to HW. */ | 98 | atomic_t hw_q_depth; /* Number of DMAs queued to HW. */ |
96 | }; | 99 | }; |
@@ -116,6 +119,7 @@ struct rsxx_dma_ctrl { | |||
116 | struct rsxx_cardinfo { | 119 | struct rsxx_cardinfo { |
117 | struct pci_dev *dev; | 120 | struct pci_dev *dev; |
118 | unsigned int halt; | 121 | unsigned int halt; |
122 | unsigned int eeh_state; | ||
119 | 123 | ||
120 | void __iomem *regmap; | 124 | void __iomem *regmap; |
121 | spinlock_t irq_lock; | 125 | spinlock_t irq_lock; |
@@ -224,6 +228,7 @@ enum rsxx_pci_regmap { | |||
224 | PERF_RD512_HI = 0xac, | 228 | PERF_RD512_HI = 0xac, |
225 | PERF_WR512_LO = 0xb0, | 229 | PERF_WR512_LO = 0xb0, |
226 | PERF_WR512_HI = 0xb4, | 230 | PERF_WR512_HI = 0xb4, |
231 | PCI_RECONFIG = 0xb8, | ||
227 | }; | 232 | }; |
228 | 233 | ||
229 | enum rsxx_intr { | 234 | enum rsxx_intr { |
@@ -237,6 +242,8 @@ enum rsxx_intr { | |||
237 | CR_INTR_DMA5 = 0x00000080, | 242 | CR_INTR_DMA5 = 0x00000080, |
238 | CR_INTR_DMA6 = 0x00000100, | 243 | CR_INTR_DMA6 = 0x00000100, |
239 | CR_INTR_DMA7 = 0x00000200, | 244 | CR_INTR_DMA7 = 0x00000200, |
245 | CR_INTR_ALL_C = 0x0000003f, | ||
246 | CR_INTR_ALL_G = 0x000003ff, | ||
240 | CR_INTR_DMA_ALL = 0x000003f5, | 247 | CR_INTR_DMA_ALL = 0x000003f5, |
241 | CR_INTR_ALL = 0xffffffff, | 248 | CR_INTR_ALL = 0xffffffff, |
242 | }; | 249 | }; |
@@ -253,8 +260,14 @@ enum rsxx_pci_reset { | |||
253 | DMA_QUEUE_RESET = 0x00000001, | 260 | DMA_QUEUE_RESET = 0x00000001, |
254 | }; | 261 | }; |
255 | 262 | ||
263 | enum rsxx_hw_fifo_flush { | ||
264 | RSXX_FLUSH_BUSY = 0x00000002, | ||
265 | RSXX_FLUSH_TIMEOUT = 0x00000004, | ||
266 | }; | ||
267 | |||
256 | enum rsxx_pci_revision { | 268 | enum rsxx_pci_revision { |
257 | RSXX_DISCARD_SUPPORT = 2, | 269 | RSXX_DISCARD_SUPPORT = 2, |
270 | RSXX_EEH_SUPPORT = 3, | ||
258 | }; | 271 | }; |
259 | 272 | ||
260 | enum rsxx_creg_cmd { | 273 | enum rsxx_creg_cmd { |
@@ -360,11 +373,17 @@ int rsxx_dma_setup(struct rsxx_cardinfo *card); | |||
360 | void rsxx_dma_destroy(struct rsxx_cardinfo *card); | 373 | void rsxx_dma_destroy(struct rsxx_cardinfo *card); |
361 | int rsxx_dma_init(void); | 374 | int rsxx_dma_init(void); |
362 | void rsxx_dma_cleanup(void); | 375 | void rsxx_dma_cleanup(void); |
376 | void rsxx_dma_queue_reset(struct rsxx_cardinfo *card); | ||
377 | int rsxx_dma_configure(struct rsxx_cardinfo *card); | ||
363 | int rsxx_dma_queue_bio(struct rsxx_cardinfo *card, | 378 | int rsxx_dma_queue_bio(struct rsxx_cardinfo *card, |
364 | struct bio *bio, | 379 | struct bio *bio, |
365 | atomic_t *n_dmas, | 380 | atomic_t *n_dmas, |
366 | rsxx_dma_cb cb, | 381 | rsxx_dma_cb cb, |
367 | void *cb_data); | 382 | void *cb_data); |
383 | int rsxx_hw_buffers_init(struct pci_dev *dev, struct rsxx_dma_ctrl *ctrl); | ||
384 | int rsxx_eeh_save_issued_dmas(struct rsxx_cardinfo *card); | ||
385 | void rsxx_eeh_cancel_dmas(struct rsxx_cardinfo *card); | ||
386 | int rsxx_eeh_remap_dmas(struct rsxx_cardinfo *card); | ||
368 | 387 | ||
369 | /***** cregs.c *****/ | 388 | /***** cregs.c *****/ |
370 | int rsxx_creg_write(struct rsxx_cardinfo *card, u32 addr, | 389 | int rsxx_creg_write(struct rsxx_cardinfo *card, u32 addr, |
@@ -389,10 +408,11 @@ int rsxx_creg_setup(struct rsxx_cardinfo *card); | |||
389 | void rsxx_creg_destroy(struct rsxx_cardinfo *card); | 408 | void rsxx_creg_destroy(struct rsxx_cardinfo *card); |
390 | int rsxx_creg_init(void); | 409 | int rsxx_creg_init(void); |
391 | void rsxx_creg_cleanup(void); | 410 | void rsxx_creg_cleanup(void); |
392 | |||
393 | int rsxx_reg_access(struct rsxx_cardinfo *card, | 411 | int rsxx_reg_access(struct rsxx_cardinfo *card, |
394 | struct rsxx_reg_access __user *ucmd, | 412 | struct rsxx_reg_access __user *ucmd, |
395 | int read); | 413 | int read); |
414 | void rsxx_eeh_save_issued_creg(struct rsxx_cardinfo *card); | ||
415 | void rsxx_kick_creg_queue(struct rsxx_cardinfo *card); | ||
396 | 416 | ||
397 | 417 | ||
398 | 418 | ||